diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-04 20:04:31 +0000 |
commit | 45711ac2869f955c40be96d8dcbc7201c718dba4 (patch) | |
tree | ef022bec4b6e8bcc11005de34d300e073c60770d | |
parent | 7ea9e31658da4fce9c4a3e30838b82fda8eda287 (diff) | |
download | rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.tar.gz rockbox-45711ac2869f955c40be96d8dcbc7201c718dba4.zip |
Sansa AMS: centralize clock settings in clock-target.h
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/as3525-codec.c | 3 | ||||
-rw-r--r-- | firmware/target/arm/as3525/ata_sd_as3525.c | 7 | ||||
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 64 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | 3 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 32 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-target.h | 4 | ||||
-rw-r--r-- | firmware/target/arm/lcd-ssd1815.c | 3 |
9 files changed, 98 insertions, 24 deletions
diff --git a/firmware/target/arm/as3525/as3525-codec.c b/firmware/target/arm/as3525/as3525-codec.c index 223b52df53..768fb8293f 100644 --- a/firmware/target/arm/as3525/as3525-codec.c +++ b/firmware/target/arm/as3525/as3525-codec.c | |||
@@ -38,6 +38,7 @@ | |||
38 | */ | 38 | */ |
39 | 39 | ||
40 | #include "ascodec-target.h" | 40 | #include "ascodec-target.h" |
41 | #include "clock-target.h" | ||
41 | #include "kernel.h" | 42 | #include "kernel.h" |
42 | #include "as3525.h" | 43 | #include "as3525.h" |
43 | 44 | ||
@@ -68,7 +69,7 @@ void ascodec_init(void) | |||
68 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; | 69 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; |
69 | 70 | ||
70 | /* prescaler for i2c clock */ | 71 | /* prescaler for i2c clock */ |
71 | I2C2_CPSR0 = 60; /* 24 MHz / 400 kHz */ | 72 | I2C2_CPSR0 = CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ); |
72 | I2C2_CPSR1 = 0; /* MSB */ | 73 | I2C2_CPSR1 = 0; /* MSB */ |
73 | 74 | ||
74 | /* set i2c slave address of codec part */ | 75 | /* set i2c slave address of codec part */ |
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c index cb1666c029..b2d8e3c1f3 100644 --- a/firmware/target/arm/as3525/ata_sd_as3525.c +++ b/firmware/target/arm/as3525/ata_sd_as3525.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include "pl180.h" /* SD controller */ | 35 | #include "pl180.h" /* SD controller */ |
36 | #include "pl081.h" /* DMA controller */ | 36 | #include "pl081.h" /* DMA controller */ |
37 | #include "dma-target.h" /* DMA request lines */ | 37 | #include "dma-target.h" /* DMA request lines */ |
38 | #include "clock-target.h" | ||
38 | #include "panic.h" | 39 | #include "panic.h" |
39 | #include "stdbool.h" | 40 | #include "stdbool.h" |
40 | #include "ata_idle_notify.h" | 41 | #include "ata_idle_notify.h" |
@@ -375,7 +376,9 @@ static void init_pl180_controller(const int drive) | |||
375 | MCI_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE; | 376 | MCI_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE; |
376 | 377 | ||
377 | /* set MCLK divider */ | 378 | /* set MCLK divider */ |
378 | mci_set_clock_divider(drive, 200); | 379 | mci_set_clock_divider(drive, |
380 | CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ)); | ||
381 | |||
379 | } | 382 | } |
380 | 383 | ||
381 | int sd_init(void) | 384 | int sd_init(void) |
@@ -384,7 +387,7 @@ int sd_init(void) | |||
384 | 387 | ||
385 | CGU_IDE = (1<<7) /* AHB interface enable */ | | 388 | CGU_IDE = (1<<7) /* AHB interface enable */ | |
386 | (1<<6) /* interface enable */ | | 389 | (1<<6) /* interface enable */ | |
387 | (2<<2) /* clock didiver = 2+1 */ | | 390 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) | |
388 | 1 /* clock source = PLLA */; | 391 | 1 /* clock source = PLLA */; |
389 | 392 | ||
390 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; | 393 | CGU_PERI |= CGU_NAF_CLOCK_ENABLE; |
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h new file mode 100644 index 0000000000..fd8cb021fa --- /dev/null +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright © 2008 Rafaël Carré | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef CLOCK_TARGET_H | ||
22 | #define CLOCK_TARGET_H | ||
23 | |||
24 | /* PLL */ | ||
25 | |||
26 | #define AS3525_PLLA_FREQ 248000000 | ||
27 | #define AS3525_PLLA_SETTING 0x261F | ||
28 | |||
29 | /* CPU */ | ||
30 | |||
31 | /* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */ | ||
32 | #define AS3525_CPU_PREDIV 0 /* div = 1/1 */ | ||
33 | |||
34 | #define CPUFREQ_MAX 248000000 | ||
35 | |||
36 | #define CPUFREQ_DEFAULT 24800000 | ||
37 | |||
38 | #define CPUFREQ_NORMAL 31000000 | ||
39 | |||
40 | /* peripherals */ | ||
41 | |||
42 | #define AS3525_PCLK_FREQ 65000000 | ||
43 | |||
44 | #define AS3525_IDE_FREQ 90000000 | ||
45 | |||
46 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | ||
47 | |||
48 | #define AS3525_I2C_FREQ 400000 | ||
49 | |||
50 | /* LCD controller : varies on the models */ | ||
51 | #if defined(SANSA_CLIP) | ||
52 | #define AS3525_DBOP_FREQ 6000000 | ||
53 | #elif defined(SANSA_M200V4) | ||
54 | #define AS3525_DBOP_FREQ 8000000 | ||
55 | #elif defined(SANSA_FUZE) | ||
56 | #define AS3525_DBOP_FREQ 24000000 | ||
57 | #elif defined(SANSA_E200V2) | ||
58 | #define AS3525_DBOP_FREQ 8000000 | ||
59 | #endif | ||
60 | |||
61 | /* macro for not giving a target clock > at the one provided */ | ||
62 | #define CLK_DIV(ref, target) ((ref + target - 1) / target) | ||
63 | |||
64 | #endif /* CLOCK_TARGET_H */ | ||
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c index 703b7e1307..d746243127 100644 --- a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c +++ b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c | |||
@@ -72,7 +72,7 @@ static void ams3525_dbop_init(void) | |||
72 | { | 72 | { |
73 | int clkdiv = 4 - 1; | 73 | int clkdiv = 4 - 1; |
74 | 74 | ||
75 | CGU_DBOP |= (1<<3) /* clk enable */ | clkdiv /* clkdiv: 3 bits */ ; | 75 | CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
76 | 76 | ||
77 | GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ | 77 | GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ |
78 | GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ | 78 | GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ |
diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c index 6bdee395c0..f157b552e4 100644 --- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c +++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "system.h" | 31 | #include "system.h" |
32 | #include "font.h" | 32 | #include "font.h" |
33 | #include "bidi.h" | 33 | #include "bidi.h" |
34 | #include "clock-target.h" | ||
34 | 35 | ||
35 | static bool display_on = false; /* is the display turned on? */ | 36 | static bool display_on = false; /* is the display turned on? */ |
36 | static bool display_flipped = false; | 37 | static bool display_flipped = false; |
@@ -94,7 +95,7 @@ static void lcd_delay(int x) | |||
94 | /* DBOP initialisation, do what OF does */ | 95 | /* DBOP initialisation, do what OF does */ |
95 | static void ams3525_dbop_init(void) | 96 | static void ams3525_dbop_init(void) |
96 | { | 97 | { |
97 | CGU_DBOP = (1<<3) | (3-1); | 98 | CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
98 | 99 | ||
99 | DBOP_TIMPOL_01 = 0xe167e167; | 100 | DBOP_TIMPOL_01 = 0xe167e167; |
100 | DBOP_TIMPOL_23 = 0xe167006e; | 101 | DBOP_TIMPOL_23 = 0xe167006e; |
diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c index cc61a82c6f..76b74b7c3e 100644 --- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c +++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | |||
@@ -24,6 +24,7 @@ | |||
24 | 24 | ||
25 | #include "cpu.h" | 25 | #include "cpu.h" |
26 | #include "lcd.h" | 26 | #include "lcd.h" |
27 | #include "clock-target.h" | ||
27 | 28 | ||
28 | /* The controller is unknown, but some registers appear to be the same as the | 29 | /* The controller is unknown, but some registers appear to be the same as the |
29 | HD66789R */ | 30 | HD66789R */ |
@@ -49,7 +50,8 @@ static void lcd_delay(int x) | |||
49 | 50 | ||
50 | static void as3525_dbop_init(void) | 51 | static void as3525_dbop_init(void) |
51 | { | 52 | { |
52 | CGU_DBOP = (1<<3); | 53 | CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
54 | |||
53 | DBOP_TIMPOL_01 = 0xe167e167; | 55 | DBOP_TIMPOL_01 = 0xe167e167; |
54 | DBOP_TIMPOL_23 = 0xe167006e; | 56 | DBOP_TIMPOL_23 = 0xe167006e; |
55 | DBOP_CTRL = 0x41008; | 57 | DBOP_CTRL = 0x41008; |
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 0451cb36d2..82a0a01795 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include "panic.h" | 25 | #include "panic.h" |
26 | #include "ascodec-target.h" | 26 | #include "ascodec-target.h" |
27 | #include "dma-target.h" | 27 | #include "dma-target.h" |
28 | #include "clock-target.h" | ||
28 | 29 | ||
29 | #define default_interrupt(name) \ | 30 | #define default_interrupt(name) \ |
30 | extern __attribute__((weak,alias("UIRQ"))) void name (void) | 31 | extern __attribute__((weak,alias("UIRQ"))) void name (void) |
@@ -135,9 +136,6 @@ static void sdram_delay(void) | |||
135 | /* Use the same initialization than OF */ | 136 | /* Use the same initialization than OF */ |
136 | static void sdram_init(void) | 137 | static void sdram_init(void) |
137 | { | 138 | { |
138 | CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */ | ||
139 | CGU_PERI |= (1<<2); /* divider = 2 */ | ||
140 | |||
141 | CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */ | 139 | CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */ |
142 | 140 | ||
143 | MPMC_CONTROL = 0x1; /* enable MPMC */ | 141 | MPMC_CONTROL = 0x1; /* enable MPMC */ |
@@ -201,11 +199,8 @@ static void sdram_init(void) | |||
201 | 199 | ||
202 | void system_init(void) | 200 | void system_init(void) |
203 | { | 201 | { |
204 | #ifdef BOOTLOADER | ||
205 | #if 0 /* the GPIO clock is already enabled by the dualboot function */ | ||
206 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; | ||
207 | #endif | ||
208 | 202 | ||
203 | #ifdef BOOTLOADER /* TODO: makes this work in the main build */ | ||
209 | CGU_PROC = 0; /* fclk 24 MHz */ | 204 | CGU_PROC = 0; /* fclk 24 MHz */ |
210 | CGU_PERI &= ~0x7f; /* pclk 24 MHz */ | 205 | CGU_PERI &= ~0x7f; /* pclk 24 MHz */ |
211 | 206 | ||
@@ -215,10 +210,13 @@ void system_init(void) | |||
215 | "mcr p15, 0, r0, c1, c0 \n" | 210 | "mcr p15, 0, r0, c1, c0 \n" |
216 | : : : "r0" ); | 211 | : : : "r0" ); |
217 | 212 | ||
218 | CGU_PLLA = 0x261F; /* PLLA 248 MHz */ | 213 | CGU_PLLA = AS3525_PLLA_SETTING; |
219 | while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ | 214 | while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ |
220 | 215 | ||
221 | CGU_PROC = 1; /* fclk = PLLA = 248 MHz */ | 216 | CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1; |
217 | |||
218 | CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2) | ||
219 | | 1; /* clk_in = PLLA */ | ||
222 | 220 | ||
223 | asm volatile( | 221 | asm volatile( |
224 | "mov r0, #0 \n" | 222 | "mov r0, #0 \n" |
@@ -230,26 +228,32 @@ void system_init(void) | |||
230 | : : : "r0" ); | 228 | : : : "r0" ); |
231 | 229 | ||
232 | sdram_init(); | 230 | sdram_init(); |
231 | #endif /* BOOTLOADER */ | ||
232 | |||
233 | #if 0 /* the GPIO clock is already enabled by the dualboot function */ | ||
234 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; | ||
235 | #endif | ||
233 | 236 | ||
234 | /* enable timer interface for TIMER1 & TIMER2 */ | 237 | /* enable timer interface for TIMER1 & TIMER2 */ |
235 | CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE; | 238 | CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE; |
236 | 239 | ||
237 | /* enable VIC */ | 240 | /* enable VIC */ |
238 | VIC_INT_ENABLE = 0; /* disable all interrupt lines */ | 241 | VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */ |
239 | CGU_PERI |= CGU_VIC_CLOCK_ENABLE; | 242 | CGU_PERI |= CGU_VIC_CLOCK_ENABLE; |
240 | VIC_INT_SELECT = 0; /* only IRQ, no FIQ */ | 243 | VIC_INT_SELECT = 0; /* only IRQ, no FIQ */ |
241 | #else | 244 | |
245 | dma_init(); | ||
246 | |||
247 | #ifndef BOOTLOADER | ||
242 | /* Disable fast hardware power-off, to use power button normally | 248 | /* Disable fast hardware power-off, to use power button normally |
243 | * We don't need the power button in the bootloader. */ | 249 | * We don't need the power button in the bootloader. */ |
244 | ascodec_init(); | 250 | ascodec_init(); |
245 | ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2)); | 251 | ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2)); |
246 | #endif /* BOOTLOADER */ | 252 | #endif /* !BOOTLOADER */ |
247 | 253 | ||
248 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 254 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
249 | set_cpu_frequency(CPUFREQ_DEFAULT); | 255 | set_cpu_frequency(CPUFREQ_DEFAULT); |
250 | #endif | 256 | #endif |
251 | |||
252 | dma_init(); | ||
253 | } | 257 | } |
254 | 258 | ||
255 | void system_reboot(void) | 259 | void system_reboot(void) |
diff --git a/firmware/target/arm/as3525/system-target.h b/firmware/target/arm/as3525/system-target.h index 53bd4cb1b4..713e96c4b8 100644 --- a/firmware/target/arm/as3525/system-target.h +++ b/firmware/target/arm/as3525/system-target.h | |||
@@ -23,8 +23,6 @@ | |||
23 | 23 | ||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | 25 | ||
26 | #define CPUFREQ_MAX 248000000 | 26 | #include "clock-target.h" /* CPUFREQ_* are defined here */ |
27 | #define CPUFREQ_DEFAULT 24800000 | ||
28 | #define CPUFREQ_NORMAL 31000000 | ||
29 | 27 | ||
30 | #endif /* SYSTEM_TARGET_H */ | 28 | #endif /* SYSTEM_TARGET_H */ |
diff --git a/firmware/target/arm/lcd-ssd1815.c b/firmware/target/arm/lcd-ssd1815.c index 6bbad19ff8..35d8cf2275 100644 --- a/firmware/target/arm/lcd-ssd1815.c +++ b/firmware/target/arm/lcd-ssd1815.c | |||
@@ -71,6 +71,7 @@ | |||
71 | 71 | ||
72 | #if CONFIG_CPU == AS3525 | 72 | #if CONFIG_CPU == AS3525 |
73 | #include "as3525.h" | 73 | #include "as3525.h" |
74 | #include "clock-target.h" | ||
74 | 75 | ||
75 | void lcd_write_command(int byte) | 76 | void lcd_write_command(int byte) |
76 | { | 77 | { |
@@ -102,7 +103,7 @@ void lcd_write_data(const fb_data* p_bytes, int count) | |||
102 | 103 | ||
103 | static inline void ams3525_dbop_init(void) | 104 | static inline void ams3525_dbop_init(void) |
104 | { | 105 | { |
105 | CGU_DBOP |= (1<<3) /* clk enable */ | (3 - 1) /* clkdiv: 3 bits */ ; | 106 | CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); |
106 | 107 | ||
107 | GPIOB_AFSEL = 0x0f; /* DBOP on pin 3:0 */ | 108 | GPIOB_AFSEL = 0x0f; /* DBOP on pin 3:0 */ |
108 | GPIOC_AFSEL = 0xff; /* DBOP on pins 7:0 */ | 109 | GPIOC_AFSEL = 0xff; /* DBOP on pins 7:0 */ |