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authorJack Halpin <jack.halpin@gmail.com>2009-10-25 18:31:44 +0000
committerJack Halpin <jack.halpin@gmail.com>2009-10-25 18:31:44 +0000
commitec43287aa08f7842b93d786c1ef5e019ac1e4ea1 (patch)
treeb7d7cd84eb61bfffe2e382e10c5bff59ccd45057 /firmware/target/arm/as3525/clock-target.h
parente0d8202599cdf79b1b07aceb561e34418b02c067 (diff)
downloadrockbox-ec43287aa08f7842b93d786c1ef5e019ac1e4ea1.tar.gz
rockbox-ec43287aa08f7842b93d786c1ef5e019ac1e4ea1.zip
AMS Sansa: Assume IDECLK is MCLK for the internal SD Disk. Reduce IDECLK to 62 MHz for now to be consistent with MCLK for uSD which is PCLK.
Adjust SD timeouts accordingly. Adjust code in debug-as3525.c to display correct frequencies on system/debug/View disk info page. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23350 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r--firmware/target/arm/as3525/clock-target.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 560e067510..319b9f57f0 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -113,14 +113,15 @@
113 #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ 113 #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
114 #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) 114 #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
115 #define AS3525_I2C_FREQ 400000 115 #define AS3525_I2C_FREQ 400000
116
117 /* For now use same divider for ident frequencies on both internal and uSD cards */
116 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) 118 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
117 #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ 119 #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
118 120
119#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ 121#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
120#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ 122#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
121#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq 123 /* for now use IDECLK == PCLK for consistency */
122 but sd transfers fail on some 124#define AS3525_IDE_FREQ AS3525_PCLK_FREQ /* The OF uses 66MHz maximal freq */
123 players with this limit */
124 125
125//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ 126//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */
126//#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ 127//#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/