From ec43287aa08f7842b93d786c1ef5e019ac1e4ea1 Mon Sep 17 00:00:00 2001 From: Jack Halpin Date: Sun, 25 Oct 2009 18:31:44 +0000 Subject: AMS Sansa: Assume IDECLK is MCLK for the internal SD Disk. Reduce IDECLK to 62 MHz for now to be consistent with MCLK for uSD which is PCLK. Adjust SD timeouts accordingly. Adjust code in debug-as3525.c to display correct frequencies on system/debug/View disk info page. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23350 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'firmware/target/arm/as3525/clock-target.h') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 560e067510..319b9f57f0 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -113,14 +113,15 @@ #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) #define AS3525_I2C_FREQ 400000 + + /* For now use same divider for ident frequencies on both internal and uSD cards */ #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ -#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq - but sd transfers fail on some - players with this limit */ + /* for now use IDECLK == PCLK for consistency */ +#define AS3525_IDE_FREQ AS3525_PCLK_FREQ /* The OF uses 66MHz maximal freq */ //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ -- cgit v1.2.3