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authorMichael Sparmann <theseven@rockbox.org>2011-01-02 23:16:27 +0000
committerMichael Sparmann <theseven@rockbox.org>2011-01-02 23:16:27 +0000
commit152847977a420487d9c3728841101ef708e41373 (patch)
treef4113d0d6f60355d1ba00d78fc96e97a98e4d493 /firmware/export
parent6f40387e742322c4860af2f389a4b531e669801f (diff)
downloadrockbox-152847977a420487d9c3728841101ef708e41373.tar.gz
rockbox-152847977a420487d9c3728841101ef708e41373.zip
New port: iPod Classic (also known as iPod 6G/6.5G/7G)
Major known issues: - No bootloader yet - No support for the first-generation 160GB CE-ATA hard disk drive yet - Audio playback is slow, only FLAC seems to reach realtime git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28953 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r--firmware/export/audiohw.h2
-rw-r--r--firmware/export/config/ipod6g.h246
-rw-r--r--firmware/export/cpu.h5
-rw-r--r--firmware/export/cs42l55.h481
-rw-r--r--firmware/export/cscodec.h27
-rw-r--r--firmware/export/i2c-s5l8702.h32
-rw-r--r--firmware/export/s5l8702.h631
7 files changed, 1423 insertions, 1 deletions
diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h
index 930c671c20..651c9cd254 100644
--- a/firmware/export/audiohw.h
+++ b/firmware/export/audiohw.h
@@ -68,6 +68,8 @@
68#include "jz4740-codec.h" 68#include "jz4740-codec.h"
69#elif defined(HAVE_AK4537) 69#elif defined(HAVE_AK4537)
70#include "ak4537.h" 70#include "ak4537.h"
71#elif defined(HAVE_CS42L55)
72#include "cs42l55.h"
71#endif 73#endif
72#if (CONFIG_PLATFORM & PLATFORM_HOSTED) 74#if (CONFIG_PLATFORM & PLATFORM_HOSTED)
73/* #include <SDL_audio.h> gives errors in other code areas, 75/* #include <SDL_audio.h> gives errors in other code areas,
diff --git a/firmware/export/config/ipod6g.h b/firmware/export/config/ipod6g.h
new file mode 100644
index 0000000000..16cf9afcef
--- /dev/null
+++ b/firmware/export/config/ipod6g.h
@@ -0,0 +1,246 @@
1/*
2 * This config file is for iPod 6G / Classic
3 */
4#define TARGET_TREE /* this target is using the target tree system */
5
6#define IPOD_ARCH 1
7
8/* For Rolo and boot loader */
9#define MODEL_NUMBER 71
10
11#define MODEL_NAME "Apple iPod Classic/6G"
12
13/* define this if you use an ATA controller */
14#define CONFIG_STORAGE STORAGE_ATA
15
16#define HAVE_ATA_DMA
17#define ATA_MAX_UDMA 4
18#define ATA_MAX_MWDMA 2
19
20/* define this if the ATA controller and method of USB access support LBA48 */
21#define HAVE_LBA48
22
23/* define this if you have recording possibility */
24//#define HAVE_RECORDING
25
26/* Define bitmask of input sources - recordable bitmask can be defined
27 explicitly if different */
28#define INPUT_SRC_CAPS (SRC_CAP_LINEIN)
29
30/* define the bitmask of hardware sample rates */
31#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
32 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
33 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
34
35/* define the bitmask of recording sample rates */
36#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
37 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
38 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
39
40/* define this if you have a bitmap LCD display */
41#define HAVE_LCD_BITMAP
42
43/* define this if you can flip your LCD */
44//#define HAVE_LCD_FLIP
45
46/* define this if you have a colour LCD */
47#define HAVE_LCD_COLOR
48
49/* define this if you want album art for this target */
50#define HAVE_ALBUMART
51
52/* define this to enable bitmap scaling */
53#define HAVE_BMP_SCALING
54
55/* define this to enable JPEG decoding */
56#define HAVE_JPEG
57
58/* define this if you can invert the colours on your LCD */
59//#define HAVE_LCD_INVERT
60
61/* LCD stays visible without backlight - simulator hint */
62#define HAVE_TRANSFLECTIVE_LCD
63
64/* define this if you have access to the quickscreen */
65#define HAVE_QUICKSCREEN
66
67/* define this if you have access to the pitchscreen */
68#define HAVE_PITCHSCREEN
69
70/* define this if you would like tagcache to build on this target */
71#define HAVE_TAGCACHE
72
73/* define this if the unit uses a scrollwheel for navigation */
74#define HAVE_SCROLLWHEEL
75#define HAVE_WHEEL_ACCELERATION
76#define WHEEL_ACCEL_START 270
77#define WHEEL_ACCELERATION 3
78
79/* Define this if you can detect headphones */
80#define HAVE_HEADPHONE_DETECTION
81
82/* LCD dimensions */
83#define LCD_WIDTH 320
84#define LCD_HEIGHT 240
85#define LCD_DEPTH 16 /* pseudo 262.144 colors */
86#define LCD_PIXELFORMAT RGB565 /* rgb565 */
87
88/* Define this if the LCD can shut down */
89#define HAVE_LCD_SHUTDOWN
90
91/* Define this if your LCD can be enabled/disabled */
92#define HAVE_LCD_ENABLE
93
94/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
95 should be defined as well. */
96#ifndef BOOTLOADER
97//TODO: #define HAVE_LCD_SLEEP
98//TODO: #define HAVE_LCD_SLEEP_SETTING
99#endif
100
101#define CONFIG_KEYPAD IPOD_4G_PAD
102
103//#define AB_REPEAT_ENABLE
104//#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE
105
106/* Define this to enable morse code input */
107#define HAVE_MORSE_INPUT
108
109/* Define this if you do software codec */
110#define CONFIG_CODEC SWCODEC
111
112/* define this if you have a real-time clock */
113#define CONFIG_RTC RTC_NANO2G
114
115/* Define if the device can wake from an RTC alarm */
116//#define HAVE_RTC_ALARM
117
118#define CONFIG_LCD LCD_IPOD6G
119
120/* Define the type of audio codec */
121#define HAVE_CS42L55
122
123#define HAVE_PCM_DMA_ADDRESS
124
125/* Define this for LCD backlight available */
126#define HAVE_BACKLIGHT
127#define HAVE_BACKLIGHT_BRIGHTNESS
128
129/* Define this if you have a software controlled poweroff */
130#define HAVE_SW_POWEROFF
131
132/* The number of bytes reserved for loadable codecs */
133#define CODEC_SIZE 0x100000
134
135/* The number of bytes reserved for loadable plugins */
136#define PLUGIN_BUFFER_SIZE 0x80000
137
138// TODO: Figure out real values
139#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
140#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
141#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
142#define BATTERY_CAPACITY_INC 10 /* capacity increment */
143#define BATTERY_TYPES_COUNT 1 /* only one type */
144
145/* Hardware controlled charging with monitoring */
146#define CONFIG_CHARGING CHARGING_MONITOR
147
148/* define current usage levels */
149//TODO: #define CURRENT_NORMAL 21 /* playback @48MHz clock, backlight off */
150//TODO: #define CURRENT_BACKLIGHT 23 /* maximum brightness */
151
152/* define this if the unit can be powered or charged via USB */
153#define HAVE_USB_POWER
154
155/* Define this if your LCD can set contrast */
156//#define HAVE_LCD_CONTRAST
157
158/* Define Apple remote tuner */
159//#define CONFIG_TUNER IPOD_REMOTE_TUNER
160//#define HAVE_RDS_CAP
161
162/* The exact type of CPU */
163#define CONFIG_CPU S5L8702
164
165/* I2C interface */
166#define CONFIG_I2C I2C_S5L8702
167
168#define HAVE_USB_CHARGING_ENABLE
169
170/* The size of the flash ROM */
171#define FLASH_SIZE 0x400000
172
173/* Define this to the CPU frequency */
174//TODO: Figure out exact value
175#define CPU_FREQ 216000000
176
177/* define this if the hardware can be powered off while charging */
178#define HAVE_POWEROFF_WHILE_CHARGING
179
180/* Offset ( in the firmware file's header ) to the file CRC */
181#define FIRMWARE_OFFSET_FILE_CRC 0
182
183/* Offset ( in the firmware file's header ) to the real data */
184#define FIRMWARE_OFFSET_FILE_DATA 8
185
186/* Define this if you can read an absolute wheel position */
187#define HAVE_WHEEL_POSITION
188
189/* define this if the device has larger sectors when accessed via USB */
190/* (only relevant in disk.c, fat.c now always supports large virtual sectors) */
191#define MAX_LOG_SECTOR_SIZE 4096
192
193/* define this if the hard drive uses large physical sectors (ATA-7 feature) */
194/* and doesn't handle them in the drive firmware */
195#define MAX_PHYS_SECTOR_SIZE 4096
196
197/* Define this if you have adjustable CPU frequency */
198//TODO: #define HAVE_ADJUSTABLE_CPU_FREQ
199
200#define BOOTFILE_EXT "ipod"
201#define BOOTFILE "rockbox." BOOTFILE_EXT
202#define BOOTDIR "/.rockbox"
203
204/* Alternative bootfile extension - this is for encrypted images */
205#define BOOTFILE_EXT2 "ipodx"
206
207/* Define this for FM radio input available */
208#define HAVE_FMRADIO_IN
209
210/** Port-specific settings **/
211
212#if 0
213/* Main LCD contrast range and defaults */
214#define MIN_CONTRAST_SETTING 1
215#define MAX_CONTRAST_SETTING 30
216#define DEFAULT_CONTRAST_SETTING 19 /* Match boot contrast */
217#endif
218
219/* Main LCD backlight brightness range and defaults */
220#define MIN_BRIGHTNESS_SETTING 1
221#define MAX_BRIGHTNESS_SETTING 0x3f
222#define DEFAULT_BRIGHTNESS_SETTING 0x20
223
224/* USB defines */
225#define HAVE_USBSTACK
226//#define HAVE_USB_HID_MOUSE - broken?
227#define CONFIG_USBOTG USBOTG_S3C6400X
228#define USB_VENDOR_ID 0x05AC
229//TODO: This is still the Nano2G product ID. Figure out the real one.
230#define USB_PRODUCT_ID 0x1260
231#define USB_NUM_ENDPOINTS 5
232#define USE_ROCKBOX_USB
233#define USB_DEVBSS_ATTR __attribute__((aligned(16)))
234
235/* Define this if you can switch on/off the accessory power supply */
236#define HAVE_ACCESSORY_SUPPLY
237//#define IPOD_ACCESSORY_PROTOCOL
238//#define HAVE_SERIAL
239
240/* Define this, if you can switch on/off the lineout */
241#define HAVE_LINEOUT_POWEROFF
242
243#define USB_WRITE_BUFFER_SIZE (1024*64)
244
245/* Define this if a programmable hotkey is mapped */
246#define HAVE_HOTKEY
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index 381830ab52..59d210380b 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -59,9 +59,12 @@
59#ifdef CPU_TCC780X 59#ifdef CPU_TCC780X
60#include "tcc780x.h" 60#include "tcc780x.h"
61#endif 61#endif
62#ifdef CPU_S5L870X 62#if CONFIG_CPU == S5L8700 || CONFIG_CPU == S5L8701
63#include "s5l8700.h" 63#include "s5l8700.h"
64#endif 64#endif
65#if CONFIG_CPU == S5L8702
66#include "s5l8702.h"
67#endif
65#if CONFIG_CPU == JZ4732 68#if CONFIG_CPU == JZ4732
66#include "jz4740.h" 69#include "jz4740.h"
67#endif 70#endif
diff --git a/firmware/export/cs42l55.h b/firmware/export/cs42l55.h
new file mode 100644
index 0000000000..8a6640f7c2
--- /dev/null
+++ b/firmware/export/cs42l55.h
@@ -0,0 +1,481 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: wm8975.h 28159 2010-09-24 22:42:06Z Buschel $
9 *
10 * Copyright (C) 2010 by Michael Sparmann
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef __CS42L55_H__
23#define __CS42L55_H__
24
25/* volume/balance/treble/bass interdependency */
26#define VOLUME_MIN -580
27#define VOLUME_MAX 120
28
29#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP)
30
31extern int tenthdb2master(int db);
32
33extern void audiohw_set_master_vol(int vol_l, int vol_r);
34extern void audiohw_set_lineout_vol(int vol_l, int vol_r);
35extern void audiohw_enable_lineout(bool enable);
36
37/* Register addresses and bits */
38
39#define HIDDENCTL 0x00
40#define HIDDENCTL_LOCK 0x00
41#define HIDDENCTL_UNLOCK 0x99
42
43#define CHIPVERSION 0x01
44
45#define PWRCTL1 0x02
46#define PWRCTL1_PDN_CODEC (1 << 0)
47#define PWRCTL1_PDN_ADCA (1 << 1)
48#define PWRCTL1_PDN_ADCB (1 << 2)
49#define PWRCTL1_PDN_CHRG (1 << 3)
50
51#define PWRCTL2 0x03
52#define PWRCTL2_PDN_LINA_MASK (3 << 0)
53#define PWRCTL2_PDN_LINA_HIGH (0 << 0)
54#define PWRCTL2_PDN_LINA_LOW (1 << 0)
55#define PWRCTL2_PDN_LINA_NEVER (2 << 0)
56#define PWRCTL2_PDN_LINA_ALWAYS (3 << 0)
57#define PWRCTL2_PDN_LINB_MASK (3 << 2)
58#define PWRCTL2_PDN_LINB_HIGH (0 << 2)
59#define PWRCTL2_PDN_LINB_LOW (1 << 2)
60#define PWRCTL2_PDN_LINB_NEVER (2 << 2)
61#define PWRCTL2_PDN_LINB_ALWAYS (3 << 2)
62#define PWRCTL2_PDN_HPA_MASK (3 << 4)
63#define PWRCTL2_PDN_HPA_HIGH (0 << 4)
64#define PWRCTL2_PDN_HPA_LOW (1 << 4)
65#define PWRCTL2_PDN_HPA_NEVER (2 << 4)
66#define PWRCTL2_PDN_HPA_ALWAYS (3 << 4)
67#define PWRCTL2_PDN_HPB_MASK (3 << 6)
68#define PWRCTL2_PDN_HPB_HIGH (0 << 6)
69#define PWRCTL2_PDN_HPB_LOW (1 << 6)
70#define PWRCTL2_PDN_HPB_NEVER (2 << 6)
71#define PWRCTL2_PDN_HPB_ALWAYS (3 << 6)
72
73#define CLKCTL1 0x04
74#define CLKCTL1_MCLKDIS (1 << 0)
75#define CLKCTL1_MCLKDIV2 (1 << 1)
76#define CLKCTL1_SCLKMCLK_MASK (3 << 2)
77#define CLKCTL1_SCLKMCLK_BURST (0 << 2)
78#define CLKCTL1_SCLKMCLK_AFTER (2 << 2)
79#define CLKCTL1_SCLKMCLK_BEFORE (3 << 2)
80#define CLKCTL1_INV_SCLK (1 << 4)
81#define CLKCTL1_MASTER (1 << 5)
82
83#define CLKCTL2 0x05
84#define CLKCTL2_MCLKLRCK_MASK (3 << 0)
85#define CLKCTL2_MCLKLRCK_125 (1 << 0)
86#define CLKCTL2_MCLKLRCK_136 (3 << 0)
87#define CLKCTL2_32KGROUP (1 << 2)
88#define CLKCTL2_SPEED_MASK (3 << 3)
89#define CLKCTL2_SPEED_SINGLE (1 << 3)
90#define CLKCTL2_SPEED_HALF (2 << 3)
91#define CLKCTL2_SPEED_QUARTER (3 << 3)
92#define CLKCTL2_8000HZ 0x1d
93#define CLKCTL2_11025HZ 0x1b
94#define CLKCTL2_12000HZ 0x19
95#define CLKCTL2_16000HZ 0x15
96#define CLKCTL2_22050HZ 0x13
97#define CLKCTL2_24000HZ 0x11
98#define CLKCTL2_32000HZ 0x0d
99#define CLKCTL2_44100HZ 0x0b
100#define CLKCTL2_48000HZ 0x09
101
102#define CLSHCTL 0x06
103#define CLSHCTL_ADPTPWR_MASK (3 << 4)
104#define CLSHCTL_ADPTPWR_VOLUME (0 << 4)
105#define CLSHCTL_ADPTPWR_HALF (1 << 4)
106#define CLSHCTL_ADPTPWR_FULL (2 << 4)
107#define CLSHCTL_ADPTPWR_SIGNAL (3 << 4)
108
109#define MISCCTL 0x07
110#define MISCCTL_FREEZE (1 << 0)
111#define MISCCTL_DIGSFT (1 << 2)
112#define MISCCTL_ANLGZC (1 << 3)
113#define MISCCTL_UNDOC4 (1 << 4)
114#define MISCCTL_DIGMUX (1 << 7)
115
116#define ALHMUX 0x08
117#define ALHMUX_HPAMUX_MASK (1 << 0)
118#define ALHMUX_HPAMUX_DACA (0 << 0)
119#define ALHMUX_HPAMUX_PGAA (1 << 0)
120#define ALHMUX_HPBMUX_MASK (1 << 1)
121#define ALHMUX_HPBMUX_DACB (0 << 1)
122#define ALHMUX_HPBMUX_PGAB (1 << 1)
123#define ALHMUX_LINEAMUX_MASK (1 << 2)
124#define ALHMUX_LINEAMUX_DACA (0 << 2)
125#define ALHMUX_LINEAMUX_PGAA (1 << 2)
126#define ALHMUX_LINEBMUX_MASK (1 << 3)
127#define ALHMUX_LINEBMUX_DACB (0 << 3)
128#define ALHMUX_LINEBMUX_PGAB (1 << 3)
129#define ALHMUX_ADCAMUX_MASK (3 << 4)
130#define ALHMUX_ADCAMUX_PGAA (0 << 4)
131#define ALHMUX_ADCAMUX_AIN1A (1 << 4)
132#define ALHMUX_ADCAMUX_AIN2A (2 << 4)
133#define ALHMUX_ADCBMUX_MASK (3 << 4)
134#define ALHMUX_ADCBMUX_PGAB (0 << 6)
135#define ALHMUX_ADCBMUX_AIN1B (1 << 6)
136#define ALHMUX_ADCBMUX_AIN2B (2 << 6)
137
138#define HPFCTL 0x09
139#define HPFCTL_HPFA_CF_MASK (3 << 0)
140#define HPFCTL_HPFA_CF_1_8 (0 << 0)
141#define HPFCTL_HPFA_CF_119 (1 << 0)
142#define HPFCTL_HPFA_CF_236 (2 << 0)
143#define HPFCTL_HPFA_CF_464 (3 << 0)
144#define HPFCTL_HPFB_CF_MASK (3 << 2)
145#define HPFCTL_HPFB_CF_1_8 (0 << 2)
146#define HPFCTL_HPFB_CF_119 (1 << 2)
147#define HPFCTL_HPFB_CF_236 (2 << 2)
148#define HPFCTL_HPFB_CF_464 (3 << 2)
149#define HPFCTL_HPFRZA (1 << 4)
150#define HPFCTL_HPFA (1 << 5)
151#define HPFCTL_HPFRZB (1 << 6)
152#define HPFCTL_HPFB (1 << 7)
153
154#define ADCCTL 0x0a
155#define ADCCTL_ADCAMUTE (1 << 0)
156#define ADCCTL_ADCBMUTE (1 << 1)
157#define ADCCTL_INV_ADCA (1 << 2)
158#define ADCCTL_INV_ADCB (1 << 3)
159#define ADCCTL_DIGSUM_MASK (3 << 4)
160#define ADCCTL_DIGSUM_NORMAL (0 << 4)
161#define ADCCTL_DIGSUM_HALFSUM (1 << 4)
162#define ADCCTL_DIGSUM_HALFDIFF (2 << 4)
163#define ADCCTL_DIGSUM_SWAPPED (3 << 4)
164#define ADCCTL_PGA_VOLUME_GROUP (1 << 6)
165#define ADCCTL_ADC_VOLUME_GROUP (1 << 7)
166
167#define PGAACTL 0x0b
168#define PGAACTL_VOLUME_MASK (0x3f << 0)
169#define PGAACTL_VOLUME_SHIFT 0
170#define PGAACTL_MUX_MASK (1 << 6)
171#define PGAACTL_MUX_AIN1A (0 << 6)
172#define PGAACTL_MUX_AIN2A (1 << 6)
173#define PGAACTL_BOOST (1 << 7)
174
175#define PGABCTL 0x0c
176#define PGABCTL_VOLUME_MASK (0x3f << 0)
177#define PGABCTL_VOLUME_SHIFT 0
178#define PGABCTL_MUX_MASK (1 << 6)
179#define PGABCTL_MUX_AIN1B (0 << 6)
180#define PGABCTL_MUX_AIN2B (1 << 6)
181#define PGABCTL_BOOST (1 << 7)
182
183#define ADCAATT 0x0d
184#define ADCAATT_VOLUME_MASK (0xff << 0)
185#define ADCAATT_VOLUME_SHIFT 0
186
187#define ADCBATT 0x0e
188#define ADCBATT_VOLUME_MASK (0xff << 0)
189#define ADCBATT_VOLUME_SHIFT 0
190
191#define PLAYCTL 0x0f
192#define PLAYCTL_MSTAMUTE (1 << 0)
193#define PLAYCTL_MSTBMUTE (1 << 1)
194#define PLAYCTL_INV_PCMA (1 << 2)
195#define PLAYCTL_INV_PCMB (1 << 3)
196#define PLAYCTL_PB_VOLUME_GROUP (1 << 4)
197#define PLAYCTL_DEEMPH (1 << 6)
198#define PLAYCTL_PDN_DSP (1 << 7)
199
200#define AMIXACTL 0x10
201#define AMIXACTL_AMIXAVOL_MASK (0x7f << 0)
202#define AMIXACTL_AMIXAVOL_SHIFT 0
203#define AMIXACTL_AMIXAMUTE (1 << 7)
204
205#define AMIXBCTL 0x11
206#define AMIXBCTL_AMIXBVOL_MASK (0x7f << 0)
207#define AMIXBCTL_AMIXBVOL_SHIFT 0
208#define AMIXBCTL_AMIXBMUTE (1 << 7)
209
210#define PMIXACTL 0x12
211#define PMIXACTL_PMIXAVOL_MASK (0x7f << 0)
212#define PMIXACTL_PMIXAVOL_SHIFT 0
213#define PMIXACTL_PMIXAMUTE (1 << 7)
214
215#define PMIXBCTL 0x13
216#define PMIXBCTL_PMIXBVOL_MASK (0x7f << 0)
217#define PMIXBCTL_PMIXBVOL_SHIFT 0
218#define PMIXBCTL_PMIXBMUTE (1 << 7)
219
220#define BEEPFO 0x14
221#define BEEPFO_ONTIME_MASK (0xf << 0)
222#define BEEPFO_ONTIME_86 (0x0 << 0)
223#define BEEPFO_ONTIME_430 (0x1 << 0)
224#define BEEPFO_ONTIME_780 (0x2 << 0)
225#define BEEPFO_ONTIME_1200 (0x3 << 0)
226#define BEEPFO_ONTIME_1500 (0x4 << 0)
227#define BEEPFO_ONTIME_1800 (0x5 << 0)
228#define BEEPFO_ONTIME_2200 (0x6 << 0)
229#define BEEPFO_ONTIME_2500 (0x7 << 0)
230#define BEEPFO_ONTIME_2800 (0x8 << 0)
231#define BEEPFO_ONTIME_3200 (0x9 << 0)
232#define BEEPFO_ONTIME_3500 (0xa << 0)
233#define BEEPFO_ONTIME_3800 (0xb << 0)
234#define BEEPFO_ONTIME_4200 (0xc << 0)
235#define BEEPFO_ONTIME_4500 (0xd << 0)
236#define BEEPFO_ONTIME_4800 (0xe << 0)
237#define BEEPFO_ONTIME_5200 (0xf << 0)
238#define BEEPFO_FREQ_MASK (0xf << 4)
239#define BEEPFO_FREQ_254_76 (0x0 << 4)
240#define BEEPFO_FREQ_509_51 (0x1 << 4)
241#define BEEPFO_FREQ_571_65 (0x2 << 4)
242#define BEEPFO_FREQ_651_04 (0x3 << 4)
243#define BEEPFO_FREQ_689_34 (0x4 << 4)
244#define BEEPFO_FREQ_756_04 (0x5 << 4)
245#define BEEPFO_FREQ_869_45 (0x6 << 4)
246#define BEEPFO_FREQ_976_56 (0x7 << 4)
247#define BEEPFO_FREQ_1019_02 (0x8 << 4)
248#define BEEPFO_FREQ_1171_88 (0x9 << 4)
249#define BEEPFO_FREQ_1302_08 (0xa << 4)
250#define BEEPFO_FREQ_1378_67 (0xb << 4)
251#define BEEPFO_FREQ_1562_50 (0xc << 4)
252#define BEEPFO_FREQ_1674_11 (0xd << 4)
253#define BEEPFO_FREQ_1953_13 (0xe << 4)
254#define BEEPFO_FREQ_2130_68 (0xf << 4)
255
256#define BEEPVO 0x15
257#define BEEPVO_VOLUME_MASK (0x1f << 0)
258#define BEEPVO_VOLUME_SHIFT 0
259#define BEEPVO_OFFTIME_MASK (7 << 5)
260#define BEEPVO_OFFTIME_1230 (0 << 5)
261#define BEEPVO_OFFTIME_2580 (1 << 5)
262#define BEEPVO_OFFTIME_3900 (2 << 5)
263#define BEEPVO_OFFTIME_5200 (3 << 5)
264#define BEEPVO_OFFTIME_6600 (4 << 5)
265#define BEEPVO_OFFTIME_8050 (5 << 5)
266#define BEEPVO_OFFTIME_9350 (6 << 5)
267#define BEEPVO_OFFTIME_10800 (7 << 5)
268
269#define BTCTL 0x16
270#define BTCTL_TCEN (1 << 0)
271#define BTCTL_BASSCF_MASK (3 << 1)
272#define BTCTL_BASSCF_50 (0 << 1)
273#define BTCTL_BASSCF_100 (1 << 1)
274#define BTCTL_BASSCF_200 (2 << 1)
275#define BTCTL_BASSCF_250 (3 << 1)
276#define BTCTL_TREBCF_MASK (3 << 3)
277#define BTCTL_TREBCF_5000 (0 << 3)
278#define BTCTL_TREBCF_7000 (1 << 3)
279#define BTCTL_TREBCF_10000 (2 << 3)
280#define BTCTL_TREBCF_15000 (3 << 3)
281#define BTCTL_BEEP_MASK (0 << 6)
282#define BTCTL_BEEP_OFF (0 << 6)
283#define BTCTL_BEEP_SINGLE (1 << 6)
284#define BTCTL_BEEP_MULTIPLE (2 << 6)
285#define BTCTL_BEEP_CONTINUOUS (3 << 6)
286
287#define TONECTL 0x17
288#define TONECTL_BASS_MASK (0xf << 0)
289#define TONECTL_BASS_SHIFT 0
290#define TONECTL_TREB_MASK (0xf << 4)
291#define TONECTL_TREB_SHIFT 4
292
293#define MSTAVOL 0x18
294#define MSTAVOL_VOLUME_MASK (0xff << 0)
295#define MSTAVOL_VOLUME_SHIFT 0
296
297#define MSTBVOL 0x19
298#define MSTBVOL_VOLUME_MASK (0xff << 0)
299#define MSTBVOL_VOLUME_SHIFT 0
300
301#define HPACTL 0x1a
302#define HPACTL_HPAVOL_MASK (0x7f << 0)
303#define HPACTL_HPAVOL_SHIFT 0
304#define HPACTL_HPAMUTE (1 << 7)
305
306#define HPBCTL 0x1b
307#define HPBCTL_HPBVOL_MASK (0x7f << 0)
308#define HPBCTL_HPBVOL_SHIFT 0
309#define HPBCTL_HPBMUTE (1 << 7)
310
311#define LINEACTL 0x1c
312#define LINEACTL_LINEAVOL_MASK (0x7f << 0)
313#define LINEACTL_LINEAVOL_SHIFT 0
314#define LINEACTL_LINEAMUTE (1 << 7)
315
316#define LINEBCTL 0x1d
317#define LINEBCTL_LINEBVOL_MASK (0x7f << 0)
318#define LINEBCTL_LINEBVOL_SHIFT 0
319#define LINEBCTL_LINEBMUTE (1 << 7)
320
321#define AINADV 0x1e
322#define AINADV_VOLUME_MASK (0xff << 0)
323#define AINADV_VOLUME_SHIFT 0
324
325#define DINADV 0x1f
326#define DINADV_VOLUME_MASK (0xff << 0)
327#define DINADV_VOLUME_SHIFT 0
328
329#define MIXCTL 0x20
330#define MIXCTL_ADCASWP_MASK (3 << 0)
331#define MIXCTL_ADCASWP_NORMAL (0 << 0)
332#define MIXCTL_ADCASWP_HALFSUM (1 << 0)
333#define MIXCTL_ADCASWP_HALFSUM2 (2 << 0)
334#define MIXCTL_ADCASWP_SWAPPED (3 << 0)
335#define MIXCTL_ADCBSWP_MASK (3 << 2)
336#define MIXCTL_ADCBSWP_NORMAL (0 << 2)
337#define MIXCTL_ADCBSWP_HALFSUM (1 << 2)
338#define MIXCTL_ADCBSWP_HALFSUM2 (2 << 2)
339#define MIXCTL_ADCBSWP_SWAPPED (3 << 2)
340#define MIXCTL_PCMASWP_MASK (3 << 4)
341#define MIXCTL_PCMASWP_NORMAL (0 << 4)
342#define MIXCTL_PCMASWP_HALFSUM (1 << 4)
343#define MIXCTL_PCMASWP_HALFSUM2 (2 << 4)
344#define MIXCTL_PCMASWP_SWAPPED (3 << 4)
345#define MIXCTL_PCMBSWP_MASK (3 << 6)
346#define MIXCTL_PCMBSWP_NORMAL (0 << 6)
347#define MIXCTL_PCMBSWP_HALFSUM (1 << 6)
348#define MIXCTL_PCMBSWP_HALFSUM2 (2 << 6)
349#define MIXCTL_PCMBSWP_SWAPPED (3 << 6)
350
351#define LIMCTL1 0x21
352#define LIMCTL1_CUSH_MASK (7 << 2)
353#define LIMCTL1_CUSH_0 (0 << 2)
354#define LIMCTL1_CUSH_3 (1 << 2)
355#define LIMCTL1_CUSH_6 (2 << 2)
356#define LIMCTL1_CUSH_9 (3 << 2)
357#define LIMCTL1_CUSH_12 (4 << 2)
358#define LIMCTL1_CUSH_18 (5 << 2)
359#define LIMCTL1_CUSH_24 (6 << 2)
360#define LIMCTL1_CUSH_30 (7 << 2)
361#define LIMCTL1_LMAX_MASK (7 << 5)
362#define LIMCTL1_LMAX_0 (0 << 5)
363#define LIMCTL1_LMAX_3 (1 << 5)
364#define LIMCTL1_LMAX_6 (2 << 5)
365#define LIMCTL1_LMAX_9 (3 << 5)
366#define LIMCTL1_LMAX_12 (4 << 5)
367#define LIMCTL1_LMAX_18 (5 << 5)
368#define LIMCTL1_LMAX_24 (6 << 5)
369#define LIMCTL1_LMAX_30 (7 << 5)
370
371#define LIMCTL2 0x22
372#define LIMCTL2_LIMRRATE_MASK (0x3f << 0)
373#define LIMCTL2_LIMRRATE_SHIFT 0
374#define LIMCTL2_LIMIT_ALL (1 << 6)
375#define LIMCTL2_LIMIT (1 << 7)
376
377#define LIMCTL3 0x23
378#define LIMCTL3_LIMARATE_MASK (0x3f << 0)
379#define LIMCTL3_LIMARATE_SHIFT 0
380
381#define ALCCTL1 0x24
382#define ALCCTL1_ALCARATE_MASK (0x3f << 0)
383#define ALCCTL1_ALCARATE_SHIFT 0
384#define ALCCTL1_ALCA (1 << 6)
385#define ALCCTL1_ALCB (1 << 7)
386
387#define ALCCTL2 0x25
388#define ALCCTL2_ALCRRATE_MASK (0x3f << 0)
389#define ALCCTL2_ALCRRATE_SHIFT 0
390
391#define ALCCTL3 0x26
392#define ALCCTL3_ALCMIN_MASK (7 << 2)
393#define ALCCTL3_ALCMIN_0 (0 << 2)
394#define ALCCTL3_ALCMIN_3 (1 << 2)
395#define ALCCTL3_ALCMIN_6 (2 << 2)
396#define ALCCTL3_ALCMIN_9 (3 << 2)
397#define ALCCTL3_ALCMIN_12 (4 << 2)
398#define ALCCTL3_ALCMIN_18 (5 << 2)
399#define ALCCTL3_ALCMIN_24 (6 << 2)
400#define ALCCTL3_ALCMIN_30 (7 << 2)
401#define ALCCTL3_ALCMAX_MASK (7 << 5)
402#define ALCCTL3_ALCMAX_0 (0 << 5)
403#define ALCCTL3_ALCMAX_3 (1 << 5)
404#define ALCCTL3_ALCMAX_6 (2 << 5)
405#define ALCCTL3_ALCMAX_9 (3 << 5)
406#define ALCCTL3_ALCMAX_12 (4 << 5)
407#define ALCCTL3_ALCMAX_18 (5 << 5)
408#define ALCCTL3_ALCMAX_24 (6 << 5)
409#define ALCCTL3_ALCMAX_30 (7 << 5)
410
411#define NGCTL 0x27
412#define NGCTL_NGDELEAY_MASK (3 << 0)
413#define NGCTL_NGDELEAY_50 (0 << 0)
414#define NGCTL_NGDELEAY_100 (1 << 0)
415#define NGCTL_NGDELEAY_150 (2 << 0)
416#define NGCTL_NGDELEAY_200 (3 << 0)
417#define NGCTL_THRESH_MASK (7 << 2)
418#define NGCTL_THRESH_SHIFT 2
419#define NGCTL_NG_BOOST30 (1 << 5)
420#define NGCTL_NG (1 << 6)
421#define NGCTL_NGALL (1 << 7)
422
423#define ALSZDIS 0x28
424#define ALSZDIS_LIMSRDIS (1 << 3)
425#define ALSZDIS_ALCAZCDIS (1 << 4)
426#define ALSZDIS_ALCASRDIS (1 << 5)
427#define ALSZDIS_ALCBZCDIS (1 << 6)
428#define ALSZDIS_ALCBSRDIS (1 << 7)
429
430#define STATUS 0x29
431#define STATUS_ADCAOVFL (1 << 0)
432#define STATUS_ADCBOVFL (1 << 1)
433#define STATUS_MIXAOVFL (1 << 2)
434#define STATUS_MIXBOVFL (1 << 3)
435#define STATUS_DSPAOVFL (1 << 4)
436#define STATUS_DSPBOVFL (1 << 5)
437#define STATUS_SPCLKERR (1 << 6)
438#define STATUS_HPDETECT (1 << 7)
439
440#define CPCTL 0x2a
441#define CPCTL_CHGFREQ_MASK (0xf << 0)
442#define CPCTL_CHGFREQ_SHIFT 0
443
444#define HIDDEN2E 0x2e
445#define HIDDEN2E_DEFAULT 0x30
446
447#define HIDDEN32 0x32
448#define HIDDEN32_DEFAULT 0x07
449
450#define HIDDEN33 0x33
451#define HIDDEN33_DEFAULT 0xff
452
453#define HIDDEN34 0x34
454#define HIDDEN34_DEFAULT 0xf8
455
456#define HIDDEN35 0x35
457#define HIDDEN35_DEFAULT 0xdc
458
459#define HIDDEN36 0x36
460#define HIDDEN36_DEFAULT 0xfc
461
462#define HIDDEN37 0x37
463#define HIDDEN37_DEFAULT 0xac
464
465#define HIDDEN3A 0x3a
466#define HIDDEN3A_DEFAULT 0xf8
467
468#define HIDDEN3C 0x3c
469#define HIDDEN3C_DEFAULT 0xd3
470
471#define HIDDEN3D 0x3d
472#define HIDDEN3D_DEFAULT 0x23
473
474#define HIDDEN3E 0x3e
475#define HIDDEN3E_DEFAULT 0x81
476
477#define HIDDEN3F 0x3f
478#define HIDDEN3F_DEFAULT 0x46
479
480
481#endif /* __CS42L55_H__ */
diff --git a/firmware/export/cscodec.h b/firmware/export/cscodec.h
new file mode 100644
index 0000000000..dcf6c30e06
--- /dev/null
+++ b/firmware/export/cscodec.h
@@ -0,0 +1,27 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: wmcodec.h 17847 2008-06-28 18:10:04Z bagder $
9 *
10 * Copyright (C) 2006 by Marcoen Hirschberg
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22unsigned char cscodec_read(int reg);
23void cscodec_write(int reg, unsigned char data);
24void cscodec_power(bool state);
25void cscodec_clock(bool state);
26void cscodec_reset(bool state);
27
diff --git a/firmware/export/i2c-s5l8702.h b/firmware/export/i2c-s5l8702.h
new file mode 100644
index 0000000000..02dc40d89e
--- /dev/null
+++ b/firmware/export/i2c-s5l8702.h
@@ -0,0 +1,32 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: i2c-s5l8700.h 21533 2009-06-27 20:11:11Z bertrik $
9 *
10 * Copyright (C) 2009 by Bertrik Sikken
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef _I2C_S5l8702_H
23#define _I2C_S5l8702_H
24
25#include "config.h"
26
27void i2c_init(void);
28int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data);
29int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data);
30
31#endif /* _I2C_S5l8702_H */
32
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h
new file mode 100644
index 0000000000..9c7b7e1662
--- /dev/null
+++ b/firmware/export/s5l8702.h
@@ -0,0 +1,631 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
9 *
10 * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef __S5L8702_H__
23#define __S5L8702_H__
24
25#include <inttypes.h>
26
27#define REG8_PTR_T volatile uint8_t *
28#define REG16_PTR_T volatile uint16_t *
29#define REG32_PTR_T volatile uint32_t *
30
31//TODO: Figure out
32#define TIMER_FREQ (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */
33
34#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
35
36#define DRAM_ORIG 0x08000000
37#define IRAM_ORIG 0
38
39#define DRAM_SIZE (MEMORYSIZE * 0x100000)
40#define IRAM_SIZE 0x40000
41
42#define TTB_SIZE 0x4000
43#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
44
45/////SYSCON/////
46#define CLKCON0C (*((uint32_t volatile*)(0x3C50000C)))
47#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
48 + ((i) == 4 ? 0x6C : \
49 ((i) == 3 ? 0x68 : \
50 ((i) == 2 ? 0x58 : \
51 ((i) == 1 ? 0x4C : \
52 0x48)))))))
53
54
55/////TIMER/////
56#define TACON (*((uint32_t volatile*)(0x3C700000)))
57#define TACMD (*((uint32_t volatile*)(0x3C700004)))
58#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
59#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
60#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
61#define TACNT (*((uint32_t volatile*)(0x3C700014)))
62#define TBCON (*((uint32_t volatile*)(0x3C700020)))
63#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
64#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
65#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
66#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
67#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
68#define TCCON (*((uint32_t volatile*)(0x3C700040)))
69#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
70#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
71#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
72#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
73#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
74#define TDCON (*((uint32_t volatile*)(0x3C700060)))
75#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
76#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
77#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
78#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
79#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
80#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
81#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
82#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
83#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
84#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
85#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
86#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
87#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
88#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
89#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
90#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
91#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
92#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
93#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
94#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
95#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
96#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
97#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
98#define THCON (*((uint32_t volatile*)(0x3C700100)))
99#define THCMD (*((uint32_t volatile*)(0x3C700104)))
100#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
101#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
102#define THPRE (*((uint32_t volatile*)(0x3C700110)))
103#define THCNT (*((uint32_t volatile*)(0x3C700114)))
104#define USEC_TIMER TFCNT
105
106
107/////USB/////
108#define OTGBASE 0x38400000
109#define PHYBASE 0x3C400000
110#define SYNOPSYSOTG_CLOCK 0
111#define SYNOPSYSOTG_AHBCFG 0x2B
112
113
114/////I2C/////
115#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
116#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
117#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
118#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
119
120
121/////INTERRUPT CONTROLLERS/////
122#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
123#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
124#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
125#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
126#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
127#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
128#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
129#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
130#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
131#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
132#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
133#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
134#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
135#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
136#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
137#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
138#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
139#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
140#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
141#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
142#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
143#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
144#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
145#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
146#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
147#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
148#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
149#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
150#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108)))
151#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C)))
152#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110)))
153#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114)))
154#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118)))
155#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C)))
156#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120)))
157#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124)))
158#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128)))
159#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C)))
160#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130)))
161#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134)))
162#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138)))
163#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C)))
164#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140)))
165#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144)))
166#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148)))
167#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C)))
168#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150)))
169#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154)))
170#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158)))
171#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C)))
172#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160)))
173#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164)))
174#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168)))
175#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C)))
176#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170)))
177#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
178#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
179#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
180#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
181#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
182#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
183#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
184#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
185#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
186#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
187#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
188#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
189#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
190#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
191#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
192#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
193#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
194#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
195#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
196#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
197#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
198#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
199#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
200#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
201#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
202#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
203#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
204#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
205#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
206#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
207#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
208#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
209#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
210#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
211#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
212#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
213#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
214#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
215#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
216#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
217#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
218#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
219#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
220#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
221#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
222#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
223#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
224#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
225#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
226#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
227#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
228#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108)))
229#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C)))
230#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110)))
231#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114)))
232#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118)))
233#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C)))
234#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120)))
235#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124)))
236#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128)))
237#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C)))
238#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130)))
239#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134)))
240#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138)))
241#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C)))
242#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140)))
243#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144)))
244#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148)))
245#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C)))
246#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150)))
247#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154)))
248#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158)))
249#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C)))
250#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160)))
251#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164)))
252#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168)))
253#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C)))
254#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170)))
255#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
256#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
257#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
258#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
259#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
260#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
261#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
262#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
263#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
264#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
265#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
266#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
267#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
268#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
269#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
270#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
271#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
272#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
273#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
274#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
275#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
276#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
277#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
278#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
279#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
280#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
281#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
282#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
283#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
284#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
285#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
286#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
287#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
288#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
289#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
290#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
291#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
292
293
294/////GPIO/////
295#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
296#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
297#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
298#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
299#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
300#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
301#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
302#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
303#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
304#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
305#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
306#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
307#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
308#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
309#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
310#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
311#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
312#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
313#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
314#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
315#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
316#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
317#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
318#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
319#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
320#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
321#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
322#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
323#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
324#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
325#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
326#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
327#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
328#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
329#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
330#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
331#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
332
333
334/////SPI/////
335#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
336 (i) == 1 ? 0x3ce00000 : \
337 0x3c300000)
338#define SPICLKGATE(i) ((i) == 2 ? 0x2f : \
339 (i) == 1 ? 0x2b : \
340 0x22)
341#define SPIDMA(i) ((i) == 2 ? 0xd : \
342 (i) == 1 ? 0xf : \
343 0x5)
344#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
345#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
346#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
347#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
348#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
349#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
350#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
351#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
352#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
353
354
355/////AES/////
356#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
357#define AESGO (*((uint32_t volatile*)(0x38c00004)))
358#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
359#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
360#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
361#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
362#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
363#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
364#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
365#define AESINADDR (*((const void* volatile*)(0x38c00028)))
366#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
367#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
368#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
369#define AESKEY ((uint32_t volatile*)(0x38c0004c))
370#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
371#define AESIV ((uint32_t volatile*)(0x38c00074))
372#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
373#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
374
375
376/////SHA1/////
377#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
378#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
379#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
380#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
381
382
383/////DMA/////
384#ifndef ASM
385struct dma_lli
386{
387 const void* srcaddr;
388 void* dstaddr;
389 const struct dma_lli* nextlli;
390 uint32_t control;
391};
392#endif
393#define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
394#define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
395#define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
396#define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
397#define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
398#define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
399#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
400#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
401#define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
402#define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
403#define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
404#define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
405#define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
406#define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
407#define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
408#define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
409#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
410#define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
411#define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
412#define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
413#define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000)))
414#define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004)))
415#define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008)))
416#define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c)))
417#define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010)))
418#define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014)))
419#define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018)))
420#define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c)))
421#define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020)))
422#define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024)))
423#define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028)))
424#define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c)))
425#define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030)))
426#define DMAC0SYNC (*((uint32_t volatile*)(0x38200034)))
427#define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
428#define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
429#define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c))))
430#define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
431#define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
432#define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
433#define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100)))
434#define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100)))
435#define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104)))
436#define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108)))
437#define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c)))
438#define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110)))
439#define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120)))
440#define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120)))
441#define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124)))
442#define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128)))
443#define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c)))
444#define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130)))
445#define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140)))
446#define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140)))
447#define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144)))
448#define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148)))
449#define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c)))
450#define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150)))
451#define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160)))
452#define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160)))
453#define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164)))
454#define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168)))
455#define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c)))
456#define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170)))
457#define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180)))
458#define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180)))
459#define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184)))
460#define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188)))
461#define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c)))
462#define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190)))
463#define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0)))
464#define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0)))
465#define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4)))
466#define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8)))
467#define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac)))
468#define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0)))
469#define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0)))
470#define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0)))
471#define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4)))
472#define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8)))
473#define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc)))
474#define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0)))
475#define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0)))
476#define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0)))
477#define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4)))
478#define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8)))
479#define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec)))
480#define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0)))
481#define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000)))
482#define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004)))
483#define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008)))
484#define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c)))
485#define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010)))
486#define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014)))
487#define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018)))
488#define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c)))
489#define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020)))
490#define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024)))
491#define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028)))
492#define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c)))
493#define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030)))
494#define DMAC1SYNC (*((uint32_t volatile*)(0x39900034)))
495#define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
496#define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
497#define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c))))
498#define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
499#define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
500#define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
501#define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100)))
502#define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100)))
503#define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104)))
504#define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108)))
505#define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c)))
506#define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110)))
507#define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120)))
508#define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120)))
509#define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124)))
510#define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128)))
511#define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c)))
512#define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130)))
513#define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140)))
514#define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140)))
515#define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144)))
516#define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148)))
517#define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c)))
518#define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150)))
519#define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160)))
520#define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160)))
521#define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164)))
522#define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168)))
523#define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c)))
524#define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170)))
525#define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180)))
526#define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180)))
527#define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184)))
528#define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188)))
529#define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c)))
530#define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190)))
531#define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0)))
532#define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0)))
533#define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4)))
534#define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8)))
535#define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac)))
536#define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0)))
537#define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0)))
538#define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0)))
539#define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4)))
540#define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8)))
541#define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc)))
542#define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0)))
543#define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0)))
544#define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0)))
545#define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4)))
546#define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8)))
547#define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec)))
548#define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0)))
549
550
551/////LCD/////
552#define LCD_BASE (*((uint32_t volatile*)(0x38300000)))
553#define LCD_WCMD (*((uint32_t volatile*)(0x38300004)))
554#define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
555#define LCD_WDATA (*((uint32_t volatile*)(0x38300040)))
556
557
558/////ATA/////
559#define ATA_CCONTROL (*((uint32_t volatile*)(0x38700000)))
560#define ATA_CSTATUS (*((uint32_t volatile*)(0x38700004)))
561#define ATA_CCOMMAND (*((uint32_t volatile*)(0x38700008)))
562#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
563#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
564#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
565#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
566#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
567#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
568#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
569#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
570#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
571#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
572#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
573#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
574#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
575#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
576#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
577#define ATA_DATA ((uint32_t volatile*)(0x38700054))
578#define ATA_ERROR ((uint32_t volatile*)(0x38700058))
579#define ATA_NSECTOR ((uint32_t volatile*)(0x3870005c))
580#define ATA_SECTOR ((uint32_t volatile*)(0x38700060))
581#define ATA_LCYL ((uint32_t volatile*)(0x38700064))
582#define ATA_HCYL ((uint32_t volatile*)(0x38700068))
583#define ATA_SELECT ((uint32_t volatile*)(0x3870006c))
584#define ATA_COMMAND ((uint32_t volatile*)(0x38700070))
585#define ATA_CONTROL ((uint32_t volatile*)(0x38700074))
586#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
587#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
588#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
589#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
590#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
591
592
593/////CLICKWHEEL/////
594#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
595#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
596#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
597#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
598#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
599#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
600#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
601#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
602
603
604/////I2S/////
605#define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000)))
606#define I2STXCON (*((volatile uint32_t*)(0x3CA00004)))
607#define I2STXCOM (*((volatile uint32_t*)(0x3CA00008)))
608#define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010)))
609#define I2SRXCON (*((volatile uint32_t*)(0x3CA00030)))
610#define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034)))
611#define I2SRXDB (*((volatile uint32_t*)(0x3CA00038)))
612#define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C)))
613#define I2S40 (*((volatile uint32_t*)(0x3CA00040)))
614
615
616/////CLOCK GATES/////
617#define CLOCKGATE_USB_1 2
618#define CLOCKGATE_USB_2 35
619
620
621/////INTERRUPTS/////
622#define IRQ_TIMER 8
623#define IRQ_USB_FUNC 19
624#define IRQ_DMAC(d) 16 + d
625#define IRQ_DMAC0 16
626#define IRQ_DMAC1 17
627#define IRQ_WHEEL 23
628#define IRQ_ATA 29
629
630
631#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-06 03:25:00 +0000