diff options
author | Solomon Peachy <pizza@shaftnet.org> | 2020-07-15 19:40:55 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-07-24 21:20:13 +0000 |
commit | 092c340a2062fa98b7387fc5fd63578ddae7d0b6 (patch) | |
tree | 98ec96946eeb2ae709cb0528cc6998e21bb9b290 /firmware/export | |
parent | 17f7cc92c258bc456a27c3e7c5a19c9409851879 (diff) | |
download | rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.tar.gz rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.zip |
[1/4] Remove SH support and all archos targets
This removes all code specific to SH targets
Change-Id: I7980523785d2596e65c06430f4638eec74a06061
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/audiohw.h | 2 | ||||
-rw-r--r-- | firmware/export/audiohw_settings.h | 10 | ||||
-rw-r--r-- | firmware/export/config.h | 48 | ||||
-rw-r--r-- | firmware/export/config/archosfmrecorder.h | 147 | ||||
-rw-r--r-- | firmware/export/config/archosondiofm.h | 147 | ||||
-rw-r--r-- | firmware/export/config/archosondiosp.h | 131 | ||||
-rw-r--r-- | firmware/export/config/archosplayer.h | 111 | ||||
-rw-r--r-- | firmware/export/config/archosrecorder.h | 141 | ||||
-rw-r--r-- | firmware/export/config/archosrecorderv2.h | 147 | ||||
-rw-r--r-- | firmware/export/cpu.h | 3 | ||||
-rw-r--r-- | firmware/export/hwcompat.h | 31 | ||||
-rw-r--r-- | firmware/export/mas35xx.h | 292 | ||||
-rw-r--r-- | firmware/export/mascodec.h | 45 | ||||
-rw-r--r-- | firmware/export/mp3_playback.h | 9 | ||||
-rw-r--r-- | firmware/export/rtc.h | 10 | ||||
-rw-r--r-- | firmware/export/s1a0903x01.h | 42 | ||||
-rw-r--r-- | firmware/export/sh7034.h | 376 | ||||
-rw-r--r-- | firmware/export/sound.h | 11 | ||||
-rw-r--r-- | firmware/export/tuner.h | 9 | ||||
-rw-r--r-- | firmware/export/usb.h | 8 |
20 files changed, 9 insertions, 1711 deletions
diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h index f22e72554d..490c8fc571 100644 --- a/firmware/export/audiohw.h +++ b/firmware/export/audiohw.h | |||
@@ -184,8 +184,6 @@ struct sound_settings_info | |||
184 | #include "tlv320.h" | 184 | #include "tlv320.h" |
185 | #elif defined(HAVE_AS3514) | 185 | #elif defined(HAVE_AS3514) |
186 | #include "as3514.h" | 186 | #include "as3514.h" |
187 | #elif defined(HAVE_MAS35XX) | ||
188 | #include "mas35xx.h" | ||
189 | #if defined(HAVE_DAC3550A) | 187 | #if defined(HAVE_DAC3550A) |
190 | #include "dac3550a.h" | 188 | #include "dac3550a.h" |
191 | #endif /* HAVE_DAC3550A */ | 189 | #endif /* HAVE_DAC3550A */ |
diff --git a/firmware/export/audiohw_settings.h b/firmware/export/audiohw_settings.h index 675ec59a7b..1d3e0dc12f 100644 --- a/firmware/export/audiohw_settings.h +++ b/firmware/export/audiohw_settings.h | |||
@@ -84,16 +84,6 @@ AUDIOHW_SETTINGS( | |||
84 | AUDIOHW_SETTING_ENT(BALANCE, sound_set_balance) | 84 | AUDIOHW_SETTING_ENT(BALANCE, sound_set_balance) |
85 | AUDIOHW_SETTING_ENT(CHANNELS, sound_set_channels) | 85 | AUDIOHW_SETTING_ENT(CHANNELS, sound_set_channels) |
86 | AUDIOHW_SETTING_ENT(STEREO_WIDTH, sound_set_stereo_width) | 86 | AUDIOHW_SETTING_ENT(STEREO_WIDTH, sound_set_stereo_width) |
87 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) | ||
88 | AUDIOHW_SETTING_ENT(LOUDNESS, sound_set_loudness) | ||
89 | AUDIOHW_SETTING_ENT(AVC, sound_set_avc) | ||
90 | AUDIOHW_SETTING_ENT(MDB_STRENGTH, sound_set_mdb_strength) | ||
91 | AUDIOHW_SETTING_ENT(MDB_HARMONICS, sound_set_mdb_harmonics) | ||
92 | AUDIOHW_SETTING_ENT(MDB_CENTER, sound_set_mdb_center) | ||
93 | AUDIOHW_SETTING_ENT(MDB_SHAPE, sound_set_mdb_shape) | ||
94 | AUDIOHW_SETTING_ENT(MDB_ENABLE, sound_set_mdb_enable) | ||
95 | AUDIOHW_SETTING_ENT(SUPERBASS, sound_set_superbass) | ||
96 | #endif /* (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) */ | ||
97 | #if defined(AUDIOHW_HAVE_LIN_GAIN) | 87 | #if defined(AUDIOHW_HAVE_LIN_GAIN) |
98 | AUDIOHW_SETTING_ENT(LEFT_GAIN, NULL) | 88 | AUDIOHW_SETTING_ENT(LEFT_GAIN, NULL) |
99 | AUDIOHW_SETTING_ENT(RIGHT_GAIN, NULL) | 89 | AUDIOHW_SETTING_ENT(RIGHT_GAIN, NULL) |
diff --git a/firmware/export/config.h b/firmware/export/config.h index 4f9cd02097..6ce9bede41 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -44,7 +44,6 @@ | |||
44 | #define STORAGE_HOSTFS (1 << STORAGE_HOSTFS_NUM) | 44 | #define STORAGE_HOSTFS (1 << STORAGE_HOSTFS_NUM) |
45 | 45 | ||
46 | /* CONFIG_TUNER (note these are combineable bit-flags) */ | 46 | /* CONFIG_TUNER (note these are combineable bit-flags) */ |
47 | #define S1A0903X01 0x01 /* Samsung */ | ||
48 | #define TEA5767 0x02 /* Philips */ | 47 | #define TEA5767 0x02 /* Philips */ |
49 | #define LV24020LP 0x04 /* Sanyo */ | 48 | #define LV24020LP 0x04 /* Sanyo */ |
50 | #define SI4700 0x08 /* Silicon Labs */ | 49 | #define SI4700 0x08 /* Silicon Labs */ |
@@ -55,13 +54,9 @@ | |||
55 | #define STFM1000 0x100 /* Sigmatel */ | 54 | #define STFM1000 0x100 /* Sigmatel */ |
56 | 55 | ||
57 | /* CONFIG_CODEC */ | 56 | /* CONFIG_CODEC */ |
58 | #define MAS3587F 3587 | ||
59 | #define MAS3507D 3507 | ||
60 | #define MAS3539F 3539 | ||
61 | #define SWCODEC 1 /* if codec is done by SW */ | 57 | #define SWCODEC 1 /* if codec is done by SW */ |
62 | 58 | ||
63 | /* CONFIG_CPU */ | 59 | /* CONFIG_CPU */ |
64 | #define SH7034 7034 | ||
65 | #define MCF5249 5249 | 60 | #define MCF5249 5249 |
66 | #define MCF5250 5250 | 61 | #define MCF5250 5250 |
67 | #define PP5002 5002 | 62 | #define PP5002 5002 |
@@ -103,9 +98,6 @@ | |||
103 | #define PLATFORM_PANDORA (1<<6) | 98 | #define PLATFORM_PANDORA (1<<6) |
104 | 99 | ||
105 | /* CONFIG_KEYPAD */ | 100 | /* CONFIG_KEYPAD */ |
106 | #define PLAYER_PAD 1 | ||
107 | #define RECORDER_PAD 2 | ||
108 | #define ONDIO_PAD 3 | ||
109 | #define IRIVER_H100_PAD 4 | 101 | #define IRIVER_H100_PAD 4 |
110 | #define IRIVER_H300_PAD 5 | 102 | #define IRIVER_H300_PAD 5 |
111 | #define IAUDIO_X5M5_PAD 6 | 103 | #define IAUDIO_X5M5_PAD 6 |
@@ -222,8 +214,7 @@ | |||
222 | if the estimation is better that ours | 214 | if the estimation is better that ours |
223 | (which it probably is) */ | 215 | (which it probably is) */ |
224 | /* CONFIG_LCD */ | 216 | /* CONFIG_LCD */ |
225 | #define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */ | 217 | #define LCD_SSD1815 1 /* as used by Sansa M200 and others */ |
226 | #define LCD_SSD1801 2 /* as used by Archos Player/Studio */ | ||
227 | #define LCD_S1D15E06 3 /* as used by iRiver H100 series */ | 218 | #define LCD_S1D15E06 3 /* as used by iRiver H100 series */ |
228 | #define LCD_H300 4 /* as used by iRiver H300 series, exact model name is | 219 | #define LCD_H300 4 /* as used by iRiver H300 series, exact model name is |
229 | unknown at the time of this writing */ | 220 | unknown at the time of this writing */ |
@@ -312,8 +303,6 @@ | |||
312 | /* CONFIG_I2C */ | 303 | /* CONFIG_I2C */ |
313 | #define I2C_NONE 0 /* For targets that do not use I2C - as the | 304 | #define I2C_NONE 0 /* For targets that do not use I2C - as the |
314 | Lyre prototype 1 */ | 305 | Lyre prototype 1 */ |
315 | #define I2C_PLAYREC 1 /* Archos Player/Recorder style */ | ||
316 | #define I2C_ONDIO 2 /* Ondio style */ | ||
317 | #define I2C_COLDFIRE 3 /* Coldfire style */ | 306 | #define I2C_COLDFIRE 3 /* Coldfire style */ |
318 | #define I2C_PP5002 4 /* PP5002 style */ | 307 | #define I2C_PP5002 4 /* PP5002 style */ |
319 | #define I2C_PP5020 5 /* PP5020 style */ | 308 | #define I2C_PP5020 5 /* PP5020 style */ |
@@ -345,7 +334,6 @@ Lyre prototype 1 */ | |||
345 | #define NAND_IMX233 6 | 334 | #define NAND_IMX233 6 |
346 | 335 | ||
347 | /* CONFIG_RTC */ | 336 | /* CONFIG_RTC */ |
348 | #define RTC_M41ST84W 1 /* Archos Recorder */ | ||
349 | #define RTC_PCF50605 2 /* iPod 3G, 4G & Mini */ | 337 | #define RTC_PCF50605 2 /* iPod 3G, 4G & Mini */ |
350 | #define RTC_PCF50606 3 /* iriver H300 */ | 338 | #define RTC_PCF50606 3 /* iriver H300 */ |
351 | #define RTC_S3C2440 4 | 339 | #define RTC_S3C2440 4 |
@@ -398,19 +386,7 @@ Lyre prototype 1 */ | |||
398 | #define IMX233_CREATIVE (1 << 1) /* Creative MBLK windowing */ | 386 | #define IMX233_CREATIVE (1 << 1) /* Creative MBLK windowing */ |
399 | 387 | ||
400 | /* now go and pick yours */ | 388 | /* now go and pick yours */ |
401 | #if defined(ARCHOS_PLAYER) | 389 | #if defined(IRIVER_H100) |
402 | #include "config/archosplayer.h" | ||
403 | #elif defined(ARCHOS_RECORDER) | ||
404 | #include "config/archosrecorder.h" | ||
405 | #elif defined(ARCHOS_FMRECORDER) | ||
406 | #include "config/archosfmrecorder.h" | ||
407 | #elif defined(ARCHOS_RECORDERV2) | ||
408 | #include "config/archosrecorderv2.h" | ||
409 | #elif defined(ARCHOS_ONDIOSP) | ||
410 | #include "config/archosondiosp.h" | ||
411 | #elif defined(ARCHOS_ONDIOFM) | ||
412 | #include "config/archosondiofm.h" | ||
413 | #elif defined(IRIVER_H100) | ||
414 | #include "config/iriverh100.h" | 390 | #include "config/iriverh100.h" |
415 | #elif defined(IRIVER_H120) | 391 | #elif defined(IRIVER_H120) |
416 | #include "config/iriverh120.h" | 392 | #include "config/iriverh120.h" |
@@ -659,11 +635,6 @@ Lyre prototype 1 */ | |||
659 | 635 | ||
660 | #ifndef __PCTOOL__ | 636 | #ifndef __PCTOOL__ |
661 | 637 | ||
662 | /* define for all cpus from SH family */ | ||
663 | #if (ARCH == ARCH_SH) && (CONFIG_CPU == SH7034) | ||
664 | #define CPU_SH | ||
665 | #endif | ||
666 | |||
667 | /* define for all cpus from coldfire family */ | 638 | /* define for all cpus from coldfire family */ |
668 | #if (ARCH == ARCH_M68K) && ((CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250)) | 639 | #if (ARCH == ARCH_M68K) && ((CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250)) |
669 | #define CPU_COLDFIRE | 640 | #define CPU_COLDFIRE |
@@ -932,11 +903,6 @@ Lyre prototype 1 */ | |||
932 | #define HAVE_PICTUREFLOW_INTEGRATION | 903 | #define HAVE_PICTUREFLOW_INTEGRATION |
933 | #endif | 904 | #endif |
934 | 905 | ||
935 | /* Add one HAVE_ define for all mas35xx targets */ | ||
936 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3507D) || (CONFIG_CODEC == MAS3539F) | ||
937 | #define HAVE_MAS35XX | ||
938 | #endif | ||
939 | |||
940 | #if (CONFIG_CODEC == SWCODEC) | 906 | #if (CONFIG_CODEC == SWCODEC) |
941 | #ifdef BOOTLOADER | 907 | #ifdef BOOTLOADER |
942 | 908 | ||
@@ -1012,7 +978,7 @@ Lyre prototype 1 */ | |||
1012 | #endif /* (CONFIG_CODEC == SWCODEC) */ | 978 | #endif /* (CONFIG_CODEC == SWCODEC) */ |
1013 | 979 | ||
1014 | /* Determine if accesses should be strictly long aligned. */ | 980 | /* Determine if accesses should be strictly long aligned. */ |
1015 | #if (CONFIG_CPU == SH7034) || defined(CPU_ARM) || defined(CPU_MIPS) | 981 | #if defined(CPU_ARM) || defined(CPU_MIPS) |
1016 | #define ROCKBOX_STRICT_ALIGN 1 | 982 | #define ROCKBOX_STRICT_ALIGN 1 |
1017 | #endif | 983 | #endif |
1018 | 984 | ||
@@ -1061,8 +1027,7 @@ Lyre prototype 1 */ | |||
1061 | 1027 | ||
1062 | /* IRAM usage */ | 1028 | /* IRAM usage */ |
1063 | #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && /* Not for hosted environments */ \ | 1029 | #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && /* Not for hosted environments */ \ |
1064 | (((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \ | 1030 | (defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ |
1065 | defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ | ||
1066 | defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ | 1031 | defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ |
1067 | (CONFIG_CPU == AS3525 && MEMORYSIZE > 2 && !defined(BOOTLOADER)) || /* AS3525 +2MB: core, plugins, codecs */ \ | 1032 | (CONFIG_CPU == AS3525 && MEMORYSIZE > 2 && !defined(BOOTLOADER)) || /* AS3525 +2MB: core, plugins, codecs */ \ |
1068 | (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC) && !defined(BOOTLOADER)) || /* AS3525 2MB: core only */ \ | 1033 | (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC) && !defined(BOOTLOADER)) || /* AS3525 2MB: core only */ \ |
@@ -1077,7 +1042,7 @@ Lyre prototype 1 */ | |||
1077 | #define IDATA_ATTR __attribute__ ((section(".idata"))) | 1042 | #define IDATA_ATTR __attribute__ ((section(".idata"))) |
1078 | #define IBSS_ATTR __attribute__ ((section(".ibss"))) | 1043 | #define IBSS_ATTR __attribute__ ((section(".ibss"))) |
1079 | #define USE_IRAM | 1044 | #define USE_IRAM |
1080 | #if CONFIG_CPU != SH7034 && (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) \ | 1045 | #if (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) \ |
1081 | && CONFIG_CPU != JZ4732 && CONFIG_CPU != JZ4760B && CONFIG_CPU != AS3525v2 && CONFIG_CPU != IMX233 | 1046 | && CONFIG_CPU != JZ4732 && CONFIG_CPU != JZ4760B && CONFIG_CPU != AS3525v2 && CONFIG_CPU != IMX233 |
1082 | #define PLUGIN_USE_IRAM | 1047 | #define PLUGIN_USE_IRAM |
1083 | #endif | 1048 | #endif |
@@ -1283,8 +1248,7 @@ Lyre prototype 1 */ | |||
1283 | #define HAVE_PCM_FULL_DUPLEX | 1248 | #define HAVE_PCM_FULL_DUPLEX |
1284 | #endif | 1249 | #endif |
1285 | 1250 | ||
1286 | #if (CONFIG_CODEC == SWCODEC) || (CONFIG_CODEC == MAS3587F) || \ | 1251 | #if (CONFIG_CODEC == SWCODEC) |
1287 | (CONFIG_CODEC == MAS3539F) | ||
1288 | #define HAVE_PITCHCONTROL | 1252 | #define HAVE_PITCHCONTROL |
1289 | #endif | 1253 | #endif |
1290 | 1254 | ||
diff --git a/firmware/export/config/archosfmrecorder.h b/firmware/export/config/archosfmrecorder.h deleted file mode 100644 index 0c64d70be4..0000000000 --- a/firmware/export/config/archosfmrecorder.h +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | /* define this if you use an ATA controller */ | ||
2 | #define CONFIG_STORAGE STORAGE_ATA | ||
3 | |||
4 | #define MODEL_NAME "Archos FM Recorder" | ||
5 | |||
6 | /* define this if you have recording possibility */ | ||
7 | #define HAVE_RECORDING | ||
8 | |||
9 | /* Define bitmask of input sources - recordable bitmask can be defined | ||
10 | explicitly if different */ | ||
11 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) | ||
12 | |||
13 | /* define this if you have a bitmap LCD display */ | ||
14 | #define HAVE_LCD_BITMAP | ||
15 | |||
16 | /* define this if you can flip your LCD */ | ||
17 | #define HAVE_LCD_FLIP | ||
18 | |||
19 | /* define this if you can invert the colours on your LCD */ | ||
20 | #define HAVE_LCD_INVERT | ||
21 | |||
22 | /* define this if you have access to the quickscreen */ | ||
23 | #define HAVE_QUICKSCREEN | ||
24 | |||
25 | /* define this if you have the button bar */ | ||
26 | #define HAVE_BUTTONBAR | ||
27 | |||
28 | /* define this if you would like tagcache to build on this target */ | ||
29 | #define HAVE_TAGCACHE | ||
30 | |||
31 | /* LCD dimensions */ | ||
32 | #define LCD_WIDTH 112 | ||
33 | #define LCD_HEIGHT 64 | ||
34 | /* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ | ||
35 | #define LCD_DPI 85 | ||
36 | #define LCD_DEPTH 1 | ||
37 | |||
38 | #define LCD_PIXEL_ASPECT_WIDTH 4 | ||
39 | #define LCD_PIXEL_ASPECT_HEIGHT 5 | ||
40 | |||
41 | #define LCD_PIXELFORMAT VERTICAL_PACKING | ||
42 | |||
43 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
44 | #define LCD_DARKCOLOR 0x000000 | ||
45 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
46 | #define LCD_BL_DARKCOLOR 0x000000 | ||
47 | #define LCD_BL_BRIGHTCOLOR 0x7ee57e | ||
48 | |||
49 | /* define this if you have a Recorder style 10-key keyboard */ | ||
50 | #define CONFIG_KEYPAD RECORDER_PAD | ||
51 | |||
52 | /* Define this to enable morse code input */ | ||
53 | #define HAVE_MORSE_INPUT | ||
54 | |||
55 | /* define this if you have a real-time clock */ | ||
56 | #define CONFIG_RTC RTC_M41ST84W | ||
57 | |||
58 | /* FM recorders can wake up from RTC alarm */ | ||
59 | #define HAVE_RTC_ALARM | ||
60 | |||
61 | /* define this if you have RTC RAM available for settings */ | ||
62 | #define HAVE_RTC_RAM | ||
63 | |||
64 | /* Define this if you have a software controlled poweroff */ | ||
65 | #define HAVE_SW_POWEROFF | ||
66 | |||
67 | /* The number of bytes reserved for loadable plugins */ | ||
68 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
69 | |||
70 | #ifndef BOOTLOADER | ||
71 | /* Define this if you have an FM Radio */ | ||
72 | #define CONFIG_TUNER S1A0903X01 | ||
73 | #endif | ||
74 | |||
75 | #define AB_REPEAT_ENABLE | ||
76 | |||
77 | /* Define this if you have a MAS3587F */ | ||
78 | #define CONFIG_CODEC MAS3587F | ||
79 | |||
80 | /* Define this for LCD backlight available */ | ||
81 | #define HAVE_BACKLIGHT | ||
82 | |||
83 | /* define this if you have a disk storage, i.e. something | ||
84 | that needs spinups and can cause skips when shaked */ | ||
85 | #define HAVE_DISK_STORAGE | ||
86 | |||
87 | #define CONFIG_I2C I2C_PLAYREC | ||
88 | |||
89 | #define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */ | ||
90 | #define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */ | ||
91 | #define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ | ||
92 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
93 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
94 | |||
95 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
96 | |||
97 | #define CURRENT_NORMAL 145 /* usual current in mA */ | ||
98 | #define CURRENT_RECORD 35 /* additional recording current */ | ||
99 | #define CURRENT_USB 500 /* usual current in mA in USB mode */ | ||
100 | |||
101 | /* Hardware controlled charging with monitoring */ | ||
102 | #define CONFIG_CHARGING CHARGING_MONITOR | ||
103 | |||
104 | /* define this if the unit can be powered or charged via USB */ | ||
105 | #define HAVE_USB_POWER | ||
106 | |||
107 | /* Define this if you have a SH7034 */ | ||
108 | #define CONFIG_CPU SH7034 | ||
109 | |||
110 | /* Define this if you have a FM Recorder key system */ | ||
111 | #define HAVE_FMADC | ||
112 | |||
113 | /* Define this if battery voltage can only be measured with ATA powered */ | ||
114 | #define NEED_ATA_POWER_BATT_MEASURE | ||
115 | |||
116 | /* Define this to the CPU frequency */ | ||
117 | #define CPU_FREQ 11059200 | ||
118 | |||
119 | /* Offset ( in the firmware file's header ) to the file length */ | ||
120 | #define FIRMWARE_OFFSET_FILE_LENGTH 20 | ||
121 | |||
122 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
123 | #define FIRMWARE_OFFSET_FILE_CRC 6 | ||
124 | |||
125 | /* Offset ( in the firmware file's header ) to the real data */ | ||
126 | #define FIRMWARE_OFFSET_FILE_DATA 24 | ||
127 | |||
128 | /* The start address index for ROM builds */ | ||
129 | /* #define ROM_START 0x14010 for behind original Archos */ | ||
130 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
131 | |||
132 | /* Software controlled LED */ | ||
133 | #define CONFIG_LED LED_REAL | ||
134 | |||
135 | #define CONFIG_LCD LCD_SSD1815 | ||
136 | |||
137 | #define BOOTFILE_EXT "ajz" | ||
138 | #define BOOTFILE "ajbrec." BOOTFILE_EXT | ||
139 | #define BOOTDIR "/" | ||
140 | |||
141 | #define HAVE_LCD_CONTRAST | ||
142 | |||
143 | #define MIN_CONTRAST_SETTING 5 | ||
144 | #define MAX_CONTRAST_SETTING 63 | ||
145 | |||
146 | /* Define this if a programmable hotkey is mapped */ | ||
147 | #define HAVE_HOTKEY | ||
diff --git a/firmware/export/config/archosondiofm.h b/firmware/export/config/archosondiofm.h deleted file mode 100644 index 68ecc217c1..0000000000 --- a/firmware/export/config/archosondiofm.h +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | /* define this if you have recording possibility */ | ||
2 | #define HAVE_RECORDING | ||
3 | |||
4 | #define MODEL_NAME "Ondio FM" | ||
5 | |||
6 | #define ONDIO_SERIES | ||
7 | |||
8 | /* Define bitmask of input sources - recordable bitmask can be defined | ||
9 | explicitly if different */ | ||
10 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN) | ||
11 | |||
12 | /* define this if you have a bitmap LCD display */ | ||
13 | #define HAVE_LCD_BITMAP | ||
14 | |||
15 | /* define this if you can flip your LCD */ | ||
16 | #define HAVE_LCD_FLIP | ||
17 | |||
18 | /* define this if you can invert the colours on your LCD */ | ||
19 | #define HAVE_LCD_INVERT | ||
20 | |||
21 | /* define this if you would like tagcache to build on this target */ | ||
22 | #define HAVE_TAGCACHE | ||
23 | |||
24 | /* LCD dimensions */ | ||
25 | #define LCD_WIDTH 112 | ||
26 | #define LCD_HEIGHT 64 | ||
27 | /* sqrt(112^2 + 64^2) / 1.5 = 83.8 */ | ||
28 | #define LCD_DPI 84 | ||
29 | #define LCD_DEPTH 1 | ||
30 | |||
31 | #define LCD_PIXEL_ASPECT_WIDTH 4 | ||
32 | #define LCD_PIXEL_ASPECT_HEIGHT 5 | ||
33 | |||
34 | #define LCD_PIXELFORMAT VERTICAL_PACKING | ||
35 | |||
36 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
37 | #define LCD_DARKCOLOR 0x000000 | ||
38 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
39 | #define LCD_BL_DARKCOLOR 0x000000 | ||
40 | #define LCD_BL_BRIGHTCOLOR 0x82b4fa | ||
41 | |||
42 | /* define this if you have an Ondio style 6-key keyboard */ | ||
43 | #define CONFIG_KEYPAD ONDIO_PAD | ||
44 | |||
45 | /* Define this to enable morse code input */ | ||
46 | #define HAVE_MORSE_INPUT | ||
47 | |||
48 | #define AB_REPEAT_ENABLE | ||
49 | #define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE | ||
50 | |||
51 | /* Define this if you have a software controlled poweroff */ | ||
52 | #define HAVE_SW_POWEROFF | ||
53 | |||
54 | /* The number of bytes reserved for loadable plugins */ | ||
55 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
56 | |||
57 | #ifndef BOOTLOADER | ||
58 | /* Define this if you have an FM Radio */ | ||
59 | #define CONFIG_TUNER (S1A0903X01 | TEA5767) /* to be decided at runtime */ | ||
60 | #define CONFIG_TUNER_XTAL 13000000 | ||
61 | #endif | ||
62 | |||
63 | /* Define this if you have a MAS3587F */ | ||
64 | #define CONFIG_CODEC MAS3587F | ||
65 | |||
66 | /* define this if you have a flash memory storage */ | ||
67 | #define HAVE_FLASH_STORAGE | ||
68 | |||
69 | #define BATTERY_CAPACITY_DEFAULT 1000 /* default battery capacity */ | ||
70 | #define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ | ||
71 | #define BATTERY_CAPACITY_MAX 1500 /* max. capacity selectable */ | ||
72 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
73 | #define BATTERY_TYPES_COUNT 2 /* Alkalines or NiMH */ | ||
74 | |||
75 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
76 | |||
77 | /* define this if the unit should not shut down on low battery. */ | ||
78 | #define NO_LOW_BATTERY_SHUTDOWN | ||
79 | |||
80 | /* define this if the unit can be powered or charged via USB */ | ||
81 | #define HAVE_USB_POWER | ||
82 | |||
83 | /* define current usage levels */ | ||
84 | #define CURRENT_NORMAL 95 /* average, nearly proportional to 1/U */ | ||
85 | #define CURRENT_USB 1 /* host powered in USB mode; avoid zero-div */ | ||
86 | #define CURRENT_BACKLIGHT 0 /* no backlight */ | ||
87 | |||
88 | /* Define this if you have a SH7034 */ | ||
89 | #define CONFIG_CPU SH7034 | ||
90 | |||
91 | /* Define this to the CPU frequency */ | ||
92 | #define CPU_FREQ 12000000 | ||
93 | |||
94 | /* Define this for different I2C pinout */ | ||
95 | #define CONFIG_I2C I2C_ONDIO | ||
96 | |||
97 | /* Offset ( in the firmware file's header ) to the file length */ | ||
98 | #define FIRMWARE_OFFSET_FILE_LENGTH 20 | ||
99 | |||
100 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
101 | #define FIRMWARE_OFFSET_FILE_CRC 6 | ||
102 | |||
103 | /* Offset ( in the firmware file's header ) to the real data */ | ||
104 | #define FIRMWARE_OFFSET_FILE_DATA 24 | ||
105 | |||
106 | /* Define this if the tuner is switched on by software */ | ||
107 | #define HAVE_TUNER_PWR_CTRL | ||
108 | |||
109 | /* The start address index for ROM builds */ | ||
110 | /* #define ROM_START 0x16010 for behind original Archos */ | ||
111 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
112 | |||
113 | /* Define this if the display is mounted upside down */ | ||
114 | #define HAVE_DISPLAY_FLIPPED | ||
115 | |||
116 | /* Define this for different ADC channel assignment */ | ||
117 | #define HAVE_ONDIO_ADC | ||
118 | |||
119 | /* Define this for MMC support instead of ATA harddisk */ | ||
120 | #define CONFIG_STORAGE STORAGE_MMC | ||
121 | |||
122 | /* Define this to support mounting FAT16 partitions */ | ||
123 | #define HAVE_FAT16SUPPORT | ||
124 | |||
125 | /* Define this if the MAS SIBI line can be controlled via PB8 */ | ||
126 | #define HAVE_MAS_SIBI_CONTROL | ||
127 | |||
128 | /* define this if more than one device/partition can be used */ | ||
129 | #define HAVE_MULTIDRIVE | ||
130 | #define NUM_DRIVES 2 | ||
131 | |||
132 | /* define this if media can be exchanged on the fly */ | ||
133 | #define HAVE_HOTSWAP | ||
134 | |||
135 | #define CONFIG_LCD LCD_SSD1815 | ||
136 | |||
137 | #define BOOTFILE_EXT "ajz" | ||
138 | #define BOOTFILE "ajbrec." BOOTFILE_EXT | ||
139 | #define BOOTDIR "/" | ||
140 | |||
141 | #define HAVE_LCD_CONTRAST | ||
142 | |||
143 | #define MIN_CONTRAST_SETTING 5 | ||
144 | #define MAX_CONTRAST_SETTING 63 | ||
145 | |||
146 | /* Define this if a programmable hotkey is mapped */ | ||
147 | //#define HAVE_HOTKEY | ||
diff --git a/firmware/export/config/archosondiosp.h b/firmware/export/config/archosondiosp.h deleted file mode 100644 index 3e9de1eda6..0000000000 --- a/firmware/export/config/archosondiosp.h +++ /dev/null | |||
@@ -1,131 +0,0 @@ | |||
1 | /* define this if you have a bitmap LCD display */ | ||
2 | #define HAVE_LCD_BITMAP | ||
3 | |||
4 | #define MODEL_NAME "Ondio SP" | ||
5 | |||
6 | #define ONDIO_SERIES | ||
7 | |||
8 | /* define this if you can flip your LCD */ | ||
9 | #define HAVE_LCD_FLIP | ||
10 | |||
11 | /* define this if you can invert the colours on your LCD */ | ||
12 | #define HAVE_LCD_INVERT | ||
13 | |||
14 | /* define this if you would like tagcache to build on this target */ | ||
15 | #define HAVE_TAGCACHE | ||
16 | |||
17 | /* LCD dimensions */ | ||
18 | #define LCD_WIDTH 112 | ||
19 | #define LCD_HEIGHT 64 | ||
20 | /* sqrt(112^2 + 64^2) / 1.5 = 83.8 */ | ||
21 | #define LCD_DPI 84 | ||
22 | #define LCD_DEPTH 1 | ||
23 | |||
24 | #define LCD_PIXEL_ASPECT_WIDTH 4 | ||
25 | #define LCD_PIXEL_ASPECT_HEIGHT 5 | ||
26 | |||
27 | #define LCD_PIXELFORMAT VERTICAL_PACKING | ||
28 | |||
29 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
30 | #define LCD_DARKCOLOR 0x000000 | ||
31 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
32 | #define LCD_BL_DARKCOLOR 0x000000 | ||
33 | #define LCD_BL_BRIGHTCOLOR 0x82b4fa | ||
34 | |||
35 | /* define this if you have an Ondio style 6-key keyboard */ | ||
36 | #define CONFIG_KEYPAD ONDIO_PAD | ||
37 | |||
38 | /* Define this to enable morse code input */ | ||
39 | #define HAVE_MORSE_INPUT | ||
40 | |||
41 | #define AB_REPEAT_ENABLE | ||
42 | #define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE | ||
43 | |||
44 | /* Define this if you have a software controlled poweroff */ | ||
45 | #define HAVE_SW_POWEROFF | ||
46 | |||
47 | /* The number of bytes reserved for loadable plugins */ | ||
48 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
49 | |||
50 | /* Define this if you have a MAS3539F */ | ||
51 | #define CONFIG_CODEC MAS3539F | ||
52 | |||
53 | /* define this if you have a flash memory storage */ | ||
54 | #define HAVE_FLASH_STORAGE | ||
55 | |||
56 | #define BATTERY_CAPACITY_DEFAULT 1000 /* default battery capacity */ | ||
57 | #define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ | ||
58 | #define BATTERY_CAPACITY_MAX 1500 /* max. capacity selectable */ | ||
59 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
60 | #define BATTERY_TYPES_COUNT 2 /* Alkalines or NiMH */ | ||
61 | |||
62 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
63 | |||
64 | /* define this if the unit should not shut down on low battery. */ | ||
65 | #define NO_LOW_BATTERY_SHUTDOWN | ||
66 | |||
67 | /* define this if the unit can be powered or charged via USB */ | ||
68 | #define HAVE_USB_POWER | ||
69 | |||
70 | /* define current usage levels */ | ||
71 | #define CURRENT_NORMAL 95 /* average, nearly proportional to 1/U */ | ||
72 | #define CURRENT_USB 1 /* host powered in USB mode; avoid zero-div */ | ||
73 | #define CURRENT_BACKLIGHT 0 /* no backlight */ | ||
74 | |||
75 | /* Define this if you have a SH7034 */ | ||
76 | #define CONFIG_CPU SH7034 | ||
77 | |||
78 | /* Define this to the CPU frequency */ | ||
79 | #define CPU_FREQ 12000000 | ||
80 | |||
81 | /* Offset ( in the firmware file's header ) to the file length */ | ||
82 | #define FIRMWARE_OFFSET_FILE_LENGTH 20 | ||
83 | |||
84 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
85 | #define FIRMWARE_OFFSET_FILE_CRC 6 | ||
86 | |||
87 | /* Offset ( in the firmware file's header ) to the real data */ | ||
88 | #define FIRMWARE_OFFSET_FILE_DATA 24 | ||
89 | |||
90 | /* The start address index for ROM builds */ | ||
91 | /* #define ROM_START 0x12010 for behind original Archos */ | ||
92 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
93 | |||
94 | /* Define this if the display is mounted upside down */ | ||
95 | #define HAVE_DISPLAY_FLIPPED | ||
96 | |||
97 | /* Define this for different I2C pinout */ | ||
98 | #define CONFIG_I2C I2C_ONDIO | ||
99 | |||
100 | /* Define this for different ADC channel assignment */ | ||
101 | #define HAVE_ONDIO_ADC | ||
102 | |||
103 | /* Define this for MMC support instead of ATA harddisk */ | ||
104 | #define CONFIG_STORAGE STORAGE_MMC | ||
105 | |||
106 | /* Define this to support mounting FAT16 partitions */ | ||
107 | #define HAVE_FAT16SUPPORT | ||
108 | |||
109 | /* Define this if the MAS SIBI line can be controlled via PB8 */ | ||
110 | #define HAVE_MAS_SIBI_CONTROL | ||
111 | |||
112 | /* define this if more than one device/partition can be used */ | ||
113 | #define HAVE_MULTIDRIVE | ||
114 | #define NUM_DRIVES 2 | ||
115 | |||
116 | /* define this if media can be exchanged on the fly */ | ||
117 | #define HAVE_HOTSWAP | ||
118 | |||
119 | #define CONFIG_LCD LCD_SSD1815 | ||
120 | |||
121 | #define BOOTFILE_EXT "ajz" | ||
122 | #define BOOTFILE "ajbrec." BOOTFILE_EXT | ||
123 | #define BOOTDIR "/" | ||
124 | |||
125 | #define HAVE_LCD_CONTRAST | ||
126 | |||
127 | #define MIN_CONTRAST_SETTING 5 | ||
128 | #define MAX_CONTRAST_SETTING 63 | ||
129 | |||
130 | /* Define this if a programmable hotkey is mapped */ | ||
131 | //#define HAVE_HOTKEY | ||
diff --git a/firmware/export/config/archosplayer.h b/firmware/export/config/archosplayer.h deleted file mode 100644 index 2e0219cff5..0000000000 --- a/firmware/export/config/archosplayer.h +++ /dev/null | |||
@@ -1,111 +0,0 @@ | |||
1 | /* define this if you use an ATA controller */ | ||
2 | #define CONFIG_STORAGE STORAGE_ATA | ||
3 | |||
4 | #define MODEL_NAME "Archos Player/Studio" | ||
5 | |||
6 | /* define this if you have a charcell LCD display */ | ||
7 | #define HAVE_LCD_CHARCELLS | ||
8 | |||
9 | /* define this if you would like tagcache to build on this target */ | ||
10 | #define HAVE_TAGCACHE | ||
11 | |||
12 | #define LCD_WIDTH 11 | ||
13 | #define LCD_HEIGHT 2 | ||
14 | /* sqrt(11^2 + 2^2) / 1.5 = 7.5 */ | ||
15 | #define LCD_DPI 7 | ||
16 | #define LCD_DEPTH 1 | ||
17 | #define SIM_LCD_WIDTH 132 /* pixels */ | ||
18 | #define SIM_LCD_HEIGHT 64 /* pixels */ | ||
19 | |||
20 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
21 | #define LCD_DARKCOLOR 0x000000 | ||
22 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
23 | #define LCD_BL_DARKCOLOR 0x000000 | ||
24 | #define LCD_BL_BRIGHTCOLOR 0x7ee57e | ||
25 | |||
26 | /* define this if you have the Player's keyboard */ | ||
27 | #define CONFIG_KEYPAD PLAYER_PAD | ||
28 | |||
29 | #define AB_REPEAT_ENABLE | ||
30 | #define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE | ||
31 | |||
32 | /* The number of bytes reserved for loadable plugins */ | ||
33 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
34 | |||
35 | /* Define this if you have a MAS3507D */ | ||
36 | #define CONFIG_CODEC MAS3507D | ||
37 | |||
38 | /* Define this if you have a DAC3550A */ | ||
39 | #define HAVE_DAC3550A | ||
40 | |||
41 | /* define this if you have a disk storage, i.e. something | ||
42 | that needs spinups and can cause skips when shaked */ | ||
43 | #define HAVE_DISK_STORAGE | ||
44 | |||
45 | /* Define this for LCD backlight available */ | ||
46 | #define HAVE_BACKLIGHT | ||
47 | |||
48 | #define BATTERY_CAPACITY_DEFAULT 1500 /* default battery capacity */ | ||
49 | #define BATTERY_CAPACITY_MIN 1500 /* min. capacity selectable */ | ||
50 | #define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ | ||
51 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
52 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
53 | |||
54 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
55 | |||
56 | #define CURRENT_NORMAL 145 /* usual current in mA */ | ||
57 | #define CURRENT_USB 500 /* usual current in mA in USB mode */ | ||
58 | |||
59 | /* define this if the unit should not shut down on low battery. */ | ||
60 | #define NO_LOW_BATTERY_SHUTDOWN | ||
61 | |||
62 | /* Hardware controlled charging */ | ||
63 | #define CONFIG_CHARGING CHARGING_SIMPLE | ||
64 | |||
65 | /* Define this if you have a SH7034 */ | ||
66 | #define CONFIG_CPU SH7034 | ||
67 | |||
68 | /* Define this if you control ata power player style | ||
69 | (with PB4, new player only) */ | ||
70 | #define ATA_POWER_PLAYERSTYLE | ||
71 | |||
72 | /* Define this to the CPU frequency */ | ||
73 | #define CPU_FREQ 12000000 /* cycle time ~83.3ns */ | ||
74 | |||
75 | /* Define this if you must discharge the data line by driving it low | ||
76 | and then set it to input to see if it stays low or goes high */ | ||
77 | #define HAVE_I2C_LOW_FIRST | ||
78 | |||
79 | #define CONFIG_I2C I2C_PLAYREC | ||
80 | |||
81 | /* Offset ( in the firmware file's header ) to the file length */ | ||
82 | #define FIRMWARE_OFFSET_FILE_LENGTH 0 | ||
83 | |||
84 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
85 | #define FIRMWARE_OFFSET_FILE_CRC 4 | ||
86 | |||
87 | /* Offset ( in the firmware file's header ) to the real data */ | ||
88 | #define FIRMWARE_OFFSET_FILE_DATA 6 | ||
89 | |||
90 | /* The start address index for ROM builds */ | ||
91 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
92 | |||
93 | /* Software controlled LED */ | ||
94 | #define CONFIG_LED LED_REAL | ||
95 | |||
96 | #define CONFIG_LCD LCD_SSD1801 | ||
97 | |||
98 | #define BOOTFILE_EXT "mod" | ||
99 | #define BOOTFILE "archos." BOOTFILE_EXT | ||
100 | #define BOOTDIR "/" | ||
101 | |||
102 | #define HAVE_LCD_CONTRAST | ||
103 | |||
104 | #define MIN_CONTRAST_SETTING 5 | ||
105 | #define MAX_CONTRAST_SETTING 31 | ||
106 | #define DEFAULT_CONTRAST_SETTING 30 | ||
107 | |||
108 | #define HAVE_SERIAL | ||
109 | |||
110 | /* Define this if a programmable hotkey is mapped */ | ||
111 | #define HAVE_HOTKEY | ||
diff --git a/firmware/export/config/archosrecorder.h b/firmware/export/config/archosrecorder.h deleted file mode 100644 index 016ea8b944..0000000000 --- a/firmware/export/config/archosrecorder.h +++ /dev/null | |||
@@ -1,141 +0,0 @@ | |||
1 | /* define this if you use an ATA controller */ | ||
2 | #define CONFIG_STORAGE STORAGE_ATA | ||
3 | |||
4 | #define MODEL_NAME "Archos Recorder" | ||
5 | |||
6 | /* define this if you have recording possibility */ | ||
7 | #define HAVE_RECORDING | ||
8 | |||
9 | /* Define bitmask of input sources - recordable bitmask can be defined | ||
10 | explicitly if different */ | ||
11 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) | ||
12 | |||
13 | /* define this if you have a bitmap LCD display */ | ||
14 | #define HAVE_LCD_BITMAP | ||
15 | |||
16 | /* define this if you can flip your LCD */ | ||
17 | //#define HAVE_LCD_FLIP | ||
18 | |||
19 | /* define this if you can invert the colours on your LCD */ | ||
20 | #define HAVE_LCD_INVERT | ||
21 | |||
22 | /* define this if you have access to the quickscreen */ | ||
23 | #define HAVE_QUICKSCREEN | ||
24 | |||
25 | /* define this if you have the button bar */ | ||
26 | #define HAVE_BUTTONBAR | ||
27 | |||
28 | /* define this if you would like tagcache to build on this target */ | ||
29 | #define HAVE_TAGCACHE | ||
30 | |||
31 | /* LCD dimensions */ | ||
32 | #define LCD_WIDTH 112 | ||
33 | #define LCD_HEIGHT 64 | ||
34 | /* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ | ||
35 | #define LCD_DPI 85 | ||
36 | #define LCD_DEPTH 1 | ||
37 | |||
38 | #define LCD_PIXEL_ASPECT_WIDTH 4 | ||
39 | #define LCD_PIXEL_ASPECT_HEIGHT 5 | ||
40 | |||
41 | #define LCD_PIXELFORMAT VERTICAL_PACKING | ||
42 | |||
43 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
44 | #define LCD_DARKCOLOR 0x000000 | ||
45 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
46 | #define LCD_BL_DARKCOLOR 0x000000 | ||
47 | #define LCD_BL_BRIGHTCOLOR 0x7ee57e | ||
48 | |||
49 | /* define this if you have the Recorder's 10-key keyboard */ | ||
50 | #define CONFIG_KEYPAD RECORDER_PAD | ||
51 | |||
52 | /* Define this to enable morse code input */ | ||
53 | //#define HAVE_MORSE_INPUT | ||
54 | |||
55 | /* define this if you have a real-time clock */ | ||
56 | #define CONFIG_RTC RTC_M41ST84W | ||
57 | |||
58 | /* define this if you have RTC RAM available for settings */ | ||
59 | #define HAVE_RTC_RAM | ||
60 | |||
61 | /* The number of bytes reserved for loadable plugins */ | ||
62 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
63 | |||
64 | #define AB_REPEAT_ENABLE | ||
65 | |||
66 | /* Define this if you have a MAS3587F */ | ||
67 | #define CONFIG_CODEC MAS3587F | ||
68 | |||
69 | /* define this if you have a disk storage, i.e. something | ||
70 | that needs spinups and can cause skips when shaked */ | ||
71 | #define HAVE_DISK_STORAGE | ||
72 | |||
73 | /* Define this for LCD backlight available */ | ||
74 | #define HAVE_BACKLIGHT | ||
75 | |||
76 | #define CONFIG_I2C I2C_PLAYREC | ||
77 | |||
78 | #define BATTERY_CAPACITY_DEFAULT 1500 /* default battery capacity */ | ||
79 | #define BATTERY_CAPACITY_MIN 1500 /* min. capacity selectable */ | ||
80 | #define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ | ||
81 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
82 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
83 | |||
84 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
85 | |||
86 | #if MEMORYSIZE < 8 | ||
87 | #define CURRENT_NORMAL 145 /* usual current in mA */ | ||
88 | #else | ||
89 | #define CURRENT_NORMAL 145 *100 / 122 /* assuming 192 kbps, the running time is 22% longer with 8MB */ | ||
90 | #endif | ||
91 | #define CURRENT_RECORD 35 /* additional recording current */ | ||
92 | #define CURRENT_USB 500 /* usual current in mA in USB mode */ | ||
93 | |||
94 | /* define this if the unit should not shut down on low battery. */ | ||
95 | #define NO_LOW_BATTERY_SHUTDOWN | ||
96 | |||
97 | /* Software controlled charging */ | ||
98 | #define CONFIG_CHARGING CHARGING_TARGET | ||
99 | |||
100 | /* Define this if you have a SH7034 */ | ||
101 | #define CONFIG_CPU SH7034 | ||
102 | |||
103 | /* Define this if you have ATA power-off control */ | ||
104 | #define HAVE_ATA_POWER_OFF | ||
105 | |||
106 | /* Define this to the CPU frequency */ | ||
107 | #define CPU_FREQ 11059200 | ||
108 | |||
109 | /* Offset ( in the firmware file's header ) to the file length */ | ||
110 | #define FIRMWARE_OFFSET_FILE_LENGTH 0 | ||
111 | |||
112 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
113 | #define FIRMWARE_OFFSET_FILE_CRC 4 | ||
114 | |||
115 | /* Offset ( in the firmware file's header ) to the real data */ | ||
116 | #define FIRMWARE_OFFSET_FILE_DATA 6 | ||
117 | |||
118 | /* The start address index for ROM builds */ | ||
119 | /* #define ROM_START 0x11010 for behind original Archos */ | ||
120 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
121 | |||
122 | /* Software controlled LED */ | ||
123 | #define CONFIG_LED LED_REAL | ||
124 | |||
125 | /* Define this for S/PDIF output available */ | ||
126 | #define HAVE_SPDIF_OUT | ||
127 | |||
128 | #define CONFIG_LCD LCD_SSD1815 | ||
129 | |||
130 | #define BOOTFILE_EXT "ajz" | ||
131 | #define BOOTFILE "ajbrec." BOOTFILE_EXT | ||
132 | #define BOOTDIR "/" | ||
133 | |||
134 | #define HAVE_LCD_CONTRAST | ||
135 | |||
136 | #define MIN_CONTRAST_SETTING 5 | ||
137 | #define MAX_CONTRAST_SETTING 63 | ||
138 | |||
139 | #define HAVE_SERIAL | ||
140 | /* Define this if a programmable hotkey is mapped */ | ||
141 | #define HAVE_HOTKEY | ||
diff --git a/firmware/export/config/archosrecorderv2.h b/firmware/export/config/archosrecorderv2.h deleted file mode 100644 index 4640eae247..0000000000 --- a/firmware/export/config/archosrecorderv2.h +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | /* define this if you use an ATA controller */ | ||
2 | #define CONFIG_STORAGE STORAGE_ATA | ||
3 | |||
4 | #define MODEL_NAME "Archos Recorder v2" | ||
5 | |||
6 | /* define this if you have recording possibility */ | ||
7 | #define HAVE_RECORDING | ||
8 | |||
9 | /* Define bitmask of input sources - recordable bitmask can be defined | ||
10 | explicitly if different */ | ||
11 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) | ||
12 | |||
13 | /* define this if you have a bitmap LCD display */ | ||
14 | #define HAVE_LCD_BITMAP | ||
15 | |||
16 | /* define this if you can flip your LCD */ | ||
17 | #define HAVE_LCD_FLIP | ||
18 | |||
19 | /* define this if you can invert the colours on your LCD */ | ||
20 | #define HAVE_LCD_INVERT | ||
21 | |||
22 | /* define this if you have access to the quickscreen */ | ||
23 | #define HAVE_QUICKSCREEN | ||
24 | |||
25 | /* define this if you have the button bar */ | ||
26 | #define HAVE_BUTTONBAR | ||
27 | |||
28 | /* define this if you would like tagcache to build on this target */ | ||
29 | #define HAVE_TAGCACHE | ||
30 | |||
31 | /* LCD dimensions */ | ||
32 | #define LCD_WIDTH 112 | ||
33 | #define LCD_HEIGHT 64 | ||
34 | /* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ | ||
35 | #define LCD_DPI 85 | ||
36 | #define LCD_DEPTH 1 | ||
37 | |||
38 | #define LCD_PIXEL_ASPECT_WIDTH 4 | ||
39 | #define LCD_PIXEL_ASPECT_HEIGHT 5 | ||
40 | |||
41 | #define LCD_PIXELFORMAT VERTICAL_PACKING | ||
42 | |||
43 | /* Display colours, for screenshots and sim (0xRRGGBB) */ | ||
44 | #define LCD_DARKCOLOR 0x000000 | ||
45 | #define LCD_BRIGHTCOLOR 0x5a915a | ||
46 | #define LCD_BL_DARKCOLOR 0x000000 | ||
47 | #define LCD_BL_BRIGHTCOLOR 0x7ee57e | ||
48 | |||
49 | /* define this if you have a Recorder style 10-key keyboard */ | ||
50 | #define CONFIG_KEYPAD RECORDER_PAD | ||
51 | |||
52 | /* Define this to enable morse code input */ | ||
53 | #define HAVE_MORSE_INPUT | ||
54 | |||
55 | /* define this if you have a real-time clock */ | ||
56 | #define CONFIG_RTC RTC_M41ST84W | ||
57 | |||
58 | /* FM recorders can wake up from RTC alarm */ | ||
59 | #define HAVE_RTC_ALARM | ||
60 | |||
61 | /* define this if you have RTC RAM available for settings */ | ||
62 | #define HAVE_RTC_RAM | ||
63 | |||
64 | /* Define this if you have a software controlled poweroff */ | ||
65 | #define HAVE_SW_POWEROFF | ||
66 | |||
67 | /* The number of bytes reserved for loadable plugins */ | ||
68 | #define PLUGIN_BUFFER_SIZE 0x8000 | ||
69 | |||
70 | #define AB_REPEAT_ENABLE | ||
71 | |||
72 | /* Define this if you have a MAS3587F */ | ||
73 | #define CONFIG_CODEC MAS3587F | ||
74 | |||
75 | /* define this if you have a disk storage, i.e. something | ||
76 | that needs spinups and can cause skips when shaked */ | ||
77 | #define HAVE_DISK_STORAGE | ||
78 | |||
79 | /* Define this for LCD backlight available */ | ||
80 | #define HAVE_BACKLIGHT | ||
81 | |||
82 | #define CONFIG_I2C I2C_PLAYREC | ||
83 | |||
84 | #define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */ | ||
85 | #define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */ | ||
86 | #define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ | ||
87 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
88 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
89 | |||
90 | #define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE | ||
91 | |||
92 | #define CURRENT_NORMAL 145 /* usual current in mA */ | ||
93 | #define CURRENT_RECORD 35 /* additional recording current */ | ||
94 | #define CURRENT_USB 500 /* usual current in mA in USB mode */ | ||
95 | |||
96 | /* Hardware controlled charging with monitoring */ | ||
97 | #define CONFIG_CHARGING CHARGING_MONITOR | ||
98 | |||
99 | /* define this if the unit can be powered or charged via USB */ | ||
100 | #define HAVE_USB_POWER | ||
101 | |||
102 | /* Define this if you have a SH7034 */ | ||
103 | #define CONFIG_CPU SH7034 | ||
104 | |||
105 | /* Define this if you have a FM Recorder key system */ | ||
106 | #define HAVE_FMADC | ||
107 | |||
108 | /* Define this if battery voltage can only be measured with ATA powered */ | ||
109 | #define NEED_ATA_POWER_BATT_MEASURE | ||
110 | |||
111 | /* Define this to the CPU frequency */ | ||
112 | #define CPU_FREQ 11059200 | ||
113 | |||
114 | /* Offset ( in the firmware file's header ) to the file length */ | ||
115 | #define FIRMWARE_OFFSET_FILE_LENGTH 20 | ||
116 | |||
117 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
118 | #define FIRMWARE_OFFSET_FILE_CRC 6 | ||
119 | |||
120 | /* Offset ( in the firmware file's header ) to the real data */ | ||
121 | #define FIRMWARE_OFFSET_FILE_DATA 24 | ||
122 | |||
123 | #ifndef BOOTLOADER | ||
124 | /* Define this if you have an FM Radio */ | ||
125 | #define CONFIG_TUNER S1A0903X01 | ||
126 | #endif | ||
127 | |||
128 | /* The start address index for ROM builds */ | ||
129 | /* #define ROM_START 0x12010 for behind original Archos */ | ||
130 | #define ROM_START 0x7010 /* for behind BootBox */ | ||
131 | |||
132 | /* Software controlled LED */ | ||
133 | #define CONFIG_LED LED_REAL | ||
134 | |||
135 | #define CONFIG_LCD LCD_SSD1815 | ||
136 | |||
137 | #define BOOTFILE_EXT "ajz" | ||
138 | #define BOOTFILE "ajbrec." BOOTFILE_EXT | ||
139 | #define BOOTDIR "/" | ||
140 | |||
141 | #define HAVE_LCD_CONTRAST | ||
142 | |||
143 | #define MIN_CONTRAST_SETTING 5 | ||
144 | #define MAX_CONTRAST_SETTING 63 | ||
145 | |||
146 | /* Define this if a programmable hotkey is mapped */ | ||
147 | #define HAVE_HOTKEY | ||
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h index 201ffba656..aade199dd2 100644 --- a/firmware/export/cpu.h +++ b/firmware/export/cpu.h | |||
@@ -20,9 +20,6 @@ | |||
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include "config.h" | 21 | #include "config.h" |
22 | 22 | ||
23 | #if CONFIG_CPU == SH7034 | ||
24 | #include "sh7034.h" | ||
25 | #endif | ||
26 | #if CONFIG_CPU == MCF5249 | 23 | #if CONFIG_CPU == MCF5249 |
27 | #include "mcf5249.h" | 24 | #include "mcf5249.h" |
28 | #endif | 25 | #endif |
diff --git a/firmware/export/hwcompat.h b/firmware/export/hwcompat.h index c37add49f9..ea167a4adf 100644 --- a/firmware/export/hwcompat.h +++ b/firmware/export/hwcompat.h | |||
@@ -24,37 +24,6 @@ | |||
24 | #include <stdbool.h> | 24 | #include <stdbool.h> |
25 | #include "config.h" | 25 | #include "config.h" |
26 | 26 | ||
27 | #if (CONFIG_CPU == SH7034) && (CONFIG_PLATFORM & PLATFORM_NATIVE) | ||
28 | |||
29 | #define ROM_VERSION (*(short *)0x020000fe) | ||
30 | |||
31 | /* Bit mask values for HW compatibility */ | ||
32 | #define ATA_ADDRESS_200 0x0100 | ||
33 | #define USB_ACTIVE_HIGH 0x0100 | ||
34 | #define PR_ACTIVE_HIGH 0x0100 | ||
35 | #define LCD_CONTRAST_BIAS 0x0200 | ||
36 | #define MMC_CLOCK_POLARITY 0x0400 | ||
37 | #define TUNER_MODEL 0x0800 | ||
38 | |||
39 | #ifdef ARCHOS_PLAYER | ||
40 | #define HW_MASK 0 | ||
41 | #else /* Recorders, Ondios */ | ||
42 | #define HW_MASK (*(short *)0x020000fc) | ||
43 | #endif | ||
44 | |||
45 | #ifdef CONFIG_TUNER_MULTI | ||
46 | static inline int tuner_detect_type(void) | ||
47 | { | ||
48 | return (HW_MASK & TUNER_MODEL) ? TEA5767 : S1A0903X01; | ||
49 | } | ||
50 | #endif | ||
51 | |||
52 | #endif /* (CONFIG_CPU == SH7034) && (CONFIG_PLATFORM & PLATFORM_NATIVE) */ | ||
53 | |||
54 | #ifdef ARCHOS_PLAYER | ||
55 | bool is_new_player(void); | ||
56 | #endif | ||
57 | |||
58 | #ifdef IPOD_ARCH | 27 | #ifdef IPOD_ARCH |
59 | #ifdef IPOD_VIDEO | 28 | #ifdef IPOD_VIDEO |
60 | #ifdef BOOTLOADER | 29 | #ifdef BOOTLOADER |
diff --git a/firmware/export/mas35xx.h b/firmware/export/mas35xx.h deleted file mode 100644 index 02691f3de2..0000000000 --- a/firmware/export/mas35xx.h +++ /dev/null | |||
@@ -1,292 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Implementation of MAS35xx audiohw api driver. | ||
11 | * | ||
12 | * Copyright (C) 2007 by Christian Gmeiner | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | |||
24 | #ifndef _MAS35XX_H | ||
25 | #define _MAS35XX_H | ||
26 | |||
27 | #include "config.h" | ||
28 | #include "mascodec.h" | ||
29 | |||
30 | #define MAS_BANK_D0 0 | ||
31 | #define MAS_BANK_D1 1 | ||
32 | |||
33 | /* registers common to all MAS35xx */ | ||
34 | #define MAS_REG_DCCF 0x8e | ||
35 | #define MAS_REG_MUTE 0xaa | ||
36 | #define MAS_REG_PIODATA 0xc8 | ||
37 | #define MAS_REG_StartUpConfig 0xe6 | ||
38 | #define MAS_REG_KPRESCALE 0xe7 | ||
39 | |||
40 | #if CONFIG_CODEC == MAS3507D | ||
41 | |||
42 | #define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP) | ||
43 | |||
44 | AUDIOHW_SETTING(VOLUME, "dB", 0, 1, -78, 18, -18) | ||
45 | AUDIOHW_SETTING(BASS, "dB", 0, 1, -15, 15, 7) | ||
46 | AUDIOHW_SETTING(TREBLE, "dB", 0, 1, -15, 15, 7) | ||
47 | |||
48 | /* I2C defines */ | ||
49 | #define MAS_ADR 0x3a | ||
50 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) | ||
51 | #define MAS_DEV_READ (MAS_ADR | 0x01) | ||
52 | |||
53 | /* MAS3507D registers */ | ||
54 | #define MAS_DATA_WRITE 0x68 | ||
55 | #define MAS_DATA_READ 0x69 | ||
56 | #define MAS_CONTROL 0x6a | ||
57 | |||
58 | #define MAS_REG_KBASS 0x6b | ||
59 | #define MAS_REG_KTREBLE 0x6f | ||
60 | |||
61 | /* MAS3507D commands */ | ||
62 | #define MAS_CMD_READ_ANCILLARY 0x30 | ||
63 | #define MAS_CMD_WRITE_REG 0x90 | ||
64 | #define MAS_CMD_WRITE_D0_MEM 0xa0 | ||
65 | #define MAS_CMD_WRITE_D1_MEM 0xb0 | ||
66 | #define MAS_CMD_READ_REG 0xd0 | ||
67 | #define MAS_CMD_READ_D0_MEM 0xe0 | ||
68 | #define MAS_CMD_READ_D1_MEM 0xf0 | ||
69 | |||
70 | /* MAS3507D D0 memmory cells */ | ||
71 | #define MAS_D0_MPEG_FRAME_COUNT 0x300 | ||
72 | #define MAS_D0_MPEG_STATUS_1 0x301 | ||
73 | #define MAS_D0_MPEG_STATUS_2 0x302 | ||
74 | #define MAS_D0_CRC_ERROR_COUNT 0x303 | ||
75 | #define MAS_D0_OUT_LL 0x7f8 | ||
76 | #define MAS_D0_OUT_LR 0x7f9 | ||
77 | #define MAS_D0_OUT_RL 0x7fa | ||
78 | #define MAS_D0_OUT_RR 0x7fb | ||
79 | |||
80 | static const unsigned int bass_table[] = | ||
81 | { | ||
82 | 0x9e400, /* -15dB */ | ||
83 | 0xa2800, /* -14dB */ | ||
84 | 0xa7400, /* -13dB */ | ||
85 | 0xac400, /* -12dB */ | ||
86 | 0xb1800, /* -11dB */ | ||
87 | 0xb7400, /* -10dB */ | ||
88 | 0xbd400, /* -9dB */ | ||
89 | 0xc3c00, /* -8dB */ | ||
90 | 0xca400, /* -7dB */ | ||
91 | 0xd1800, /* -6dB */ | ||
92 | 0xd8c00, /* -5dB */ | ||
93 | 0xe0400, /* -4dB */ | ||
94 | 0xe8000, /* -3dB */ | ||
95 | 0xefc00, /* -2dB */ | ||
96 | 0xf7c00, /* -1dB */ | ||
97 | 0, | ||
98 | 0x800, /* 1dB */ | ||
99 | 0x10000, /* 2dB */ | ||
100 | 0x17c00, /* 3dB */ | ||
101 | 0x1f800, /* 4dB */ | ||
102 | 0x27000, /* 5dB */ | ||
103 | 0x2e400, /* 6dB */ | ||
104 | 0x35800, /* 7dB */ | ||
105 | 0x3c000, /* 8dB */ | ||
106 | 0x42800, /* 9dB */ | ||
107 | 0x48800, /* 10dB */ | ||
108 | 0x4e400, /* 11dB */ | ||
109 | 0x53800, /* 12dB */ | ||
110 | 0x58800, /* 13dB */ | ||
111 | 0x5d400, /* 14dB */ | ||
112 | 0x61800 /* 15dB */ | ||
113 | }; | ||
114 | |||
115 | static const unsigned int treble_table[] = | ||
116 | { | ||
117 | 0xb2c00, /* -15dB */ | ||
118 | 0xbb400, /* -14dB */ | ||
119 | 0xc1800, /* -13dB */ | ||
120 | 0xc6c00, /* -12dB */ | ||
121 | 0xcbc00, /* -11dB */ | ||
122 | 0xd0400, /* -10dB */ | ||
123 | 0xd5000, /* -9dB */ | ||
124 | 0xd9800, /* -8dB */ | ||
125 | 0xde000, /* -7dB */ | ||
126 | 0xe2800, /* -6dB */ | ||
127 | 0xe7e00, /* -5dB */ | ||
128 | 0xec000, /* -4dB */ | ||
129 | 0xf0c00, /* -3dB */ | ||
130 | 0xf5c00, /* -2dB */ | ||
131 | 0xfac00, /* -1dB */ | ||
132 | 0, | ||
133 | 0x5400, /* 1dB */ | ||
134 | 0xac00, /* 2dB */ | ||
135 | 0x10400, /* 3dB */ | ||
136 | 0x16000, /* 4dB */ | ||
137 | 0x1c000, /* 5dB */ | ||
138 | 0x22400, /* 6dB */ | ||
139 | 0x28400, /* 7dB */ | ||
140 | 0x2ec00, /* 8dB */ | ||
141 | 0x35400, /* 9dB */ | ||
142 | 0x3c000, /* 10dB */ | ||
143 | 0x42c00, /* 11dB */ | ||
144 | 0x49c00, /* 12dB */ | ||
145 | 0x51800, /* 13dB */ | ||
146 | 0x58400, /* 14dB */ | ||
147 | 0x5f800 /* 15dB */ | ||
148 | }; | ||
149 | |||
150 | static const unsigned int prescale_table[] = | ||
151 | { | ||
152 | 0x80000, /* 0db */ | ||
153 | 0x8e000, /* 1dB */ | ||
154 | 0x9a400, /* 2dB */ | ||
155 | 0xa5800, /* 3dB */ | ||
156 | 0xaf400, /* 4dB */ | ||
157 | 0xb8000, /* 5dB */ | ||
158 | 0xbfc00, /* 6dB */ | ||
159 | 0xc6c00, /* 7dB */ | ||
160 | 0xcd000, /* 8dB */ | ||
161 | 0xd25c0, /* 9dB */ | ||
162 | 0xd7800, /* 10dB */ | ||
163 | 0xdc000, /* 11dB */ | ||
164 | 0xdfc00, /* 12dB */ | ||
165 | 0xe3400, /* 13dB */ | ||
166 | 0xe6800, /* 14dB */ | ||
167 | 0xe9400 /* 15dB */ | ||
168 | }; | ||
169 | |||
170 | #else /* CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F */ | ||
171 | |||
172 | AUDIOHW_SETTING(VOLUME, "dB", 0, 1,-100, 12, -25) | ||
173 | AUDIOHW_SETTING(BASS, "dB", 0, 1, -12, 12, 6) | ||
174 | AUDIOHW_SETTING(TREBLE, "dB", 0, 1, -12, 12, 6) | ||
175 | AUDIOHW_SETTING(LOUDNESS, "dB", 0, 1, 0, 17, 0) | ||
176 | AUDIOHW_SETTING(AVC, "", 0, 1, -1, 4, 0) | ||
177 | AUDIOHW_SETTING(MDB_STRENGTH, "dB", 0, 1, 0, 127, 48) | ||
178 | AUDIOHW_SETTING(MDB_HARMONICS, "%", 0, 1, 0, 100, 50) | ||
179 | AUDIOHW_SETTING(MDB_CENTER, "Hz", 0, 10, 20, 300, 60) | ||
180 | AUDIOHW_SETTING(MDB_SHAPE, "Hz", 0, 10, 50, 300, 90) | ||
181 | AUDIOHW_SETTING(MDB_ENABLE, "", 0, 1, 0, 1, 0) | ||
182 | AUDIOHW_SETTING(SUPERBASS, "", 0, 1, 0, 1, 0) | ||
183 | |||
184 | #if CONFIG_CODEC == MAS3587F && defined(HAVE_RECORDING) | ||
185 | /* MAS3587F and MAS3539F handle clipping prevention internally so we do not | ||
186 | * need the prescaler -> CLIPPING_CAP */ | ||
187 | #define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | BALANCE_CAP | CLIPPING_CAP | \ | ||
188 | MONO_VOL_CAP | LIN_GAIN_CAP | MIC_GAIN_CAP) | ||
189 | AUDIOHW_SETTING(LEFT_GAIN, "dB", 1, 1, 0, 15, 8, (val - 2) * 15) | ||
190 | AUDIOHW_SETTING(RIGHT_GAIN, "dB", 1, 1, 0, 15, 8, (val - 2) * 15) | ||
191 | AUDIOHW_SETTING(MIC_GAIN, "dB", 1, 1, 0, 15, 2, val * 15 + 210) | ||
192 | #else | ||
193 | /* MAS3587F and MAS3539F handle clipping prevention internally so we do not | ||
194 | * need the prescaler -> CLIPPING_CAP */ | ||
195 | #define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | BALANCE_CAP | CLIPPING_CAP | \ | ||
196 | MONO_VOL_CAP) | ||
197 | #endif /* MAS3587F && HAVE_RECORDING */ | ||
198 | |||
199 | /* I2C defines */ | ||
200 | #define MAS_ADR 0x3c | ||
201 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) | ||
202 | #define MAS_DEV_READ (MAS_ADR | 0x01) | ||
203 | |||
204 | /* MAS3587F/MAS3539F registers */ | ||
205 | #define MAS_DATA_WRITE 0x68 | ||
206 | #define MAS_DATA_READ 0x69 | ||
207 | #define MAS_CODEC_WRITE 0x6c | ||
208 | #define MAS_CODEC_READ 0x6d | ||
209 | #define MAS_CONTROL 0x6a | ||
210 | #define MAS_DCCF 0x76 | ||
211 | #define MAS_DCFR 0x77 | ||
212 | |||
213 | #define MAS_REG_KMDB_SWITCH 0x21 | ||
214 | #define MAS_REG_KMDB_STR 0x22 | ||
215 | #define MAS_REG_KMDB_HAR 0x23 | ||
216 | #define MAS_REG_KMDB_FC 0x24 | ||
217 | #define MAS_REG_KLOUDNESS 0x1e | ||
218 | #define MAS_REG_QPEAK_L 0x0a | ||
219 | #define MAS_REG_QPEAK_R 0x0b | ||
220 | #define MAS_REG_DQPEAK_L 0x0c | ||
221 | #define MAS_REG_DQPEAK_R 0x0d | ||
222 | #define MAS_REG_VOLUME_CONTROL 0x10 | ||
223 | #define MAS_REG_BALANCE 0x11 | ||
224 | #define MAS_REG_KAVC 0x12 | ||
225 | #define MAS_REG_KBASS 0x14 | ||
226 | #define MAS_REG_KTREBLE 0x15 | ||
227 | |||
228 | /* MAS3587F/MAS3539F commands */ | ||
229 | #define MAS_CMD_READ_ANCILLARY 0x50 | ||
230 | #define MAS_CMD_FAST_PRG_DL 0x60 | ||
231 | #define MAS_CMD_READ_IC_VER 0x70 | ||
232 | #define MAS_CMD_READ_REG 0xa0 | ||
233 | #define MAS_CMD_WRITE_REG 0xb0 | ||
234 | #define MAS_CMD_READ_D0_MEM 0xc0 | ||
235 | #define MAS_CMD_READ_D1_MEM 0xd0 | ||
236 | #define MAS_CMD_WRITE_D0_MEM 0xe0 | ||
237 | #define MAS_CMD_WRITE_D1_MEM 0xf0 | ||
238 | |||
239 | /* MAS3587F D0 memory cells */ | ||
240 | #if CONFIG_CODEC == MAS3587F | ||
241 | #define MAS_D0_APP_SELECT 0x7f6 | ||
242 | #define MAS_D0_APP_RUNNING 0x7f7 | ||
243 | #define MAS_D0_ENCODER_CONTROL 0x7f0 | ||
244 | #define MAS_D0_IO_CONTROL_MAIN 0x7f1 | ||
245 | #define MAS_D0_INTERFACE_CONTROL 0x7f2 | ||
246 | #define MAS_D0_OFREQ_CONTROL 0x7f3 | ||
247 | #define MAS_D0_OUT_CLK_CONFIG 0x7f4 | ||
248 | #define MAS_D0_SPD_OUT_BITS 0x7f8 | ||
249 | #define MAS_D0_SOFT_MUTE 0x7f9 | ||
250 | #define MAS_D0_OUT_LL 0x7fc | ||
251 | #define MAS_D0_OUT_LR 0x7fd | ||
252 | #define MAS_D0_OUT_RL 0x7fe | ||
253 | #define MAS_D0_OUT_RR 0x7ff | ||
254 | #define MAS_D0_MPEG_FRAME_COUNT 0xfd0 | ||
255 | #define MAS_D0_MPEG_STATUS_1 0xfd1 | ||
256 | #define MAS_D0_MPEG_STATUS_2 0xfd2 | ||
257 | #define MAS_D0_CRC_ERROR_COUNT 0xfd3 | ||
258 | |||
259 | /* MAS3539F D0 memory cells */ | ||
260 | #elif CONFIG_CODEC == MAS3539F | ||
261 | #define MAS_D0_APP_SELECT 0x34b | ||
262 | #define MAS_D0_APP_RUNNING 0x34c | ||
263 | /* no encoder :( */ | ||
264 | #define MAS_D0_IO_CONTROL_MAIN 0x346 | ||
265 | #define MAS_D0_INTERFACE_CONTROL 0x347 | ||
266 | #define MAS_D0_OFREQ_CONTROL 0x348 | ||
267 | #define MAS_D0_OUT_CLK_CONFIG 0x349 | ||
268 | #define MAS_D0_SPD_OUT_BITS 0x351 | ||
269 | #define MAS_D0_SOFT_MUTE 0x350 | ||
270 | #define MAS_D0_OUT_LL 0x354 | ||
271 | #define MAS_D0_OUT_LR 0x355 | ||
272 | #define MAS_D0_OUT_RL 0x356 | ||
273 | #define MAS_D0_OUT_RR 0x357 | ||
274 | #define MAS_D0_MPEG_FRAME_COUNT 0xfd0 | ||
275 | #define MAS_D0_MPEG_STATUS_1 0xfd1 | ||
276 | #define MAS_D0_MPEG_STATUS_2 0xfd2 | ||
277 | #define MAS_D0_CRC_ERROR_COUNT 0xfd3 | ||
278 | #endif | ||
279 | |||
280 | /* Function prototypes */ | ||
281 | extern void audiohw_set_loudness(int value); | ||
282 | extern void audiohw_set_avc(int value); | ||
283 | extern void audiohw_set_mdb_strength(int value); | ||
284 | extern void audiohw_set_mdb_harmonics(int value); | ||
285 | extern void audiohw_set_mdb_center(int value); | ||
286 | extern void audiohw_set_mdb_shape(int value); | ||
287 | extern void audiohw_set_mdb_enable(int value); | ||
288 | extern void audiohw_set_superbass(int value); | ||
289 | |||
290 | #endif /* CONFIG_CODEC */ | ||
291 | |||
292 | #endif /* _MAS35XX_H */ | ||
diff --git a/firmware/export/mascodec.h b/firmware/export/mascodec.h deleted file mode 100644 index 00690ae7dd..0000000000 --- a/firmware/export/mascodec.h +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef _MASCODEC_H_ | ||
22 | #define _MASCODEC_H_ | ||
23 | |||
24 | /* unused: int mas_default_read(unsigned short *buf); */ | ||
25 | #if CONFIG_CODEC == MAS3507D | ||
26 | int mas_run(unsigned short address); | ||
27 | #endif | ||
28 | int mas_readmem(int bank, int addr, unsigned long* dest, int len); | ||
29 | int mas_writemem(int bank, int addr, const unsigned long* src, int len); | ||
30 | int mas_readreg(int reg); | ||
31 | int mas_writereg(int reg, unsigned int val); | ||
32 | void mas_reset(void); | ||
33 | /* unused: int mas_direct_config_read(unsigned char reg); */ | ||
34 | int mas_direct_config_write(unsigned char reg, unsigned int val); | ||
35 | int mas_codec_writereg(int reg, unsigned int val); | ||
36 | int mas_codec_readreg(int reg); | ||
37 | unsigned long mas_readver(void); | ||
38 | |||
39 | #endif | ||
40 | |||
41 | #if CONFIG_TUNER & S1A0903X01 | ||
42 | void mas_store_pllfreq(int freq); | ||
43 | int mas_get_pllfreq(void); | ||
44 | #endif | ||
45 | |||
diff --git a/firmware/export/mp3_playback.h b/firmware/export/mp3_playback.h index 7434021611..51efb45651 100644 --- a/firmware/export/mp3_playback.h +++ b/firmware/export/mp3_playback.h | |||
@@ -39,15 +39,6 @@ void mp3_init(int volume, int bass, int treble, int balance, int loudness, | |||
39 | int mdb_center, int mdb_shape, bool mdb_enable, | 39 | int mdb_center, int mdb_shape, bool mdb_enable, |
40 | bool superbass); | 40 | bool superbass); |
41 | 41 | ||
42 | /* exported just for mpeg.c, to keep the recording there */ | ||
43 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) | ||
44 | void demand_irq_enable(bool on); | ||
45 | #endif | ||
46 | |||
47 | /* new functions, exported to plugin API */ | ||
48 | #if CONFIG_CODEC == MAS3587F | ||
49 | void mp3_play_init(void); | ||
50 | #endif | ||
51 | void mp3_play_data(const void* start, size_t size, | 42 | void mp3_play_data(const void* start, size_t size, |
52 | mp3_play_callback_t get_more); | 43 | mp3_play_callback_t get_more); |
53 | void mp3_play_pause(bool play); | 44 | void mp3_play_pause(bool play); |
diff --git a/firmware/export/rtc.h b/firmware/export/rtc.h index 216de87dea..a668c9c729 100644 --- a/firmware/export/rtc.h +++ b/firmware/export/rtc.h | |||
@@ -38,16 +38,6 @@ void rtc_init(void); | |||
38 | int rtc_read_datetime(struct tm *tm); | 38 | int rtc_read_datetime(struct tm *tm); |
39 | int rtc_write_datetime(const struct tm *tm); | 39 | int rtc_write_datetime(const struct tm *tm); |
40 | 40 | ||
41 | #if CONFIG_RTC == RTC_M41ST84W | ||
42 | |||
43 | /* The RTC in the Archos devices is used for much more than just the clock | ||
44 | data */ | ||
45 | int rtc_read(unsigned char address); | ||
46 | int rtc_read_multiple(unsigned char address, unsigned char *buf, int numbytes); | ||
47 | int rtc_write(unsigned char address, unsigned char value); | ||
48 | |||
49 | #endif /* RTC_M41ST84W */ | ||
50 | |||
51 | #ifdef HAVE_RTC_ALARM | 41 | #ifdef HAVE_RTC_ALARM |
52 | void rtc_set_alarm(int h, int m); | 42 | void rtc_set_alarm(int h, int m); |
53 | void rtc_get_alarm(int *h, int *m); | 43 | void rtc_get_alarm(int *h, int *m); |
diff --git a/firmware/export/s1a0903x01.h b/firmware/export/s1a0903x01.h deleted file mode 100644 index d9f1a11baf..0000000000 --- a/firmware/export/s1a0903x01.h +++ /dev/null | |||
@@ -1,42 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * Tuner header for the Samsung S1A0903X01 | ||
10 | * | ||
11 | * Copyright (C) 2007 Michael Sevakis | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License | ||
15 | * as published by the Free Software Foundation; either version 2 | ||
16 | * of the License, or (at your option) any later version. | ||
17 | * | ||
18 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
19 | * KIND, either express or implied. | ||
20 | * | ||
21 | ****************************************************************************/ | ||
22 | |||
23 | #ifndef _S1A0903X01_H_ | ||
24 | #define _S1A0903X01_H_ | ||
25 | |||
26 | /* Define additional tuner messages here */ | ||
27 | #define HAVE_RADIO_MUTE_TIMEOUT | ||
28 | |||
29 | #if 0 | ||
30 | #define S1A0903X01_IF_MEASUREMENT (RADIO_SET_CHIP_FIRST+0) | ||
31 | #define S1A0903X01_SENSITIVITY (RADIO_SET_CHIP_FIRST+1) | ||
32 | #endif | ||
33 | |||
34 | int s1a0903x01_set(int setting, int value); | ||
35 | int s1a0903x01_get(int setting); | ||
36 | |||
37 | #ifndef CONFIG_TUNER_MULTI | ||
38 | #define tuner_get s1a0903x01_get | ||
39 | #define tuner_set s1a0903x01_set | ||
40 | #endif | ||
41 | |||
42 | #endif /* _S1A0903X01_H_ */ | ||
diff --git a/firmware/export/sh7034.h b/firmware/export/sh7034.h deleted file mode 100644 index 2695acbc00..0000000000 --- a/firmware/export/sh7034.h +++ /dev/null | |||
@@ -1,376 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Alan Korr | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __SH7034_H__ | ||
23 | #define __SH7034_H__ | ||
24 | |||
25 | #define GBR 0x00000000 | ||
26 | |||
27 | /* register address macros: */ | ||
28 | |||
29 | #define SMR0_ADDR 0x05FFFEC0 | ||
30 | #define BRR0_ADDR 0x05FFFEC1 | ||
31 | #define SCR0_ADDR 0x05FFFEC2 | ||
32 | #define TDR0_ADDR 0x05FFFEC3 | ||
33 | #define SSR0_ADDR 0x05FFFEC4 | ||
34 | #define RDR0_ADDR 0x05FFFEC5 | ||
35 | #define SMR1_ADDR 0x05FFFEC8 | ||
36 | #define BRR1_ADDR 0x05FFFEC9 | ||
37 | #define SCR1_ADDR 0x05FFFECA | ||
38 | #define TDR1_ADDR 0x05FFFECB | ||
39 | #define SSR1_ADDR 0x05FFFECC | ||
40 | #define RDR1_ADDR 0x05FFFECD | ||
41 | |||
42 | #define ADDRAH_ADDR 0x05FFFEE0 | ||
43 | #define ADDRAL_ADDR 0x05FFFEE1 | ||
44 | #define ADDRBH_ADDR 0x05FFFEE2 | ||
45 | #define ADDRBL_ADDR 0x05FFFEE3 | ||
46 | #define ADDRCH_ADDR 0x05FFFEE4 | ||
47 | #define ADDRCL_ADDR 0x05FFFEE5 | ||
48 | #define ADDRDH_ADDR 0x05FFFEE6 | ||
49 | #define ADDRDL_ADDR 0x05FFFEE7 | ||
50 | #define ADCSR_ADDR 0x05FFFEE8 | ||
51 | #define ADCR_ADDR 0x05FFFEE9 | ||
52 | |||
53 | #define TSTR_ADDR 0x05FFFF00 | ||
54 | #define TSNC_ADDR 0x05FFFF01 | ||
55 | #define TMDR_ADDR 0x05FFFF02 | ||
56 | #define TFCR_ADDR 0x05FFFF03 | ||
57 | #define TCR0_ADDR 0x05FFFF04 | ||
58 | #define TIOR0_ADDR 0x05FFFF05 | ||
59 | #define TIER0_ADDR 0x05FFFF06 | ||
60 | #define TSR0_ADDR 0x05FFFF07 | ||
61 | #define TCNT0_ADDR 0x05FFFF08 | ||
62 | #define GRA0_ADDR 0x05FFFF0A | ||
63 | #define GRB0_ADDR 0x05FFFF0C | ||
64 | #define TCR1_ADDR 0x05FFFF0E | ||
65 | #define TIOR1_ADDR 0x05FFFF0F | ||
66 | #define TIER1_ADDR 0x05FFFF10 | ||
67 | #define TSR1_ADDR 0x05FFFF11 | ||
68 | #define TCNT1_ADDR 0x05FFFF12 | ||
69 | #define GRA1_ADDR 0x05FFFF14 | ||
70 | #define GRB1_ADDR 0x05FFFF16 | ||
71 | #define TCR2_ADDR 0x05FFFF18 | ||
72 | #define TIOR2_ADDR 0x05FFFF19 | ||
73 | #define TIER2_ADDR 0x05FFFF1A | ||
74 | #define TSR2_ADDR 0x05FFFF1B | ||
75 | #define TCNT2_ADDR 0x05FFFF1C | ||
76 | #define GRA2_ADDR 0x05FFFF1E | ||
77 | #define GRB2_ADDR 0x05FFFF20 | ||
78 | #define TCR3_ADDR 0x05FFFF22 | ||
79 | #define TIOR3_ADDR 0x05FFFF23 | ||
80 | #define TIER3_ADDR 0x05FFFF24 | ||
81 | #define TSR3_ADDR 0x05FFFF25 | ||
82 | #define TCNT3_ADDR 0x05FFFF26 | ||
83 | #define GRA3_ADDR 0x05FFFF28 | ||
84 | #define GRB3_ADDR 0x05FFFF2A | ||
85 | #define BRA3_ADDR 0x05FFFF2C | ||
86 | #define BRB3_ADDR 0x05FFFF2E | ||
87 | #define TOCR_ADDR 0x05FFFF31 | ||
88 | #define TCR4_ADDR 0x05FFFF32 | ||
89 | #define TIOR4_ADDR 0x05FFFF33 | ||
90 | #define TIER4_ADDR 0x05FFFF34 | ||
91 | #define TSR4_ADDR 0x05FFFF35 | ||
92 | #define TCNT4_ADDR 0x05FFFF36 | ||
93 | #define GRA4_ADDR 0x05FFFF38 | ||
94 | #define GRB4_ADDR 0x05FFFF3A | ||
95 | #define BRA4_ADDR 0x05FFFF3C | ||
96 | #define BRB4_ADDR 0x05FFFF3E | ||
97 | |||
98 | #define SAR0_ADDR 0x05FFFF40 | ||
99 | #define DAR0_ADDR 0x05FFFF44 | ||
100 | #define DMAOR_ADDR 0x05FFFF48 | ||
101 | #define DTCR0_ADDR 0x05FFFF4A | ||
102 | #define CHCR0_ADDR 0x05FFFF4E | ||
103 | #define SAR1_ADDR 0x05FFFF50 | ||
104 | #define DAR1_ADDR 0x05FFFF54 | ||
105 | #define DTCR1_ADDR 0x05FFFF5A | ||
106 | #define CHCR1_ADDR 0x05FFFF5E | ||
107 | #define SAR2_ADDR 0x05FFFF60 | ||
108 | #define DAR2_ADDR 0x05FFFF64 | ||
109 | #define DTCR2_ADDR 0x05FFFF6A | ||
110 | #define CHCR2_ADDR 0x05FFFF6E | ||
111 | #define SAR3_ADDR 0x05FFFF70 | ||
112 | #define DAR3_ADDR 0x05FFFF74 | ||
113 | #define DTCR3_ADDR 0x05FFFF7A | ||
114 | #define CHCR3_ADDR 0x05FFFF7E | ||
115 | |||
116 | #define IPRA_ADDR 0x05FFFF84 | ||
117 | #define IPRB_ADDR 0x05FFFF86 | ||
118 | #define IPRC_ADDR 0x05FFFF88 | ||
119 | #define IPRD_ADDR 0x05FFFF8A | ||
120 | #define IPRE_ADDR 0x05FFFF8C | ||
121 | #define ICR_ADDR 0x05FFFF8E | ||
122 | |||
123 | #define BARH_ADDR 0x05FFFF90 | ||
124 | #define BARL_ADDR 0x05FFFF92 | ||
125 | #define BAMRH_ADDR 0x05FFFF94 | ||
126 | #define BAMRL_ADDR 0x05FFFF96 | ||
127 | #define BBR_ADDR 0x05FFFF98 | ||
128 | |||
129 | #define BCR_ADDR 0x05FFFFA0 | ||
130 | #define WCR1_ADDR 0x05FFFFA2 | ||
131 | #define WCR2_ADDR 0x05FFFFA4 | ||
132 | #define WCR3_ADDR 0x05FFFFA6 | ||
133 | #define DCR_ADDR 0x05FFFFA8 | ||
134 | #define PCR_ADDR 0x05FFFFAA | ||
135 | #define RCR_ADDR 0x05FFFFAC | ||
136 | #define RTCSR_ADDR 0x05FFFFAE | ||
137 | #define RTCNT_ADDR 0x05FFFFB0 | ||
138 | #define RTCOR_ADDR 0x05FFFFB2 | ||
139 | |||
140 | #define TCSR_ADDR 0x05FFFFB8 | ||
141 | #define TCNT_ADDR 0x05FFFFB9 | ||
142 | #define RSTCSR_ADDR 0x05FFFFBB | ||
143 | |||
144 | #define SBYCR_ADDR 0x05FFFFBC | ||
145 | |||
146 | #define PADR_ADDR 0x05FFFFC0 | ||
147 | #define PBDR_ADDR 0x05FFFFC2 | ||
148 | #define PAIOR_ADDR 0x05FFFFC4 | ||
149 | #define PBIOR_ADDR 0x05FFFFC6 | ||
150 | #define PACR1_ADDR 0x05FFFFC8 | ||
151 | #define PACR2_ADDR 0x05FFFFCA | ||
152 | #define PBCR1_ADDR 0x05FFFFCC | ||
153 | #define PBCR2_ADDR 0x05FFFFCE | ||
154 | #define PCDR_ADDR 0x05FFFFD0 | ||
155 | |||
156 | #define CASCR_ADDR 0x05FFFFEE | ||
157 | |||
158 | /* byte halves of the ports */ | ||
159 | #define PADRH_ADDR 0x05FFFFC0 | ||
160 | #define PADRL_ADDR 0x05FFFFC1 | ||
161 | #define PBDRH_ADDR 0x05FFFFC2 | ||
162 | #define PBDRL_ADDR 0x05FFFFC3 | ||
163 | #define PAIORH_ADDR 0x05FFFFC4 | ||
164 | #define PAIORL_ADDR 0x05FFFFC5 | ||
165 | #define PBIORH_ADDR 0x05FFFFC6 | ||
166 | #define PBIORL_ADDR 0x05FFFFC7 | ||
167 | |||
168 | |||
169 | /* A/D control/status register bits */ | ||
170 | #define ADCSR_CH 0x07 /* Channel/group select */ | ||
171 | #define ADCSR_CKS 0x08 /* Clock select */ | ||
172 | #define ADCSR_SCAN 0x10 /* Scan mode */ | ||
173 | #define ADCSR_ADST 0x20 /* A/D start */ | ||
174 | #define ADCSR_ADIE 0x40 /* A/D interrupt enable */ | ||
175 | #define ADCSR_ADF 0x80 /* A/D end flag */ | ||
176 | |||
177 | /* A/D control register bits */ | ||
178 | #define ADCR_TRGE 0x80 /* Trigger enable */ | ||
179 | |||
180 | /* register macros for direct access: */ | ||
181 | |||
182 | #define SMR0 (*((volatile unsigned char*)SMR0_ADDR)) | ||
183 | #define BRR0 (*((volatile unsigned char*)BRR0_ADDR)) | ||
184 | #define SCR0 (*((volatile unsigned char*)SCR0_ADDR)) | ||
185 | #define TDR0 (*((volatile unsigned char*)TDR0_ADDR)) | ||
186 | #define SSR0 (*((volatile unsigned char*)SSR0_ADDR)) | ||
187 | #define RDR0 (*((volatile unsigned char*)RDR0_ADDR)) | ||
188 | #define SMR1 (*((volatile unsigned char*)SMR1_ADDR)) | ||
189 | #define BRR1 (*((volatile unsigned char*)BRR1_ADDR)) | ||
190 | #define SCR1 (*((volatile unsigned char*)SCR1_ADDR)) | ||
191 | #define TDR1 (*((volatile unsigned char*)TDR1_ADDR)) | ||
192 | #define SSR1 (*((volatile unsigned char*)SSR1_ADDR)) | ||
193 | #define RDR1 (*((volatile unsigned char*)RDR1_ADDR)) | ||
194 | |||
195 | #define ADDRA (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */ | ||
196 | #define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR)) | ||
197 | #define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR)) | ||
198 | #define ADDRB (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */ | ||
199 | #define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR)) | ||
200 | #define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR)) | ||
201 | #define ADDRC (*((volatile unsigned short*)ADDRCH_ADDR)) /* combined */ | ||
202 | #define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR)) | ||
203 | #define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR)) | ||
204 | #define ADDRD (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */ | ||
205 | #define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR)) | ||
206 | #define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR)) | ||
207 | #define ADCSR (*((volatile unsigned char*)ADCSR_ADDR)) | ||
208 | #define ADCR (*((volatile unsigned char*)ADCR_ADDR)) | ||
209 | |||
210 | #define TSTR (*((volatile unsigned char*)TSTR_ADDR)) | ||
211 | #define TSNC (*((volatile unsigned char*)TSNC_ADDR)) | ||
212 | #define TMDR (*((volatile unsigned char*)TMDR_ADDR)) | ||
213 | #define TFCR (*((volatile unsigned char*)TFCR_ADDR)) | ||
214 | #define TCR0 (*((volatile unsigned char*)TCR0_ADDR)) | ||
215 | #define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR)) | ||
216 | #define TIER0 (*((volatile unsigned char*)TIER0_ADDR)) | ||
217 | #define TSR0 (*((volatile unsigned char*)TSR0_ADDR)) | ||
218 | #define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR)) | ||
219 | #define GRA0 (*((volatile unsigned short*)GRA0_ADDR)) | ||
220 | #define GRB0 (*((volatile unsigned short*)GRB0_ADDR)) | ||
221 | #define TCR1 (*((volatile unsigned char*)TCR1_ADDR)) | ||
222 | #define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR)) | ||
223 | #define TIER1 (*((volatile unsigned char*)TIER1_ADDR)) | ||
224 | #define TSR1 (*((volatile unsigned char*)TSR1_ADDR)) | ||
225 | #define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR)) | ||
226 | #define GRA1 (*((volatile unsigned short*)GRA1_ADDR)) | ||
227 | #define GRB1 (*((volatile unsigned short*)GRB1_ADDR)) | ||
228 | #define TCR2 (*((volatile unsigned char*)TCR2_ADDR)) | ||
229 | #define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR)) | ||
230 | #define TIER2 (*((volatile unsigned char*)TIER2_ADDR)) | ||
231 | #define TSR2 (*((volatile unsigned char*)TSR2_ADDR)) | ||
232 | #define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR)) | ||
233 | #define GRA2 (*((volatile unsigned short*)GRA2_ADDR)) | ||
234 | #define GRB2 (*((volatile unsigned short*)GRB2_ADDR)) | ||
235 | #define TCR3 (*((volatile unsigned char*)TCR3_ADDR)) | ||
236 | #define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR)) | ||
237 | #define TIER3 (*((volatile unsigned char*)TIER3_ADDR)) | ||
238 | #define TSR3 (*((volatile unsigned char*)TSR3_ADDR)) | ||
239 | #define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR)) | ||
240 | #define GRA3 (*((volatile unsigned short*)GRA3_ADDR)) | ||
241 | #define GRB3 (*((volatile unsigned short*)GRB3_ADDR)) | ||
242 | #define BRA3 (*((volatile unsigned short*)BRA3_ADDR)) | ||
243 | #define BRB3 (*((volatile unsigned short*)BRB3_ADDR)) | ||
244 | #define TOCR (*((volatile unsigned char*)TOCR_ADDR)) | ||
245 | #define TCR4 (*((volatile unsigned char*)TCR4_ADDR)) | ||
246 | #define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR)) | ||
247 | #define TIER4 (*((volatile unsigned char*)TIER4_ADDR)) | ||
248 | #define TSR4 (*((volatile unsigned char*)TSR4_ADDR)) | ||
249 | #define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR)) | ||
250 | #define GRA4 (*((volatile unsigned short*)GRA4_ADDR)) | ||
251 | #define GRB4 (*((volatile unsigned short*)GRB4_ADDR)) | ||
252 | #define BRA4 (*((volatile unsigned short*)BRA4_ADDR)) | ||
253 | #define BRB4 (*((volatile unsigned short*)BRB4_ADDR)) | ||
254 | |||
255 | #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) | ||
256 | #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) | ||
257 | #define DMAOR (*((volatile unsigned short*)DMAOR_ADDR)) | ||
258 | #define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR)) | ||
259 | #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) | ||
260 | #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) | ||
261 | #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) | ||
262 | #define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR)) | ||
263 | #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) | ||
264 | #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) | ||
265 | #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) | ||
266 | #define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR)) | ||
267 | #define CHCR2 (*((volatile unsigned short*)CHCR2_ADDR)) | ||
268 | #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) | ||
269 | #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) | ||
270 | #define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR)) | ||
271 | #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) | ||
272 | |||
273 | #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) | ||
274 | #define IPRB (*((volatile unsigned short*)IPRB_ADDR)) | ||
275 | #define IPRC (*((volatile unsigned short*)IPRC_ADDR)) | ||
276 | #define IPRD (*((volatile unsigned short*)IPRD_ADDR)) | ||
277 | #define IPRE (*((volatile unsigned short*)IPRE_ADDR)) | ||
278 | #define ICR (*((volatile unsigned short*)ICR_ADDR)) | ||
279 | |||
280 | #define BAR (*((volatile unsigned long*)BARH_ADDR)) /* combined */ | ||
281 | #define BARH (*((volatile unsigned short*)BARH_ADDR)) | ||
282 | #define BARL (*((volatile unsigned short*)BARL_ADDR)) | ||
283 | #define BAMR (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */ | ||
284 | #define BAMRH (*((volatile unsigned short*)BAMRH_ADDR)) | ||
285 | #define BAMRL (*((volatile unsigned short*)BAMRL_ADDR)) | ||
286 | #define BBR (*((volatile unsigned short*)BBR_ADDR)) | ||
287 | |||
288 | #define BCR (*((volatile unsigned short*)BCR_ADDR)) | ||
289 | #define WCR1 (*((volatile unsigned short*)WCR1_ADDR)) | ||
290 | #define WCR2 (*((volatile unsigned short*)WCR2_ADDR)) | ||
291 | #define WCR3 (*((volatile unsigned short*)WCR3_ADDR)) | ||
292 | #define DCR (*((volatile unsigned short*)DCR_ADDR)) | ||
293 | #define PCR (*((volatile unsigned short*)PCR_ADDR)) | ||
294 | #define RCR (*((volatile unsigned short*)RCR_ADDR)) | ||
295 | #define RTCSR (*((volatile unsigned short*)RTCSR_ADDR)) | ||
296 | #define RTCNT (*((volatile unsigned short*)RTCNT_ADDR)) | ||
297 | #define RTCOR (*((volatile unsigned short*)RTCOR_ADDR)) | ||
298 | |||
299 | #define TCSR_R (*((volatile unsigned char*)TCSR_ADDR)) | ||
300 | #define TCSR_W (*((volatile unsigned short*)(TCSR_ADDR & ~1))) | ||
301 | #define TCNT_R (*((volatile unsigned char*)TCNT_ADDR)) | ||
302 | #define TCNT_W (*((volatile unsigned short*)(TCNT_ADDR & ~1))) | ||
303 | #define RSTCSR_R (*((volatile unsigned char*)RSTCSR_ADDR)) | ||
304 | #define RSTCSR_W (*((volatile unsigned short*)(RSTCSR_ADDR & ~1))) | ||
305 | |||
306 | #define SBYCR (*((volatile unsigned char*)SBYCR_ADDR)) | ||
307 | |||
308 | #define PADR (*((volatile unsigned short*)PADR_ADDR)) | ||
309 | #define PBDR (*((volatile unsigned short*)PBDR_ADDR)) | ||
310 | #define PAIOR (*((volatile unsigned short*)PAIOR_ADDR)) | ||
311 | #define PBIOR (*((volatile unsigned short*)PBIOR_ADDR)) | ||
312 | #define PACR1 (*((volatile unsigned short*)PACR1_ADDR)) | ||
313 | #define PACR2 (*((volatile unsigned short*)PACR2_ADDR)) | ||
314 | #define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR)) | ||
315 | #define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR)) | ||
316 | #define PCDR (*((volatile unsigned short*)PCDR_ADDR)) | ||
317 | |||
318 | #define CASCR (*((volatile unsigned char*)CASCR_ADDR)) | ||
319 | |||
320 | /* byte halves of the ports */ | ||
321 | #define PADRH (*((volatile unsigned char*)PADRH_ADDR)) | ||
322 | #define PADRL (*((volatile unsigned char*)PADRL_ADDR)) | ||
323 | #define PBDRH (*((volatile unsigned char*)PBDRH_ADDR)) | ||
324 | #define PBDRL (*((volatile unsigned char*)PBDRL_ADDR)) | ||
325 | #define PAIORH (*((volatile unsigned char*)PAIORH_ADDR)) | ||
326 | #define PAIORL (*((volatile unsigned char*)PAIORL_ADDR)) | ||
327 | #define PBIORH (*((volatile unsigned char*)PBIORH_ADDR)) | ||
328 | #define PBIORL (*((volatile unsigned char*)PBIORL_ADDR)) | ||
329 | |||
330 | |||
331 | /*************************************************************************** | ||
332 | * Register bit definitions | ||
333 | **************************************************************************/ | ||
334 | |||
335 | /* | ||
336 | * Serial mode register bits | ||
337 | */ | ||
338 | |||
339 | #define SYNC_MODE 0x80 | ||
340 | #define SEVEN_BIT_DATA 0x40 | ||
341 | #define PARITY_ON 0x20 | ||
342 | #define ODD_PARITY 0x10 | ||
343 | #define STOP_BITS_2 0x08 | ||
344 | #define ENABLE_MULTIP 0x04 | ||
345 | #define PHI_64 0x03 | ||
346 | #define PHI_16 0x02 | ||
347 | #define PHI_4 0x01 | ||
348 | |||
349 | /* | ||
350 | * Serial control register bits | ||
351 | */ | ||
352 | #define SCI_TIE 0x80 /* Transmit interrupt enable */ | ||
353 | #define SCI_RIE 0x40 /* Receive interrupt enable */ | ||
354 | #define SCI_TE 0x20 /* Transmit enable */ | ||
355 | #define SCI_RE 0x10 /* Receive enable */ | ||
356 | #define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ | ||
357 | #define SCI_TEIE 0x04 /* Transmit end interrupt enable */ | ||
358 | #define SCI_CKE1 0x02 /* Clock enable 1 */ | ||
359 | #define SCI_CKE0 0x01 /* Clock enable 0 */ | ||
360 | |||
361 | /* | ||
362 | * Serial status register bits | ||
363 | */ | ||
364 | #define SCI_TDRE 0x80 /* Transmit data register empty */ | ||
365 | #define SCI_RDRF 0x40 /* Receive data register full */ | ||
366 | #define SCI_ORER 0x20 /* Overrun error */ | ||
367 | #define SCI_FER 0x10 /* Framing error */ | ||
368 | #define SCI_PER 0x08 /* Parity error */ | ||
369 | #define SCI_TEND 0x04 /* Transmit end */ | ||
370 | #define SCI_MPB 0x02 /* Multiprocessor bit */ | ||
371 | #define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ | ||
372 | |||
373 | /* Timer frequency */ | ||
374 | #define TIMER_FREQ CPU_FREQ | ||
375 | |||
376 | #endif | ||
diff --git a/firmware/export/sound.h b/firmware/export/sound.h index 3a26e30b68..9bcb9a8513 100644 --- a/firmware/export/sound.h +++ b/firmware/export/sound.h | |||
@@ -109,17 +109,6 @@ void sound_set_hw_eq_band5_frequency(int value); | |||
109 | #endif /* AUDIOHW_HAVE_EQ_BAND5 */ | 109 | #endif /* AUDIOHW_HAVE_EQ_BAND5 */ |
110 | #endif /* AUDIOHW_HAVE_EQ */ | 110 | #endif /* AUDIOHW_HAVE_EQ */ |
111 | 111 | ||
112 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) | ||
113 | void sound_set_loudness(int value); | ||
114 | void sound_set_avc(int value); | ||
115 | void sound_set_mdb_strength(int value); | ||
116 | void sound_set_mdb_harmonics(int value); | ||
117 | void sound_set_mdb_center(int value); | ||
118 | void sound_set_mdb_shape(int value); | ||
119 | void sound_set_mdb_enable(int value); | ||
120 | void sound_set_superbass(int value); | ||
121 | #endif /* (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) */ | ||
122 | |||
123 | void sound_set(int setting, int value); | 112 | void sound_set(int setting, int value); |
124 | int sound_val2phys(int setting, int value); | 113 | int sound_val2phys(int setting, int value); |
125 | 114 | ||
diff --git a/firmware/export/tuner.h b/firmware/export/tuner.h index a166eacf33..a3cc985137 100644 --- a/firmware/export/tuner.h +++ b/firmware/export/tuner.h | |||
@@ -22,8 +22,9 @@ | |||
22 | #ifndef __TUNER_H__ | 22 | #ifndef __TUNER_H__ |
23 | #define __TUNER_H__ | 23 | #define __TUNER_H__ |
24 | 24 | ||
25 | #include <stdbool.h> | ||
26 | |||
25 | #include "config.h" | 27 | #include "config.h" |
26 | #include "hwcompat.h" | ||
27 | 28 | ||
28 | #ifdef HAVE_RDS_CAP | 29 | #ifdef HAVE_RDS_CAP |
29 | #include <sys/types.h> | 30 | #include <sys/types.h> |
@@ -114,12 +115,6 @@ extern int (*tuner_get)(int setting); | |||
114 | #include "lv24020lp.h" | 115 | #include "lv24020lp.h" |
115 | #endif | 116 | #endif |
116 | 117 | ||
117 | /** Samsung S1A0903X01 **/ | ||
118 | #if (CONFIG_TUNER & S1A0903X01) | ||
119 | /* Ondio FM, FM Recorder */ | ||
120 | #include "s1a0903x01.h" | ||
121 | #endif | ||
122 | |||
123 | /** Philips TEA5760 **/ | 118 | /** Philips TEA5760 **/ |
124 | #if (CONFIG_TUNER & TEA5760) | 119 | #if (CONFIG_TUNER & TEA5760) |
125 | #include "tea5760.h" | 120 | #include "tea5760.h" |
diff --git a/firmware/export/usb.h b/firmware/export/usb.h index 0c74efc9e2..d723f85b1a 100644 --- a/firmware/export/usb.h +++ b/firmware/export/usb.h | |||
@@ -134,14 +134,8 @@ enum | |||
134 | }; | 134 | }; |
135 | 135 | ||
136 | #ifdef HAVE_USB_POWER | 136 | #ifdef HAVE_USB_POWER |
137 | #if CONFIG_KEYPAD == RECORDER_PAD | ||
138 | #define USBPOWER_BUTTON BUTTON_F1 | ||
139 | #define USBPOWER_BTN_IGNORE BUTTON_ON | ||
140 | #elif CONFIG_KEYPAD == ONDIO_PAD | ||
141 | #define USBPOWER_BUTTON BUTTON_MENU | ||
142 | #define USBPOWER_BTN_IGNORE BUTTON_OFF | ||
143 | /*allow people to define this in config-target.h if they need it*/ | 137 | /*allow people to define this in config-target.h if they need it*/ |
144 | #elif !defined(USBPOWER_BTN_IGNORE) | 138 | #if !defined(USBPOWER_BTN_IGNORE) |
145 | #define USBPOWER_BTN_IGNORE 0 | 139 | #define USBPOWER_BTN_IGNORE 0 |
146 | #endif | 140 | #endif |
147 | #endif | 141 | #endif |