From 092c340a2062fa98b7387fc5fd63578ddae7d0b6 Mon Sep 17 00:00:00 2001 From: Solomon Peachy Date: Wed, 15 Jul 2020 19:40:55 -0400 Subject: [1/4] Remove SH support and all archos targets This removes all code specific to SH targets Change-Id: I7980523785d2596e65c06430f4638eec74a06061 --- firmware/export/audiohw.h | 2 - firmware/export/audiohw_settings.h | 10 - firmware/export/config.h | 48 +--- firmware/export/config/archosfmrecorder.h | 147 ------------ firmware/export/config/archosondiofm.h | 147 ------------ firmware/export/config/archosondiosp.h | 131 ----------- firmware/export/config/archosplayer.h | 111 --------- firmware/export/config/archosrecorder.h | 141 ----------- firmware/export/config/archosrecorderv2.h | 147 ------------ firmware/export/cpu.h | 3 - firmware/export/hwcompat.h | 31 --- firmware/export/mas35xx.h | 292 ----------------------- firmware/export/mascodec.h | 45 ---- firmware/export/mp3_playback.h | 9 - firmware/export/rtc.h | 10 - firmware/export/s1a0903x01.h | 42 ---- firmware/export/sh7034.h | 376 ------------------------------ firmware/export/sound.h | 11 - firmware/export/tuner.h | 9 +- firmware/export/usb.h | 8 +- 20 files changed, 9 insertions(+), 1711 deletions(-) delete mode 100644 firmware/export/config/archosfmrecorder.h delete mode 100644 firmware/export/config/archosondiofm.h delete mode 100644 firmware/export/config/archosondiosp.h delete mode 100644 firmware/export/config/archosplayer.h delete mode 100644 firmware/export/config/archosrecorder.h delete mode 100644 firmware/export/config/archosrecorderv2.h delete mode 100644 firmware/export/mas35xx.h delete mode 100644 firmware/export/mascodec.h delete mode 100644 firmware/export/s1a0903x01.h delete mode 100644 firmware/export/sh7034.h (limited to 'firmware/export') diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h index f22e72554d..490c8fc571 100644 --- a/firmware/export/audiohw.h +++ b/firmware/export/audiohw.h @@ -184,8 +184,6 @@ struct sound_settings_info #include "tlv320.h" #elif defined(HAVE_AS3514) #include "as3514.h" -#elif defined(HAVE_MAS35XX) -#include "mas35xx.h" #if defined(HAVE_DAC3550A) #include "dac3550a.h" #endif /* HAVE_DAC3550A */ diff --git a/firmware/export/audiohw_settings.h b/firmware/export/audiohw_settings.h index 675ec59a7b..1d3e0dc12f 100644 --- a/firmware/export/audiohw_settings.h +++ b/firmware/export/audiohw_settings.h @@ -84,16 +84,6 @@ AUDIOHW_SETTINGS( AUDIOHW_SETTING_ENT(BALANCE, sound_set_balance) AUDIOHW_SETTING_ENT(CHANNELS, sound_set_channels) AUDIOHW_SETTING_ENT(STEREO_WIDTH, sound_set_stereo_width) -#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) - AUDIOHW_SETTING_ENT(LOUDNESS, sound_set_loudness) - AUDIOHW_SETTING_ENT(AVC, sound_set_avc) - AUDIOHW_SETTING_ENT(MDB_STRENGTH, sound_set_mdb_strength) - AUDIOHW_SETTING_ENT(MDB_HARMONICS, sound_set_mdb_harmonics) - AUDIOHW_SETTING_ENT(MDB_CENTER, sound_set_mdb_center) - AUDIOHW_SETTING_ENT(MDB_SHAPE, sound_set_mdb_shape) - AUDIOHW_SETTING_ENT(MDB_ENABLE, sound_set_mdb_enable) - AUDIOHW_SETTING_ENT(SUPERBASS, sound_set_superbass) -#endif /* (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) */ #if defined(AUDIOHW_HAVE_LIN_GAIN) AUDIOHW_SETTING_ENT(LEFT_GAIN, NULL) AUDIOHW_SETTING_ENT(RIGHT_GAIN, NULL) diff --git a/firmware/export/config.h b/firmware/export/config.h index 4f9cd02097..6ce9bede41 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -44,7 +44,6 @@ #define STORAGE_HOSTFS (1 << STORAGE_HOSTFS_NUM) /* CONFIG_TUNER (note these are combineable bit-flags) */ -#define S1A0903X01 0x01 /* Samsung */ #define TEA5767 0x02 /* Philips */ #define LV24020LP 0x04 /* Sanyo */ #define SI4700 0x08 /* Silicon Labs */ @@ -55,13 +54,9 @@ #define STFM1000 0x100 /* Sigmatel */ /* CONFIG_CODEC */ -#define MAS3587F 3587 -#define MAS3507D 3507 -#define MAS3539F 3539 #define SWCODEC 1 /* if codec is done by SW */ /* CONFIG_CPU */ -#define SH7034 7034 #define MCF5249 5249 #define MCF5250 5250 #define PP5002 5002 @@ -103,9 +98,6 @@ #define PLATFORM_PANDORA (1<<6) /* CONFIG_KEYPAD */ -#define PLAYER_PAD 1 -#define RECORDER_PAD 2 -#define ONDIO_PAD 3 #define IRIVER_H100_PAD 4 #define IRIVER_H300_PAD 5 #define IAUDIO_X5M5_PAD 6 @@ -222,8 +214,7 @@ if the estimation is better that ours (which it probably is) */ /* CONFIG_LCD */ -#define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */ -#define LCD_SSD1801 2 /* as used by Archos Player/Studio */ +#define LCD_SSD1815 1 /* as used by Sansa M200 and others */ #define LCD_S1D15E06 3 /* as used by iRiver H100 series */ #define LCD_H300 4 /* as used by iRiver H300 series, exact model name is unknown at the time of this writing */ @@ -312,8 +303,6 @@ /* CONFIG_I2C */ #define I2C_NONE 0 /* For targets that do not use I2C - as the Lyre prototype 1 */ -#define I2C_PLAYREC 1 /* Archos Player/Recorder style */ -#define I2C_ONDIO 2 /* Ondio style */ #define I2C_COLDFIRE 3 /* Coldfire style */ #define I2C_PP5002 4 /* PP5002 style */ #define I2C_PP5020 5 /* PP5020 style */ @@ -345,7 +334,6 @@ Lyre prototype 1 */ #define NAND_IMX233 6 /* CONFIG_RTC */ -#define RTC_M41ST84W 1 /* Archos Recorder */ #define RTC_PCF50605 2 /* iPod 3G, 4G & Mini */ #define RTC_PCF50606 3 /* iriver H300 */ #define RTC_S3C2440 4 @@ -398,19 +386,7 @@ Lyre prototype 1 */ #define IMX233_CREATIVE (1 << 1) /* Creative MBLK windowing */ /* now go and pick yours */ -#if defined(ARCHOS_PLAYER) -#include "config/archosplayer.h" -#elif defined(ARCHOS_RECORDER) -#include "config/archosrecorder.h" -#elif defined(ARCHOS_FMRECORDER) -#include "config/archosfmrecorder.h" -#elif defined(ARCHOS_RECORDERV2) -#include "config/archosrecorderv2.h" -#elif defined(ARCHOS_ONDIOSP) -#include "config/archosondiosp.h" -#elif defined(ARCHOS_ONDIOFM) -#include "config/archosondiofm.h" -#elif defined(IRIVER_H100) +#if defined(IRIVER_H100) #include "config/iriverh100.h" #elif defined(IRIVER_H120) #include "config/iriverh120.h" @@ -659,11 +635,6 @@ Lyre prototype 1 */ #ifndef __PCTOOL__ -/* define for all cpus from SH family */ -#if (ARCH == ARCH_SH) && (CONFIG_CPU == SH7034) -#define CPU_SH -#endif - /* define for all cpus from coldfire family */ #if (ARCH == ARCH_M68K) && ((CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250)) #define CPU_COLDFIRE @@ -932,11 +903,6 @@ Lyre prototype 1 */ #define HAVE_PICTUREFLOW_INTEGRATION #endif -/* Add one HAVE_ define for all mas35xx targets */ -#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3507D) || (CONFIG_CODEC == MAS3539F) -#define HAVE_MAS35XX -#endif - #if (CONFIG_CODEC == SWCODEC) #ifdef BOOTLOADER @@ -1012,7 +978,7 @@ Lyre prototype 1 */ #endif /* (CONFIG_CODEC == SWCODEC) */ /* Determine if accesses should be strictly long aligned. */ -#if (CONFIG_CPU == SH7034) || defined(CPU_ARM) || defined(CPU_MIPS) +#if defined(CPU_ARM) || defined(CPU_MIPS) #define ROCKBOX_STRICT_ALIGN 1 #endif @@ -1061,8 +1027,7 @@ Lyre prototype 1 */ /* IRAM usage */ #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && /* Not for hosted environments */ \ - (((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \ - defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ + (defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ (CONFIG_CPU == AS3525 && MEMORYSIZE > 2 && !defined(BOOTLOADER)) || /* AS3525 +2MB: core, plugins, codecs */ \ (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC) && !defined(BOOTLOADER)) || /* AS3525 2MB: core only */ \ @@ -1077,7 +1042,7 @@ Lyre prototype 1 */ #define IDATA_ATTR __attribute__ ((section(".idata"))) #define IBSS_ATTR __attribute__ ((section(".ibss"))) #define USE_IRAM -#if CONFIG_CPU != SH7034 && (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) \ +#if (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) \ && CONFIG_CPU != JZ4732 && CONFIG_CPU != JZ4760B && CONFIG_CPU != AS3525v2 && CONFIG_CPU != IMX233 #define PLUGIN_USE_IRAM #endif @@ -1283,8 +1248,7 @@ Lyre prototype 1 */ #define HAVE_PCM_FULL_DUPLEX #endif -#if (CONFIG_CODEC == SWCODEC) || (CONFIG_CODEC == MAS3587F) || \ - (CONFIG_CODEC == MAS3539F) +#if (CONFIG_CODEC == SWCODEC) #define HAVE_PITCHCONTROL #endif diff --git a/firmware/export/config/archosfmrecorder.h b/firmware/export/config/archosfmrecorder.h deleted file mode 100644 index 0c64d70be4..0000000000 --- a/firmware/export/config/archosfmrecorder.h +++ /dev/null @@ -1,147 +0,0 @@ -/* define this if you use an ATA controller */ -#define CONFIG_STORAGE STORAGE_ATA - -#define MODEL_NAME "Archos FM Recorder" - -/* define this if you have recording possibility */ -#define HAVE_RECORDING - -/* Define bitmask of input sources - recordable bitmask can be defined - explicitly if different */ -#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) - -/* define this if you have a bitmap LCD display */ -#define HAVE_LCD_BITMAP - -/* define this if you can flip your LCD */ -#define HAVE_LCD_FLIP - -/* define this if you can invert the colours on your LCD */ -#define HAVE_LCD_INVERT - -/* define this if you have access to the quickscreen */ -#define HAVE_QUICKSCREEN - -/* define this if you have the button bar */ -#define HAVE_BUTTONBAR - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -/* LCD dimensions */ -#define LCD_WIDTH 112 -#define LCD_HEIGHT 64 -/* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ -#define LCD_DPI 85 -#define LCD_DEPTH 1 - -#define LCD_PIXEL_ASPECT_WIDTH 4 -#define LCD_PIXEL_ASPECT_HEIGHT 5 - -#define LCD_PIXELFORMAT VERTICAL_PACKING - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x7ee57e - -/* define this if you have a Recorder style 10-key keyboard */ -#define CONFIG_KEYPAD RECORDER_PAD - -/* Define this to enable morse code input */ -#define HAVE_MORSE_INPUT - -/* define this if you have a real-time clock */ -#define CONFIG_RTC RTC_M41ST84W - -/* FM recorders can wake up from RTC alarm */ -#define HAVE_RTC_ALARM - -/* define this if you have RTC RAM available for settings */ -#define HAVE_RTC_RAM - -/* Define this if you have a software controlled poweroff */ -#define HAVE_SW_POWEROFF - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -#ifndef BOOTLOADER -/* Define this if you have an FM Radio */ -#define CONFIG_TUNER S1A0903X01 -#endif - -#define AB_REPEAT_ENABLE - -/* Define this if you have a MAS3587F */ -#define CONFIG_CODEC MAS3587F - -/* Define this for LCD backlight available */ -#define HAVE_BACKLIGHT - -/* define this if you have a disk storage, i.e. something - that needs spinups and can cause skips when shaked */ -#define HAVE_DISK_STORAGE - -#define CONFIG_I2C I2C_PLAYREC - -#define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 1 /* only one type */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -#define CURRENT_NORMAL 145 /* usual current in mA */ -#define CURRENT_RECORD 35 /* additional recording current */ -#define CURRENT_USB 500 /* usual current in mA in USB mode */ - -/* Hardware controlled charging with monitoring */ -#define CONFIG_CHARGING CHARGING_MONITOR - -/* define this if the unit can be powered or charged via USB */ -#define HAVE_USB_POWER - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this if you have a FM Recorder key system */ -#define HAVE_FMADC - -/* Define this if battery voltage can only be measured with ATA powered */ -#define NEED_ATA_POWER_BATT_MEASURE - -/* Define this to the CPU frequency */ -#define CPU_FREQ 11059200 - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 20 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 6 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 24 - -/* The start address index for ROM builds */ -/* #define ROM_START 0x14010 for behind original Archos */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Software controlled LED */ -#define CONFIG_LED LED_REAL - -#define CONFIG_LCD LCD_SSD1815 - -#define BOOTFILE_EXT "ajz" -#define BOOTFILE "ajbrec." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 63 - -/* Define this if a programmable hotkey is mapped */ -#define HAVE_HOTKEY diff --git a/firmware/export/config/archosondiofm.h b/firmware/export/config/archosondiofm.h deleted file mode 100644 index 68ecc217c1..0000000000 --- a/firmware/export/config/archosondiofm.h +++ /dev/null @@ -1,147 +0,0 @@ -/* define this if you have recording possibility */ -#define HAVE_RECORDING - -#define MODEL_NAME "Ondio FM" - -#define ONDIO_SERIES - -/* Define bitmask of input sources - recordable bitmask can be defined - explicitly if different */ -#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN) - -/* define this if you have a bitmap LCD display */ -#define HAVE_LCD_BITMAP - -/* define this if you can flip your LCD */ -#define HAVE_LCD_FLIP - -/* define this if you can invert the colours on your LCD */ -#define HAVE_LCD_INVERT - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -/* LCD dimensions */ -#define LCD_WIDTH 112 -#define LCD_HEIGHT 64 -/* sqrt(112^2 + 64^2) / 1.5 = 83.8 */ -#define LCD_DPI 84 -#define LCD_DEPTH 1 - -#define LCD_PIXEL_ASPECT_WIDTH 4 -#define LCD_PIXEL_ASPECT_HEIGHT 5 - -#define LCD_PIXELFORMAT VERTICAL_PACKING - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x82b4fa - -/* define this if you have an Ondio style 6-key keyboard */ -#define CONFIG_KEYPAD ONDIO_PAD - -/* Define this to enable morse code input */ -#define HAVE_MORSE_INPUT - -#define AB_REPEAT_ENABLE -#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE - -/* Define this if you have a software controlled poweroff */ -#define HAVE_SW_POWEROFF - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -#ifndef BOOTLOADER -/* Define this if you have an FM Radio */ -#define CONFIG_TUNER (S1A0903X01 | TEA5767) /* to be decided at runtime */ -#define CONFIG_TUNER_XTAL 13000000 -#endif - -/* Define this if you have a MAS3587F */ -#define CONFIG_CODEC MAS3587F - -/* define this if you have a flash memory storage */ -#define HAVE_FLASH_STORAGE - -#define BATTERY_CAPACITY_DEFAULT 1000 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 1500 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 2 /* Alkalines or NiMH */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -/* define this if the unit should not shut down on low battery. */ -#define NO_LOW_BATTERY_SHUTDOWN - -/* define this if the unit can be powered or charged via USB */ -#define HAVE_USB_POWER - -/* define current usage levels */ -#define CURRENT_NORMAL 95 /* average, nearly proportional to 1/U */ -#define CURRENT_USB 1 /* host powered in USB mode; avoid zero-div */ -#define CURRENT_BACKLIGHT 0 /* no backlight */ - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this to the CPU frequency */ -#define CPU_FREQ 12000000 - -/* Define this for different I2C pinout */ -#define CONFIG_I2C I2C_ONDIO - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 20 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 6 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 24 - -/* Define this if the tuner is switched on by software */ -#define HAVE_TUNER_PWR_CTRL - -/* The start address index for ROM builds */ -/* #define ROM_START 0x16010 for behind original Archos */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Define this if the display is mounted upside down */ -#define HAVE_DISPLAY_FLIPPED - -/* Define this for different ADC channel assignment */ -#define HAVE_ONDIO_ADC - -/* Define this for MMC support instead of ATA harddisk */ -#define CONFIG_STORAGE STORAGE_MMC - -/* Define this to support mounting FAT16 partitions */ -#define HAVE_FAT16SUPPORT - -/* Define this if the MAS SIBI line can be controlled via PB8 */ -#define HAVE_MAS_SIBI_CONTROL - -/* define this if more than one device/partition can be used */ -#define HAVE_MULTIDRIVE -#define NUM_DRIVES 2 - -/* define this if media can be exchanged on the fly */ -#define HAVE_HOTSWAP - -#define CONFIG_LCD LCD_SSD1815 - -#define BOOTFILE_EXT "ajz" -#define BOOTFILE "ajbrec." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 63 - -/* Define this if a programmable hotkey is mapped */ -//#define HAVE_HOTKEY diff --git a/firmware/export/config/archosondiosp.h b/firmware/export/config/archosondiosp.h deleted file mode 100644 index 3e9de1eda6..0000000000 --- a/firmware/export/config/archosondiosp.h +++ /dev/null @@ -1,131 +0,0 @@ -/* define this if you have a bitmap LCD display */ -#define HAVE_LCD_BITMAP - -#define MODEL_NAME "Ondio SP" - -#define ONDIO_SERIES - -/* define this if you can flip your LCD */ -#define HAVE_LCD_FLIP - -/* define this if you can invert the colours on your LCD */ -#define HAVE_LCD_INVERT - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -/* LCD dimensions */ -#define LCD_WIDTH 112 -#define LCD_HEIGHT 64 -/* sqrt(112^2 + 64^2) / 1.5 = 83.8 */ -#define LCD_DPI 84 -#define LCD_DEPTH 1 - -#define LCD_PIXEL_ASPECT_WIDTH 4 -#define LCD_PIXEL_ASPECT_HEIGHT 5 - -#define LCD_PIXELFORMAT VERTICAL_PACKING - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x82b4fa - -/* define this if you have an Ondio style 6-key keyboard */ -#define CONFIG_KEYPAD ONDIO_PAD - -/* Define this to enable morse code input */ -#define HAVE_MORSE_INPUT - -#define AB_REPEAT_ENABLE -#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE - -/* Define this if you have a software controlled poweroff */ -#define HAVE_SW_POWEROFF - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -/* Define this if you have a MAS3539F */ -#define CONFIG_CODEC MAS3539F - -/* define this if you have a flash memory storage */ -#define HAVE_FLASH_STORAGE - -#define BATTERY_CAPACITY_DEFAULT 1000 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 1500 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 2 /* Alkalines or NiMH */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -/* define this if the unit should not shut down on low battery. */ -#define NO_LOW_BATTERY_SHUTDOWN - -/* define this if the unit can be powered or charged via USB */ -#define HAVE_USB_POWER - -/* define current usage levels */ -#define CURRENT_NORMAL 95 /* average, nearly proportional to 1/U */ -#define CURRENT_USB 1 /* host powered in USB mode; avoid zero-div */ -#define CURRENT_BACKLIGHT 0 /* no backlight */ - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this to the CPU frequency */ -#define CPU_FREQ 12000000 - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 20 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 6 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 24 - -/* The start address index for ROM builds */ -/* #define ROM_START 0x12010 for behind original Archos */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Define this if the display is mounted upside down */ -#define HAVE_DISPLAY_FLIPPED - -/* Define this for different I2C pinout */ -#define CONFIG_I2C I2C_ONDIO - -/* Define this for different ADC channel assignment */ -#define HAVE_ONDIO_ADC - -/* Define this for MMC support instead of ATA harddisk */ -#define CONFIG_STORAGE STORAGE_MMC - -/* Define this to support mounting FAT16 partitions */ -#define HAVE_FAT16SUPPORT - -/* Define this if the MAS SIBI line can be controlled via PB8 */ -#define HAVE_MAS_SIBI_CONTROL - -/* define this if more than one device/partition can be used */ -#define HAVE_MULTIDRIVE -#define NUM_DRIVES 2 - -/* define this if media can be exchanged on the fly */ -#define HAVE_HOTSWAP - -#define CONFIG_LCD LCD_SSD1815 - -#define BOOTFILE_EXT "ajz" -#define BOOTFILE "ajbrec." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 63 - -/* Define this if a programmable hotkey is mapped */ -//#define HAVE_HOTKEY diff --git a/firmware/export/config/archosplayer.h b/firmware/export/config/archosplayer.h deleted file mode 100644 index 2e0219cff5..0000000000 --- a/firmware/export/config/archosplayer.h +++ /dev/null @@ -1,111 +0,0 @@ -/* define this if you use an ATA controller */ -#define CONFIG_STORAGE STORAGE_ATA - -#define MODEL_NAME "Archos Player/Studio" - -/* define this if you have a charcell LCD display */ -#define HAVE_LCD_CHARCELLS - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -#define LCD_WIDTH 11 -#define LCD_HEIGHT 2 -/* sqrt(11^2 + 2^2) / 1.5 = 7.5 */ -#define LCD_DPI 7 -#define LCD_DEPTH 1 -#define SIM_LCD_WIDTH 132 /* pixels */ -#define SIM_LCD_HEIGHT 64 /* pixels */ - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x7ee57e - -/* define this if you have the Player's keyboard */ -#define CONFIG_KEYPAD PLAYER_PAD - -#define AB_REPEAT_ENABLE -#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -/* Define this if you have a MAS3507D */ -#define CONFIG_CODEC MAS3507D - -/* Define this if you have a DAC3550A */ -#define HAVE_DAC3550A - -/* define this if you have a disk storage, i.e. something - that needs spinups and can cause skips when shaked */ -#define HAVE_DISK_STORAGE - -/* Define this for LCD backlight available */ -#define HAVE_BACKLIGHT - -#define BATTERY_CAPACITY_DEFAULT 1500 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 1500 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 1 /* only one type */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -#define CURRENT_NORMAL 145 /* usual current in mA */ -#define CURRENT_USB 500 /* usual current in mA in USB mode */ - -/* define this if the unit should not shut down on low battery. */ -#define NO_LOW_BATTERY_SHUTDOWN - -/* Hardware controlled charging */ -#define CONFIG_CHARGING CHARGING_SIMPLE - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this if you control ata power player style - (with PB4, new player only) */ -#define ATA_POWER_PLAYERSTYLE - -/* Define this to the CPU frequency */ -#define CPU_FREQ 12000000 /* cycle time ~83.3ns */ - -/* Define this if you must discharge the data line by driving it low - and then set it to input to see if it stays low or goes high */ -#define HAVE_I2C_LOW_FIRST - -#define CONFIG_I2C I2C_PLAYREC - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 0 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 4 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 6 - -/* The start address index for ROM builds */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Software controlled LED */ -#define CONFIG_LED LED_REAL - -#define CONFIG_LCD LCD_SSD1801 - -#define BOOTFILE_EXT "mod" -#define BOOTFILE "archos." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 31 -#define DEFAULT_CONTRAST_SETTING 30 - -#define HAVE_SERIAL - -/* Define this if a programmable hotkey is mapped */ -#define HAVE_HOTKEY diff --git a/firmware/export/config/archosrecorder.h b/firmware/export/config/archosrecorder.h deleted file mode 100644 index 016ea8b944..0000000000 --- a/firmware/export/config/archosrecorder.h +++ /dev/null @@ -1,141 +0,0 @@ -/* define this if you use an ATA controller */ -#define CONFIG_STORAGE STORAGE_ATA - -#define MODEL_NAME "Archos Recorder" - -/* define this if you have recording possibility */ -#define HAVE_RECORDING - -/* Define bitmask of input sources - recordable bitmask can be defined - explicitly if different */ -#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) - -/* define this if you have a bitmap LCD display */ -#define HAVE_LCD_BITMAP - -/* define this if you can flip your LCD */ -//#define HAVE_LCD_FLIP - -/* define this if you can invert the colours on your LCD */ -#define HAVE_LCD_INVERT - -/* define this if you have access to the quickscreen */ -#define HAVE_QUICKSCREEN - -/* define this if you have the button bar */ -#define HAVE_BUTTONBAR - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -/* LCD dimensions */ -#define LCD_WIDTH 112 -#define LCD_HEIGHT 64 -/* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ -#define LCD_DPI 85 -#define LCD_DEPTH 1 - -#define LCD_PIXEL_ASPECT_WIDTH 4 -#define LCD_PIXEL_ASPECT_HEIGHT 5 - -#define LCD_PIXELFORMAT VERTICAL_PACKING - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x7ee57e - -/* define this if you have the Recorder's 10-key keyboard */ -#define CONFIG_KEYPAD RECORDER_PAD - -/* Define this to enable morse code input */ -//#define HAVE_MORSE_INPUT - -/* define this if you have a real-time clock */ -#define CONFIG_RTC RTC_M41ST84W - -/* define this if you have RTC RAM available for settings */ -#define HAVE_RTC_RAM - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -#define AB_REPEAT_ENABLE - -/* Define this if you have a MAS3587F */ -#define CONFIG_CODEC MAS3587F - -/* define this if you have a disk storage, i.e. something - that needs spinups and can cause skips when shaked */ -#define HAVE_DISK_STORAGE - -/* Define this for LCD backlight available */ -#define HAVE_BACKLIGHT - -#define CONFIG_I2C I2C_PLAYREC - -#define BATTERY_CAPACITY_DEFAULT 1500 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 1500 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 1 /* only one type */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -#if MEMORYSIZE < 8 - #define CURRENT_NORMAL 145 /* usual current in mA */ -#else - #define CURRENT_NORMAL 145 *100 / 122 /* assuming 192 kbps, the running time is 22% longer with 8MB */ -#endif -#define CURRENT_RECORD 35 /* additional recording current */ -#define CURRENT_USB 500 /* usual current in mA in USB mode */ - -/* define this if the unit should not shut down on low battery. */ -#define NO_LOW_BATTERY_SHUTDOWN - -/* Software controlled charging */ -#define CONFIG_CHARGING CHARGING_TARGET - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this if you have ATA power-off control */ -#define HAVE_ATA_POWER_OFF - -/* Define this to the CPU frequency */ -#define CPU_FREQ 11059200 - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 0 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 4 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 6 - -/* The start address index for ROM builds */ -/* #define ROM_START 0x11010 for behind original Archos */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Software controlled LED */ -#define CONFIG_LED LED_REAL - -/* Define this for S/PDIF output available */ -#define HAVE_SPDIF_OUT - -#define CONFIG_LCD LCD_SSD1815 - -#define BOOTFILE_EXT "ajz" -#define BOOTFILE "ajbrec." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 63 - -#define HAVE_SERIAL -/* Define this if a programmable hotkey is mapped */ -#define HAVE_HOTKEY diff --git a/firmware/export/config/archosrecorderv2.h b/firmware/export/config/archosrecorderv2.h deleted file mode 100644 index 4640eae247..0000000000 --- a/firmware/export/config/archosrecorderv2.h +++ /dev/null @@ -1,147 +0,0 @@ -/* define this if you use an ATA controller */ -#define CONFIG_STORAGE STORAGE_ATA - -#define MODEL_NAME "Archos Recorder v2" - -/* define this if you have recording possibility */ -#define HAVE_RECORDING - -/* Define bitmask of input sources - recordable bitmask can be defined - explicitly if different */ -#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_SPDIF) - -/* define this if you have a bitmap LCD display */ -#define HAVE_LCD_BITMAP - -/* define this if you can flip your LCD */ -#define HAVE_LCD_FLIP - -/* define this if you can invert the colours on your LCD */ -#define HAVE_LCD_INVERT - -/* define this if you have access to the quickscreen */ -#define HAVE_QUICKSCREEN - -/* define this if you have the button bar */ -#define HAVE_BUTTONBAR - -/* define this if you would like tagcache to build on this target */ -#define HAVE_TAGCACHE - -/* LCD dimensions */ -#define LCD_WIDTH 112 -#define LCD_HEIGHT 64 -/* sqrt(112^2 + 64^2) / 1.5 = 85.4 */ -#define LCD_DPI 85 -#define LCD_DEPTH 1 - -#define LCD_PIXEL_ASPECT_WIDTH 4 -#define LCD_PIXEL_ASPECT_HEIGHT 5 - -#define LCD_PIXELFORMAT VERTICAL_PACKING - -/* Display colours, for screenshots and sim (0xRRGGBB) */ -#define LCD_DARKCOLOR 0x000000 -#define LCD_BRIGHTCOLOR 0x5a915a -#define LCD_BL_DARKCOLOR 0x000000 -#define LCD_BL_BRIGHTCOLOR 0x7ee57e - -/* define this if you have a Recorder style 10-key keyboard */ -#define CONFIG_KEYPAD RECORDER_PAD - -/* Define this to enable morse code input */ -#define HAVE_MORSE_INPUT - -/* define this if you have a real-time clock */ -#define CONFIG_RTC RTC_M41ST84W - -/* FM recorders can wake up from RTC alarm */ -#define HAVE_RTC_ALARM - -/* define this if you have RTC RAM available for settings */ -#define HAVE_RTC_RAM - -/* Define this if you have a software controlled poweroff */ -#define HAVE_SW_POWEROFF - -/* The number of bytes reserved for loadable plugins */ -#define PLUGIN_BUFFER_SIZE 0x8000 - -#define AB_REPEAT_ENABLE - -/* Define this if you have a MAS3587F */ -#define CONFIG_CODEC MAS3587F - -/* define this if you have a disk storage, i.e. something - that needs spinups and can cause skips when shaked */ -#define HAVE_DISK_STORAGE - -/* Define this for LCD backlight available */ -#define HAVE_BACKLIGHT - -#define CONFIG_I2C I2C_PLAYREC - -#define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */ -#define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */ -#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */ -#define BATTERY_CAPACITY_INC 50 /* capacity increment */ -#define BATTERY_TYPES_COUNT 1 /* only one type */ - -#define CONFIG_BATTERY_MEASURE VOLTAGE_MEASURE - -#define CURRENT_NORMAL 145 /* usual current in mA */ -#define CURRENT_RECORD 35 /* additional recording current */ -#define CURRENT_USB 500 /* usual current in mA in USB mode */ - -/* Hardware controlled charging with monitoring */ -#define CONFIG_CHARGING CHARGING_MONITOR - -/* define this if the unit can be powered or charged via USB */ -#define HAVE_USB_POWER - -/* Define this if you have a SH7034 */ -#define CONFIG_CPU SH7034 - -/* Define this if you have a FM Recorder key system */ -#define HAVE_FMADC - -/* Define this if battery voltage can only be measured with ATA powered */ -#define NEED_ATA_POWER_BATT_MEASURE - -/* Define this to the CPU frequency */ -#define CPU_FREQ 11059200 - -/* Offset ( in the firmware file's header ) to the file length */ -#define FIRMWARE_OFFSET_FILE_LENGTH 20 - -/* Offset ( in the firmware file's header ) to the file CRC */ -#define FIRMWARE_OFFSET_FILE_CRC 6 - -/* Offset ( in the firmware file's header ) to the real data */ -#define FIRMWARE_OFFSET_FILE_DATA 24 - -#ifndef BOOTLOADER -/* Define this if you have an FM Radio */ -#define CONFIG_TUNER S1A0903X01 -#endif - -/* The start address index for ROM builds */ -/* #define ROM_START 0x12010 for behind original Archos */ -#define ROM_START 0x7010 /* for behind BootBox */ - -/* Software controlled LED */ -#define CONFIG_LED LED_REAL - -#define CONFIG_LCD LCD_SSD1815 - -#define BOOTFILE_EXT "ajz" -#define BOOTFILE "ajbrec." BOOTFILE_EXT -#define BOOTDIR "/" - -#define HAVE_LCD_CONTRAST - -#define MIN_CONTRAST_SETTING 5 -#define MAX_CONTRAST_SETTING 63 - -/* Define this if a programmable hotkey is mapped */ -#define HAVE_HOTKEY diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h index 201ffba656..aade199dd2 100644 --- a/firmware/export/cpu.h +++ b/firmware/export/cpu.h @@ -20,9 +20,6 @@ ****************************************************************************/ #include "config.h" -#if CONFIG_CPU == SH7034 -#include "sh7034.h" -#endif #if CONFIG_CPU == MCF5249 #include "mcf5249.h" #endif diff --git a/firmware/export/hwcompat.h b/firmware/export/hwcompat.h index c37add49f9..ea167a4adf 100644 --- a/firmware/export/hwcompat.h +++ b/firmware/export/hwcompat.h @@ -24,37 +24,6 @@ #include #include "config.h" -#if (CONFIG_CPU == SH7034) && (CONFIG_PLATFORM & PLATFORM_NATIVE) - -#define ROM_VERSION (*(short *)0x020000fe) - -/* Bit mask values for HW compatibility */ -#define ATA_ADDRESS_200 0x0100 -#define USB_ACTIVE_HIGH 0x0100 -#define PR_ACTIVE_HIGH 0x0100 -#define LCD_CONTRAST_BIAS 0x0200 -#define MMC_CLOCK_POLARITY 0x0400 -#define TUNER_MODEL 0x0800 - -#ifdef ARCHOS_PLAYER -#define HW_MASK 0 -#else /* Recorders, Ondios */ -#define HW_MASK (*(short *)0x020000fc) -#endif - -#ifdef CONFIG_TUNER_MULTI -static inline int tuner_detect_type(void) -{ - return (HW_MASK & TUNER_MODEL) ? TEA5767 : S1A0903X01; -} -#endif - -#endif /* (CONFIG_CPU == SH7034) && (CONFIG_PLATFORM & PLATFORM_NATIVE) */ - -#ifdef ARCHOS_PLAYER -bool is_new_player(void); -#endif - #ifdef IPOD_ARCH #ifdef IPOD_VIDEO #ifdef BOOTLOADER diff --git a/firmware/export/mas35xx.h b/firmware/export/mas35xx.h deleted file mode 100644 index 02691f3de2..0000000000 --- a/firmware/export/mas35xx.h +++ /dev/null @@ -1,292 +0,0 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Implementation of MAS35xx audiohw api driver. - * - * Copyright (C) 2007 by Christian Gmeiner - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -#ifndef _MAS35XX_H -#define _MAS35XX_H - -#include "config.h" -#include "mascodec.h" - -#define MAS_BANK_D0 0 -#define MAS_BANK_D1 1 - -/* registers common to all MAS35xx */ -#define MAS_REG_DCCF 0x8e -#define MAS_REG_MUTE 0xaa -#define MAS_REG_PIODATA 0xc8 -#define MAS_REG_StartUpConfig 0xe6 -#define MAS_REG_KPRESCALE 0xe7 - -#if CONFIG_CODEC == MAS3507D - -#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP) - -AUDIOHW_SETTING(VOLUME, "dB", 0, 1, -78, 18, -18) -AUDIOHW_SETTING(BASS, "dB", 0, 1, -15, 15, 7) -AUDIOHW_SETTING(TREBLE, "dB", 0, 1, -15, 15, 7) - -/* I2C defines */ -#define MAS_ADR 0x3a -#define MAS_DEV_WRITE (MAS_ADR | 0x00) -#define MAS_DEV_READ (MAS_ADR | 0x01) - -/* MAS3507D registers */ -#define MAS_DATA_WRITE 0x68 -#define MAS_DATA_READ 0x69 -#define MAS_CONTROL 0x6a - -#define MAS_REG_KBASS 0x6b -#define MAS_REG_KTREBLE 0x6f - -/* MAS3507D commands */ -#define MAS_CMD_READ_ANCILLARY 0x30 -#define MAS_CMD_WRITE_REG 0x90 -#define MAS_CMD_WRITE_D0_MEM 0xa0 -#define MAS_CMD_WRITE_D1_MEM 0xb0 -#define MAS_CMD_READ_REG 0xd0 -#define MAS_CMD_READ_D0_MEM 0xe0 -#define MAS_CMD_READ_D1_MEM 0xf0 - -/* MAS3507D D0 memmory cells */ -#define MAS_D0_MPEG_FRAME_COUNT 0x300 -#define MAS_D0_MPEG_STATUS_1 0x301 -#define MAS_D0_MPEG_STATUS_2 0x302 -#define MAS_D0_CRC_ERROR_COUNT 0x303 -#define MAS_D0_OUT_LL 0x7f8 -#define MAS_D0_OUT_LR 0x7f9 -#define MAS_D0_OUT_RL 0x7fa -#define MAS_D0_OUT_RR 0x7fb - -static const unsigned int bass_table[] = -{ - 0x9e400, /* -15dB */ - 0xa2800, /* -14dB */ - 0xa7400, /* -13dB */ - 0xac400, /* -12dB */ - 0xb1800, /* -11dB */ - 0xb7400, /* -10dB */ - 0xbd400, /* -9dB */ - 0xc3c00, /* -8dB */ - 0xca400, /* -7dB */ - 0xd1800, /* -6dB */ - 0xd8c00, /* -5dB */ - 0xe0400, /* -4dB */ - 0xe8000, /* -3dB */ - 0xefc00, /* -2dB */ - 0xf7c00, /* -1dB */ - 0, - 0x800, /* 1dB */ - 0x10000, /* 2dB */ - 0x17c00, /* 3dB */ - 0x1f800, /* 4dB */ - 0x27000, /* 5dB */ - 0x2e400, /* 6dB */ - 0x35800, /* 7dB */ - 0x3c000, /* 8dB */ - 0x42800, /* 9dB */ - 0x48800, /* 10dB */ - 0x4e400, /* 11dB */ - 0x53800, /* 12dB */ - 0x58800, /* 13dB */ - 0x5d400, /* 14dB */ - 0x61800 /* 15dB */ -}; - -static const unsigned int treble_table[] = -{ - 0xb2c00, /* -15dB */ - 0xbb400, /* -14dB */ - 0xc1800, /* -13dB */ - 0xc6c00, /* -12dB */ - 0xcbc00, /* -11dB */ - 0xd0400, /* -10dB */ - 0xd5000, /* -9dB */ - 0xd9800, /* -8dB */ - 0xde000, /* -7dB */ - 0xe2800, /* -6dB */ - 0xe7e00, /* -5dB */ - 0xec000, /* -4dB */ - 0xf0c00, /* -3dB */ - 0xf5c00, /* -2dB */ - 0xfac00, /* -1dB */ - 0, - 0x5400, /* 1dB */ - 0xac00, /* 2dB */ - 0x10400, /* 3dB */ - 0x16000, /* 4dB */ - 0x1c000, /* 5dB */ - 0x22400, /* 6dB */ - 0x28400, /* 7dB */ - 0x2ec00, /* 8dB */ - 0x35400, /* 9dB */ - 0x3c000, /* 10dB */ - 0x42c00, /* 11dB */ - 0x49c00, /* 12dB */ - 0x51800, /* 13dB */ - 0x58400, /* 14dB */ - 0x5f800 /* 15dB */ -}; - -static const unsigned int prescale_table[] = -{ - 0x80000, /* 0db */ - 0x8e000, /* 1dB */ - 0x9a400, /* 2dB */ - 0xa5800, /* 3dB */ - 0xaf400, /* 4dB */ - 0xb8000, /* 5dB */ - 0xbfc00, /* 6dB */ - 0xc6c00, /* 7dB */ - 0xcd000, /* 8dB */ - 0xd25c0, /* 9dB */ - 0xd7800, /* 10dB */ - 0xdc000, /* 11dB */ - 0xdfc00, /* 12dB */ - 0xe3400, /* 13dB */ - 0xe6800, /* 14dB */ - 0xe9400 /* 15dB */ -}; - -#else /* CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F */ - -AUDIOHW_SETTING(VOLUME, "dB", 0, 1,-100, 12, -25) -AUDIOHW_SETTING(BASS, "dB", 0, 1, -12, 12, 6) -AUDIOHW_SETTING(TREBLE, "dB", 0, 1, -12, 12, 6) -AUDIOHW_SETTING(LOUDNESS, "dB", 0, 1, 0, 17, 0) -AUDIOHW_SETTING(AVC, "", 0, 1, -1, 4, 0) -AUDIOHW_SETTING(MDB_STRENGTH, "dB", 0, 1, 0, 127, 48) -AUDIOHW_SETTING(MDB_HARMONICS, "%", 0, 1, 0, 100, 50) -AUDIOHW_SETTING(MDB_CENTER, "Hz", 0, 10, 20, 300, 60) -AUDIOHW_SETTING(MDB_SHAPE, "Hz", 0, 10, 50, 300, 90) -AUDIOHW_SETTING(MDB_ENABLE, "", 0, 1, 0, 1, 0) -AUDIOHW_SETTING(SUPERBASS, "", 0, 1, 0, 1, 0) - -#if CONFIG_CODEC == MAS3587F && defined(HAVE_RECORDING) -/* MAS3587F and MAS3539F handle clipping prevention internally so we do not - * need the prescaler -> CLIPPING_CAP */ -#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | BALANCE_CAP | CLIPPING_CAP | \ - MONO_VOL_CAP | LIN_GAIN_CAP | MIC_GAIN_CAP) -AUDIOHW_SETTING(LEFT_GAIN, "dB", 1, 1, 0, 15, 8, (val - 2) * 15) -AUDIOHW_SETTING(RIGHT_GAIN, "dB", 1, 1, 0, 15, 8, (val - 2) * 15) -AUDIOHW_SETTING(MIC_GAIN, "dB", 1, 1, 0, 15, 2, val * 15 + 210) -#else -/* MAS3587F and MAS3539F handle clipping prevention internally so we do not - * need the prescaler -> CLIPPING_CAP */ -#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | BALANCE_CAP | CLIPPING_CAP | \ - MONO_VOL_CAP) -#endif /* MAS3587F && HAVE_RECORDING */ - -/* I2C defines */ -#define MAS_ADR 0x3c -#define MAS_DEV_WRITE (MAS_ADR | 0x00) -#define MAS_DEV_READ (MAS_ADR | 0x01) - -/* MAS3587F/MAS3539F registers */ -#define MAS_DATA_WRITE 0x68 -#define MAS_DATA_READ 0x69 -#define MAS_CODEC_WRITE 0x6c -#define MAS_CODEC_READ 0x6d -#define MAS_CONTROL 0x6a -#define MAS_DCCF 0x76 -#define MAS_DCFR 0x77 - -#define MAS_REG_KMDB_SWITCH 0x21 -#define MAS_REG_KMDB_STR 0x22 -#define MAS_REG_KMDB_HAR 0x23 -#define MAS_REG_KMDB_FC 0x24 -#define MAS_REG_KLOUDNESS 0x1e -#define MAS_REG_QPEAK_L 0x0a -#define MAS_REG_QPEAK_R 0x0b -#define MAS_REG_DQPEAK_L 0x0c -#define MAS_REG_DQPEAK_R 0x0d -#define MAS_REG_VOLUME_CONTROL 0x10 -#define MAS_REG_BALANCE 0x11 -#define MAS_REG_KAVC 0x12 -#define MAS_REG_KBASS 0x14 -#define MAS_REG_KTREBLE 0x15 - -/* MAS3587F/MAS3539F commands */ -#define MAS_CMD_READ_ANCILLARY 0x50 -#define MAS_CMD_FAST_PRG_DL 0x60 -#define MAS_CMD_READ_IC_VER 0x70 -#define MAS_CMD_READ_REG 0xa0 -#define MAS_CMD_WRITE_REG 0xb0 -#define MAS_CMD_READ_D0_MEM 0xc0 -#define MAS_CMD_READ_D1_MEM 0xd0 -#define MAS_CMD_WRITE_D0_MEM 0xe0 -#define MAS_CMD_WRITE_D1_MEM 0xf0 - -/* MAS3587F D0 memory cells */ -#if CONFIG_CODEC == MAS3587F -#define MAS_D0_APP_SELECT 0x7f6 -#define MAS_D0_APP_RUNNING 0x7f7 -#define MAS_D0_ENCODER_CONTROL 0x7f0 -#define MAS_D0_IO_CONTROL_MAIN 0x7f1 -#define MAS_D0_INTERFACE_CONTROL 0x7f2 -#define MAS_D0_OFREQ_CONTROL 0x7f3 -#define MAS_D0_OUT_CLK_CONFIG 0x7f4 -#define MAS_D0_SPD_OUT_BITS 0x7f8 -#define MAS_D0_SOFT_MUTE 0x7f9 -#define MAS_D0_OUT_LL 0x7fc -#define MAS_D0_OUT_LR 0x7fd -#define MAS_D0_OUT_RL 0x7fe -#define MAS_D0_OUT_RR 0x7ff -#define MAS_D0_MPEG_FRAME_COUNT 0xfd0 -#define MAS_D0_MPEG_STATUS_1 0xfd1 -#define MAS_D0_MPEG_STATUS_2 0xfd2 -#define MAS_D0_CRC_ERROR_COUNT 0xfd3 - -/* MAS3539F D0 memory cells */ -#elif CONFIG_CODEC == MAS3539F -#define MAS_D0_APP_SELECT 0x34b -#define MAS_D0_APP_RUNNING 0x34c -/* no encoder :( */ -#define MAS_D0_IO_CONTROL_MAIN 0x346 -#define MAS_D0_INTERFACE_CONTROL 0x347 -#define MAS_D0_OFREQ_CONTROL 0x348 -#define MAS_D0_OUT_CLK_CONFIG 0x349 -#define MAS_D0_SPD_OUT_BITS 0x351 -#define MAS_D0_SOFT_MUTE 0x350 -#define MAS_D0_OUT_LL 0x354 -#define MAS_D0_OUT_LR 0x355 -#define MAS_D0_OUT_RL 0x356 -#define MAS_D0_OUT_RR 0x357 -#define MAS_D0_MPEG_FRAME_COUNT 0xfd0 -#define MAS_D0_MPEG_STATUS_1 0xfd1 -#define MAS_D0_MPEG_STATUS_2 0xfd2 -#define MAS_D0_CRC_ERROR_COUNT 0xfd3 -#endif - -/* Function prototypes */ -extern void audiohw_set_loudness(int value); -extern void audiohw_set_avc(int value); -extern void audiohw_set_mdb_strength(int value); -extern void audiohw_set_mdb_harmonics(int value); -extern void audiohw_set_mdb_center(int value); -extern void audiohw_set_mdb_shape(int value); -extern void audiohw_set_mdb_enable(int value); -extern void audiohw_set_superbass(int value); - -#endif /* CONFIG_CODEC */ - -#endif /* _MAS35XX_H */ diff --git a/firmware/export/mascodec.h b/firmware/export/mascodec.h deleted file mode 100644 index 00690ae7dd..0000000000 --- a/firmware/export/mascodec.h +++ /dev/null @@ -1,45 +0,0 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2002 by Linus Nielsen Feltzing - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ -#ifndef _MASCODEC_H_ -#define _MASCODEC_H_ - -/* unused: int mas_default_read(unsigned short *buf); */ -#if CONFIG_CODEC == MAS3507D -int mas_run(unsigned short address); -#endif -int mas_readmem(int bank, int addr, unsigned long* dest, int len); -int mas_writemem(int bank, int addr, const unsigned long* src, int len); -int mas_readreg(int reg); -int mas_writereg(int reg, unsigned int val); -void mas_reset(void); -/* unused: int mas_direct_config_read(unsigned char reg); */ -int mas_direct_config_write(unsigned char reg, unsigned int val); -int mas_codec_writereg(int reg, unsigned int val); -int mas_codec_readreg(int reg); -unsigned long mas_readver(void); - -#endif - -#if CONFIG_TUNER & S1A0903X01 -void mas_store_pllfreq(int freq); -int mas_get_pllfreq(void); -#endif - diff --git a/firmware/export/mp3_playback.h b/firmware/export/mp3_playback.h index 7434021611..51efb45651 100644 --- a/firmware/export/mp3_playback.h +++ b/firmware/export/mp3_playback.h @@ -39,15 +39,6 @@ void mp3_init(int volume, int bass, int treble, int balance, int loudness, int mdb_center, int mdb_shape, bool mdb_enable, bool superbass); -/* exported just for mpeg.c, to keep the recording there */ -#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) -void demand_irq_enable(bool on); -#endif - -/* new functions, exported to plugin API */ -#if CONFIG_CODEC == MAS3587F -void mp3_play_init(void); -#endif void mp3_play_data(const void* start, size_t size, mp3_play_callback_t get_more); void mp3_play_pause(bool play); diff --git a/firmware/export/rtc.h b/firmware/export/rtc.h index 216de87dea..a668c9c729 100644 --- a/firmware/export/rtc.h +++ b/firmware/export/rtc.h @@ -38,16 +38,6 @@ void rtc_init(void); int rtc_read_datetime(struct tm *tm); int rtc_write_datetime(const struct tm *tm); -#if CONFIG_RTC == RTC_M41ST84W - -/* The RTC in the Archos devices is used for much more than just the clock - data */ -int rtc_read(unsigned char address); -int rtc_read_multiple(unsigned char address, unsigned char *buf, int numbytes); -int rtc_write(unsigned char address, unsigned char value); - -#endif /* RTC_M41ST84W */ - #ifdef HAVE_RTC_ALARM void rtc_set_alarm(int h, int m); void rtc_get_alarm(int *h, int *m); diff --git a/firmware/export/s1a0903x01.h b/firmware/export/s1a0903x01.h deleted file mode 100644 index d9f1a11baf..0000000000 --- a/firmware/export/s1a0903x01.h +++ /dev/null @@ -1,42 +0,0 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * Tuner header for the Samsung S1A0903X01 - * - * Copyright (C) 2007 Michael Sevakis - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -#ifndef _S1A0903X01_H_ -#define _S1A0903X01_H_ - -/* Define additional tuner messages here */ -#define HAVE_RADIO_MUTE_TIMEOUT - -#if 0 -#define S1A0903X01_IF_MEASUREMENT (RADIO_SET_CHIP_FIRST+0) -#define S1A0903X01_SENSITIVITY (RADIO_SET_CHIP_FIRST+1) -#endif - -int s1a0903x01_set(int setting, int value); -int s1a0903x01_get(int setting); - -#ifndef CONFIG_TUNER_MULTI -#define tuner_get s1a0903x01_get -#define tuner_set s1a0903x01_set -#endif - -#endif /* _S1A0903X01_H_ */ diff --git a/firmware/export/sh7034.h b/firmware/export/sh7034.h deleted file mode 100644 index 2695acbc00..0000000000 --- a/firmware/export/sh7034.h +++ /dev/null @@ -1,376 +0,0 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2002 by Alan Korr - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -#ifndef __SH7034_H__ -#define __SH7034_H__ - -#define GBR 0x00000000 - -/* register address macros: */ - -#define SMR0_ADDR 0x05FFFEC0 -#define BRR0_ADDR 0x05FFFEC1 -#define SCR0_ADDR 0x05FFFEC2 -#define TDR0_ADDR 0x05FFFEC3 -#define SSR0_ADDR 0x05FFFEC4 -#define RDR0_ADDR 0x05FFFEC5 -#define SMR1_ADDR 0x05FFFEC8 -#define BRR1_ADDR 0x05FFFEC9 -#define SCR1_ADDR 0x05FFFECA -#define TDR1_ADDR 0x05FFFECB -#define SSR1_ADDR 0x05FFFECC -#define RDR1_ADDR 0x05FFFECD - -#define ADDRAH_ADDR 0x05FFFEE0 -#define ADDRAL_ADDR 0x05FFFEE1 -#define ADDRBH_ADDR 0x05FFFEE2 -#define ADDRBL_ADDR 0x05FFFEE3 -#define ADDRCH_ADDR 0x05FFFEE4 -#define ADDRCL_ADDR 0x05FFFEE5 -#define ADDRDH_ADDR 0x05FFFEE6 -#define ADDRDL_ADDR 0x05FFFEE7 -#define ADCSR_ADDR 0x05FFFEE8 -#define ADCR_ADDR 0x05FFFEE9 - -#define TSTR_ADDR 0x05FFFF00 -#define TSNC_ADDR 0x05FFFF01 -#define TMDR_ADDR 0x05FFFF02 -#define TFCR_ADDR 0x05FFFF03 -#define TCR0_ADDR 0x05FFFF04 -#define TIOR0_ADDR 0x05FFFF05 -#define TIER0_ADDR 0x05FFFF06 -#define TSR0_ADDR 0x05FFFF07 -#define TCNT0_ADDR 0x05FFFF08 -#define GRA0_ADDR 0x05FFFF0A -#define GRB0_ADDR 0x05FFFF0C -#define TCR1_ADDR 0x05FFFF0E -#define TIOR1_ADDR 0x05FFFF0F -#define TIER1_ADDR 0x05FFFF10 -#define TSR1_ADDR 0x05FFFF11 -#define TCNT1_ADDR 0x05FFFF12 -#define GRA1_ADDR 0x05FFFF14 -#define GRB1_ADDR 0x05FFFF16 -#define TCR2_ADDR 0x05FFFF18 -#define TIOR2_ADDR 0x05FFFF19 -#define TIER2_ADDR 0x05FFFF1A -#define TSR2_ADDR 0x05FFFF1B -#define TCNT2_ADDR 0x05FFFF1C -#define GRA2_ADDR 0x05FFFF1E -#define GRB2_ADDR 0x05FFFF20 -#define TCR3_ADDR 0x05FFFF22 -#define TIOR3_ADDR 0x05FFFF23 -#define TIER3_ADDR 0x05FFFF24 -#define TSR3_ADDR 0x05FFFF25 -#define TCNT3_ADDR 0x05FFFF26 -#define GRA3_ADDR 0x05FFFF28 -#define GRB3_ADDR 0x05FFFF2A -#define BRA3_ADDR 0x05FFFF2C -#define BRB3_ADDR 0x05FFFF2E -#define TOCR_ADDR 0x05FFFF31 -#define TCR4_ADDR 0x05FFFF32 -#define TIOR4_ADDR 0x05FFFF33 -#define TIER4_ADDR 0x05FFFF34 -#define TSR4_ADDR 0x05FFFF35 -#define TCNT4_ADDR 0x05FFFF36 -#define GRA4_ADDR 0x05FFFF38 -#define GRB4_ADDR 0x05FFFF3A -#define BRA4_ADDR 0x05FFFF3C -#define BRB4_ADDR 0x05FFFF3E - -#define SAR0_ADDR 0x05FFFF40 -#define DAR0_ADDR 0x05FFFF44 -#define DMAOR_ADDR 0x05FFFF48 -#define DTCR0_ADDR 0x05FFFF4A -#define CHCR0_ADDR 0x05FFFF4E -#define SAR1_ADDR 0x05FFFF50 -#define DAR1_ADDR 0x05FFFF54 -#define DTCR1_ADDR 0x05FFFF5A -#define CHCR1_ADDR 0x05FFFF5E -#define SAR2_ADDR 0x05FFFF60 -#define DAR2_ADDR 0x05FFFF64 -#define DTCR2_ADDR 0x05FFFF6A -#define CHCR2_ADDR 0x05FFFF6E -#define SAR3_ADDR 0x05FFFF70 -#define DAR3_ADDR 0x05FFFF74 -#define DTCR3_ADDR 0x05FFFF7A -#define CHCR3_ADDR 0x05FFFF7E - -#define IPRA_ADDR 0x05FFFF84 -#define IPRB_ADDR 0x05FFFF86 -#define IPRC_ADDR 0x05FFFF88 -#define IPRD_ADDR 0x05FFFF8A -#define IPRE_ADDR 0x05FFFF8C -#define ICR_ADDR 0x05FFFF8E - -#define BARH_ADDR 0x05FFFF90 -#define BARL_ADDR 0x05FFFF92 -#define BAMRH_ADDR 0x05FFFF94 -#define BAMRL_ADDR 0x05FFFF96 -#define BBR_ADDR 0x05FFFF98 - -#define BCR_ADDR 0x05FFFFA0 -#define WCR1_ADDR 0x05FFFFA2 -#define WCR2_ADDR 0x05FFFFA4 -#define WCR3_ADDR 0x05FFFFA6 -#define DCR_ADDR 0x05FFFFA8 -#define PCR_ADDR 0x05FFFFAA -#define RCR_ADDR 0x05FFFFAC -#define RTCSR_ADDR 0x05FFFFAE -#define RTCNT_ADDR 0x05FFFFB0 -#define RTCOR_ADDR 0x05FFFFB2 - -#define TCSR_ADDR 0x05FFFFB8 -#define TCNT_ADDR 0x05FFFFB9 -#define RSTCSR_ADDR 0x05FFFFBB - -#define SBYCR_ADDR 0x05FFFFBC - -#define PADR_ADDR 0x05FFFFC0 -#define PBDR_ADDR 0x05FFFFC2 -#define PAIOR_ADDR 0x05FFFFC4 -#define PBIOR_ADDR 0x05FFFFC6 -#define PACR1_ADDR 0x05FFFFC8 -#define PACR2_ADDR 0x05FFFFCA -#define PBCR1_ADDR 0x05FFFFCC -#define PBCR2_ADDR 0x05FFFFCE -#define PCDR_ADDR 0x05FFFFD0 - -#define CASCR_ADDR 0x05FFFFEE - -/* byte halves of the ports */ -#define PADRH_ADDR 0x05FFFFC0 -#define PADRL_ADDR 0x05FFFFC1 -#define PBDRH_ADDR 0x05FFFFC2 -#define PBDRL_ADDR 0x05FFFFC3 -#define PAIORH_ADDR 0x05FFFFC4 -#define PAIORL_ADDR 0x05FFFFC5 -#define PBIORH_ADDR 0x05FFFFC6 -#define PBIORL_ADDR 0x05FFFFC7 - - -/* A/D control/status register bits */ -#define ADCSR_CH 0x07 /* Channel/group select */ -#define ADCSR_CKS 0x08 /* Clock select */ -#define ADCSR_SCAN 0x10 /* Scan mode */ -#define ADCSR_ADST 0x20 /* A/D start */ -#define ADCSR_ADIE 0x40 /* A/D interrupt enable */ -#define ADCSR_ADF 0x80 /* A/D end flag */ - -/* A/D control register bits */ -#define ADCR_TRGE 0x80 /* Trigger enable */ - -/* register macros for direct access: */ - -#define SMR0 (*((volatile unsigned char*)SMR0_ADDR)) -#define BRR0 (*((volatile unsigned char*)BRR0_ADDR)) -#define SCR0 (*((volatile unsigned char*)SCR0_ADDR)) -#define TDR0 (*((volatile unsigned char*)TDR0_ADDR)) -#define SSR0 (*((volatile unsigned char*)SSR0_ADDR)) -#define RDR0 (*((volatile unsigned char*)RDR0_ADDR)) -#define SMR1 (*((volatile unsigned char*)SMR1_ADDR)) -#define BRR1 (*((volatile unsigned char*)BRR1_ADDR)) -#define SCR1 (*((volatile unsigned char*)SCR1_ADDR)) -#define TDR1 (*((volatile unsigned char*)TDR1_ADDR)) -#define SSR1 (*((volatile unsigned char*)SSR1_ADDR)) -#define RDR1 (*((volatile unsigned char*)RDR1_ADDR)) - -#define ADDRA (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */ -#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR)) -#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR)) -#define ADDRB (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */ -#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR)) -#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR)) -#define ADDRC (*((volatile unsigned short*)ADDRCH_ADDR)) /* combined */ -#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR)) -#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR)) -#define ADDRD (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */ -#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR)) -#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR)) -#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR)) -#define ADCR (*((volatile unsigned char*)ADCR_ADDR)) - -#define TSTR (*((volatile unsigned char*)TSTR_ADDR)) -#define TSNC (*((volatile unsigned char*)TSNC_ADDR)) -#define TMDR (*((volatile unsigned char*)TMDR_ADDR)) -#define TFCR (*((volatile unsigned char*)TFCR_ADDR)) -#define TCR0 (*((volatile unsigned char*)TCR0_ADDR)) -#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR)) -#define TIER0 (*((volatile unsigned char*)TIER0_ADDR)) -#define TSR0 (*((volatile unsigned char*)TSR0_ADDR)) -#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR)) -#define GRA0 (*((volatile unsigned short*)GRA0_ADDR)) -#define GRB0 (*((volatile unsigned short*)GRB0_ADDR)) -#define TCR1 (*((volatile unsigned char*)TCR1_ADDR)) -#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR)) -#define TIER1 (*((volatile unsigned char*)TIER1_ADDR)) -#define TSR1 (*((volatile unsigned char*)TSR1_ADDR)) -#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR)) -#define GRA1 (*((volatile unsigned short*)GRA1_ADDR)) -#define GRB1 (*((volatile unsigned short*)GRB1_ADDR)) -#define TCR2 (*((volatile unsigned char*)TCR2_ADDR)) -#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR)) -#define TIER2 (*((volatile unsigned char*)TIER2_ADDR)) -#define TSR2 (*((volatile unsigned char*)TSR2_ADDR)) -#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR)) -#define GRA2 (*((volatile unsigned short*)GRA2_ADDR)) -#define GRB2 (*((volatile unsigned short*)GRB2_ADDR)) -#define TCR3 (*((volatile unsigned char*)TCR3_ADDR)) -#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR)) -#define TIER3 (*((volatile unsigned char*)TIER3_ADDR)) -#define TSR3 (*((volatile unsigned char*)TSR3_ADDR)) -#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR)) -#define GRA3 (*((volatile unsigned short*)GRA3_ADDR)) -#define GRB3 (*((volatile unsigned short*)GRB3_ADDR)) -#define BRA3 (*((volatile unsigned short*)BRA3_ADDR)) -#define BRB3 (*((volatile unsigned short*)BRB3_ADDR)) -#define TOCR (*((volatile unsigned char*)TOCR_ADDR)) -#define TCR4 (*((volatile unsigned char*)TCR4_ADDR)) -#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR)) -#define TIER4 (*((volatile unsigned char*)TIER4_ADDR)) -#define TSR4 (*((volatile unsigned char*)TSR4_ADDR)) -#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR)) -#define GRA4 (*((volatile unsigned short*)GRA4_ADDR)) -#define GRB4 (*((volatile unsigned short*)GRB4_ADDR)) -#define BRA4 (*((volatile unsigned short*)BRA4_ADDR)) -#define BRB4 (*((volatile unsigned short*)BRB4_ADDR)) - -#define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) -#define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) -#define DMAOR (*((volatile unsigned short*)DMAOR_ADDR)) -#define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR)) -#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) -#define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) -#define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) -#define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR)) -#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) -#define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) -#define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) -#define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR)) -#define CHCR2 (*((volatile unsigned short*)CHCR2_ADDR)) -#define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) -#define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) -#define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR)) -#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) - -#define IPRA (*((volatile unsigned short*)IPRA_ADDR)) -#define IPRB (*((volatile unsigned short*)IPRB_ADDR)) -#define IPRC (*((volatile unsigned short*)IPRC_ADDR)) -#define IPRD (*((volatile unsigned short*)IPRD_ADDR)) -#define IPRE (*((volatile unsigned short*)IPRE_ADDR)) -#define ICR (*((volatile unsigned short*)ICR_ADDR)) - -#define BAR (*((volatile unsigned long*)BARH_ADDR)) /* combined */ -#define BARH (*((volatile unsigned short*)BARH_ADDR)) -#define BARL (*((volatile unsigned short*)BARL_ADDR)) -#define BAMR (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */ -#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR)) -#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR)) -#define BBR (*((volatile unsigned short*)BBR_ADDR)) - -#define BCR (*((volatile unsigned short*)BCR_ADDR)) -#define WCR1 (*((volatile unsigned short*)WCR1_ADDR)) -#define WCR2 (*((volatile unsigned short*)WCR2_ADDR)) -#define WCR3 (*((volatile unsigned short*)WCR3_ADDR)) -#define DCR (*((volatile unsigned short*)DCR_ADDR)) -#define PCR (*((volatile unsigned short*)PCR_ADDR)) -#define RCR (*((volatile unsigned short*)RCR_ADDR)) -#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR)) -#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR)) -#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR)) - -#define TCSR_R (*((volatile unsigned char*)TCSR_ADDR)) -#define TCSR_W (*((volatile unsigned short*)(TCSR_ADDR & ~1))) -#define TCNT_R (*((volatile unsigned char*)TCNT_ADDR)) -#define TCNT_W (*((volatile unsigned short*)(TCNT_ADDR & ~1))) -#define RSTCSR_R (*((volatile unsigned char*)RSTCSR_ADDR)) -#define RSTCSR_W (*((volatile unsigned short*)(RSTCSR_ADDR & ~1))) - -#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR)) - -#define PADR (*((volatile unsigned short*)PADR_ADDR)) -#define PBDR (*((volatile unsigned short*)PBDR_ADDR)) -#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR)) -#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR)) -#define PACR1 (*((volatile unsigned short*)PACR1_ADDR)) -#define PACR2 (*((volatile unsigned short*)PACR2_ADDR)) -#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR)) -#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR)) -#define PCDR (*((volatile unsigned short*)PCDR_ADDR)) - -#define CASCR (*((volatile unsigned char*)CASCR_ADDR)) - -/* byte halves of the ports */ -#define PADRH (*((volatile unsigned char*)PADRH_ADDR)) -#define PADRL (*((volatile unsigned char*)PADRL_ADDR)) -#define PBDRH (*((volatile unsigned char*)PBDRH_ADDR)) -#define PBDRL (*((volatile unsigned char*)PBDRL_ADDR)) -#define PAIORH (*((volatile unsigned char*)PAIORH_ADDR)) -#define PAIORL (*((volatile unsigned char*)PAIORL_ADDR)) -#define PBIORH (*((volatile unsigned char*)PBIORH_ADDR)) -#define PBIORL (*((volatile unsigned char*)PBIORL_ADDR)) - - -/*************************************************************************** - * Register bit definitions - **************************************************************************/ - -/* - * Serial mode register bits - */ - -#define SYNC_MODE 0x80 -#define SEVEN_BIT_DATA 0x40 -#define PARITY_ON 0x20 -#define ODD_PARITY 0x10 -#define STOP_BITS_2 0x08 -#define ENABLE_MULTIP 0x04 -#define PHI_64 0x03 -#define PHI_16 0x02 -#define PHI_4 0x01 - -/* - * Serial control register bits - */ -#define SCI_TIE 0x80 /* Transmit interrupt enable */ -#define SCI_RIE 0x40 /* Receive interrupt enable */ -#define SCI_TE 0x20 /* Transmit enable */ -#define SCI_RE 0x10 /* Receive enable */ -#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ -#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ -#define SCI_CKE1 0x02 /* Clock enable 1 */ -#define SCI_CKE0 0x01 /* Clock enable 0 */ - -/* - * Serial status register bits - */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ -#define SCI_RDRF 0x40 /* Receive data register full */ -#define SCI_ORER 0x20 /* Overrun error */ -#define SCI_FER 0x10 /* Framing error */ -#define SCI_PER 0x08 /* Parity error */ -#define SCI_TEND 0x04 /* Transmit end */ -#define SCI_MPB 0x02 /* Multiprocessor bit */ -#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ - -/* Timer frequency */ -#define TIMER_FREQ CPU_FREQ - -#endif diff --git a/firmware/export/sound.h b/firmware/export/sound.h index 3a26e30b68..9bcb9a8513 100644 --- a/firmware/export/sound.h +++ b/firmware/export/sound.h @@ -109,17 +109,6 @@ void sound_set_hw_eq_band5_frequency(int value); #endif /* AUDIOHW_HAVE_EQ_BAND5 */ #endif /* AUDIOHW_HAVE_EQ */ -#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) -void sound_set_loudness(int value); -void sound_set_avc(int value); -void sound_set_mdb_strength(int value); -void sound_set_mdb_harmonics(int value); -void sound_set_mdb_center(int value); -void sound_set_mdb_shape(int value); -void sound_set_mdb_enable(int value); -void sound_set_superbass(int value); -#endif /* (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) */ - void sound_set(int setting, int value); int sound_val2phys(int setting, int value); diff --git a/firmware/export/tuner.h b/firmware/export/tuner.h index a166eacf33..a3cc985137 100644 --- a/firmware/export/tuner.h +++ b/firmware/export/tuner.h @@ -22,8 +22,9 @@ #ifndef __TUNER_H__ #define __TUNER_H__ +#include + #include "config.h" -#include "hwcompat.h" #ifdef HAVE_RDS_CAP #include @@ -114,12 +115,6 @@ extern int (*tuner_get)(int setting); #include "lv24020lp.h" #endif -/** Samsung S1A0903X01 **/ -#if (CONFIG_TUNER & S1A0903X01) -/* Ondio FM, FM Recorder */ -#include "s1a0903x01.h" -#endif - /** Philips TEA5760 **/ #if (CONFIG_TUNER & TEA5760) #include "tea5760.h" diff --git a/firmware/export/usb.h b/firmware/export/usb.h index 0c74efc9e2..d723f85b1a 100644 --- a/firmware/export/usb.h +++ b/firmware/export/usb.h @@ -134,14 +134,8 @@ enum }; #ifdef HAVE_USB_POWER -#if CONFIG_KEYPAD == RECORDER_PAD -#define USBPOWER_BUTTON BUTTON_F1 -#define USBPOWER_BTN_IGNORE BUTTON_ON -#elif CONFIG_KEYPAD == ONDIO_PAD -#define USBPOWER_BUTTON BUTTON_MENU -#define USBPOWER_BTN_IGNORE BUTTON_OFF /*allow people to define this in config-target.h if they need it*/ -#elif !defined(USBPOWER_BTN_IGNORE) +#if !defined(USBPOWER_BTN_IGNORE) #define USBPOWER_BTN_IGNORE 0 #endif #endif -- cgit v1.2.3