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authorSolomon Peachy <pizza@shaftnet.org>2020-07-15 19:40:55 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-07-24 21:20:13 +0000
commit092c340a2062fa98b7387fc5fd63578ddae7d0b6 (patch)
tree98ec96946eeb2ae709cb0528cc6998e21bb9b290 /firmware/export/sh7034.h
parent17f7cc92c258bc456a27c3e7c5a19c9409851879 (diff)
downloadrockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.tar.gz
rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.zip
[1/4] Remove SH support and all archos targets
This removes all code specific to SH targets Change-Id: I7980523785d2596e65c06430f4638eec74a06061
Diffstat (limited to 'firmware/export/sh7034.h')
-rw-r--r--firmware/export/sh7034.h376
1 files changed, 0 insertions, 376 deletions
diff --git a/firmware/export/sh7034.h b/firmware/export/sh7034.h
deleted file mode 100644
index 2695acbc00..0000000000
--- a/firmware/export/sh7034.h
+++ /dev/null
@@ -1,376 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Alan Korr
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef __SH7034_H__
23#define __SH7034_H__
24
25#define GBR 0x00000000
26
27/* register address macros: */
28
29#define SMR0_ADDR 0x05FFFEC0
30#define BRR0_ADDR 0x05FFFEC1
31#define SCR0_ADDR 0x05FFFEC2
32#define TDR0_ADDR 0x05FFFEC3
33#define SSR0_ADDR 0x05FFFEC4
34#define RDR0_ADDR 0x05FFFEC5
35#define SMR1_ADDR 0x05FFFEC8
36#define BRR1_ADDR 0x05FFFEC9
37#define SCR1_ADDR 0x05FFFECA
38#define TDR1_ADDR 0x05FFFECB
39#define SSR1_ADDR 0x05FFFECC
40#define RDR1_ADDR 0x05FFFECD
41
42#define ADDRAH_ADDR 0x05FFFEE0
43#define ADDRAL_ADDR 0x05FFFEE1
44#define ADDRBH_ADDR 0x05FFFEE2
45#define ADDRBL_ADDR 0x05FFFEE3
46#define ADDRCH_ADDR 0x05FFFEE4
47#define ADDRCL_ADDR 0x05FFFEE5
48#define ADDRDH_ADDR 0x05FFFEE6
49#define ADDRDL_ADDR 0x05FFFEE7
50#define ADCSR_ADDR 0x05FFFEE8
51#define ADCR_ADDR 0x05FFFEE9
52
53#define TSTR_ADDR 0x05FFFF00
54#define TSNC_ADDR 0x05FFFF01
55#define TMDR_ADDR 0x05FFFF02
56#define TFCR_ADDR 0x05FFFF03
57#define TCR0_ADDR 0x05FFFF04
58#define TIOR0_ADDR 0x05FFFF05
59#define TIER0_ADDR 0x05FFFF06
60#define TSR0_ADDR 0x05FFFF07
61#define TCNT0_ADDR 0x05FFFF08
62#define GRA0_ADDR 0x05FFFF0A
63#define GRB0_ADDR 0x05FFFF0C
64#define TCR1_ADDR 0x05FFFF0E
65#define TIOR1_ADDR 0x05FFFF0F
66#define TIER1_ADDR 0x05FFFF10
67#define TSR1_ADDR 0x05FFFF11
68#define TCNT1_ADDR 0x05FFFF12
69#define GRA1_ADDR 0x05FFFF14
70#define GRB1_ADDR 0x05FFFF16
71#define TCR2_ADDR 0x05FFFF18
72#define TIOR2_ADDR 0x05FFFF19
73#define TIER2_ADDR 0x05FFFF1A
74#define TSR2_ADDR 0x05FFFF1B
75#define TCNT2_ADDR 0x05FFFF1C
76#define GRA2_ADDR 0x05FFFF1E
77#define GRB2_ADDR 0x05FFFF20
78#define TCR3_ADDR 0x05FFFF22
79#define TIOR3_ADDR 0x05FFFF23
80#define TIER3_ADDR 0x05FFFF24
81#define TSR3_ADDR 0x05FFFF25
82#define TCNT3_ADDR 0x05FFFF26
83#define GRA3_ADDR 0x05FFFF28
84#define GRB3_ADDR 0x05FFFF2A
85#define BRA3_ADDR 0x05FFFF2C
86#define BRB3_ADDR 0x05FFFF2E
87#define TOCR_ADDR 0x05FFFF31
88#define TCR4_ADDR 0x05FFFF32
89#define TIOR4_ADDR 0x05FFFF33
90#define TIER4_ADDR 0x05FFFF34
91#define TSR4_ADDR 0x05FFFF35
92#define TCNT4_ADDR 0x05FFFF36
93#define GRA4_ADDR 0x05FFFF38
94#define GRB4_ADDR 0x05FFFF3A
95#define BRA4_ADDR 0x05FFFF3C
96#define BRB4_ADDR 0x05FFFF3E
97
98#define SAR0_ADDR 0x05FFFF40
99#define DAR0_ADDR 0x05FFFF44
100#define DMAOR_ADDR 0x05FFFF48
101#define DTCR0_ADDR 0x05FFFF4A
102#define CHCR0_ADDR 0x05FFFF4E
103#define SAR1_ADDR 0x05FFFF50
104#define DAR1_ADDR 0x05FFFF54
105#define DTCR1_ADDR 0x05FFFF5A
106#define CHCR1_ADDR 0x05FFFF5E
107#define SAR2_ADDR 0x05FFFF60
108#define DAR2_ADDR 0x05FFFF64
109#define DTCR2_ADDR 0x05FFFF6A
110#define CHCR2_ADDR 0x05FFFF6E
111#define SAR3_ADDR 0x05FFFF70
112#define DAR3_ADDR 0x05FFFF74
113#define DTCR3_ADDR 0x05FFFF7A
114#define CHCR3_ADDR 0x05FFFF7E
115
116#define IPRA_ADDR 0x05FFFF84
117#define IPRB_ADDR 0x05FFFF86
118#define IPRC_ADDR 0x05FFFF88
119#define IPRD_ADDR 0x05FFFF8A
120#define IPRE_ADDR 0x05FFFF8C
121#define ICR_ADDR 0x05FFFF8E
122
123#define BARH_ADDR 0x05FFFF90
124#define BARL_ADDR 0x05FFFF92
125#define BAMRH_ADDR 0x05FFFF94
126#define BAMRL_ADDR 0x05FFFF96
127#define BBR_ADDR 0x05FFFF98
128
129#define BCR_ADDR 0x05FFFFA0
130#define WCR1_ADDR 0x05FFFFA2
131#define WCR2_ADDR 0x05FFFFA4
132#define WCR3_ADDR 0x05FFFFA6
133#define DCR_ADDR 0x05FFFFA8
134#define PCR_ADDR 0x05FFFFAA
135#define RCR_ADDR 0x05FFFFAC
136#define RTCSR_ADDR 0x05FFFFAE
137#define RTCNT_ADDR 0x05FFFFB0
138#define RTCOR_ADDR 0x05FFFFB2
139
140#define TCSR_ADDR 0x05FFFFB8
141#define TCNT_ADDR 0x05FFFFB9
142#define RSTCSR_ADDR 0x05FFFFBB
143
144#define SBYCR_ADDR 0x05FFFFBC
145
146#define PADR_ADDR 0x05FFFFC0
147#define PBDR_ADDR 0x05FFFFC2
148#define PAIOR_ADDR 0x05FFFFC4
149#define PBIOR_ADDR 0x05FFFFC6
150#define PACR1_ADDR 0x05FFFFC8
151#define PACR2_ADDR 0x05FFFFCA
152#define PBCR1_ADDR 0x05FFFFCC
153#define PBCR2_ADDR 0x05FFFFCE
154#define PCDR_ADDR 0x05FFFFD0
155
156#define CASCR_ADDR 0x05FFFFEE
157
158/* byte halves of the ports */
159#define PADRH_ADDR 0x05FFFFC0
160#define PADRL_ADDR 0x05FFFFC1
161#define PBDRH_ADDR 0x05FFFFC2
162#define PBDRL_ADDR 0x05FFFFC3
163#define PAIORH_ADDR 0x05FFFFC4
164#define PAIORL_ADDR 0x05FFFFC5
165#define PBIORH_ADDR 0x05FFFFC6
166#define PBIORL_ADDR 0x05FFFFC7
167
168
169/* A/D control/status register bits */
170#define ADCSR_CH 0x07 /* Channel/group select */
171#define ADCSR_CKS 0x08 /* Clock select */
172#define ADCSR_SCAN 0x10 /* Scan mode */
173#define ADCSR_ADST 0x20 /* A/D start */
174#define ADCSR_ADIE 0x40 /* A/D interrupt enable */
175#define ADCSR_ADF 0x80 /* A/D end flag */
176
177/* A/D control register bits */
178#define ADCR_TRGE 0x80 /* Trigger enable */
179
180/* register macros for direct access: */
181
182#define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
183#define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
184#define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
185#define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
186#define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
187#define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
188#define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
189#define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
190#define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
191#define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
192#define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
193#define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
194
195#define ADDRA (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */
196#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
197#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
198#define ADDRB (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */
199#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
200#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
201#define ADDRC (*((volatile unsigned short*)ADDRCH_ADDR)) /* combined */
202#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
203#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
204#define ADDRD (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */
205#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
206#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
207#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
208#define ADCR (*((volatile unsigned char*)ADCR_ADDR))
209
210#define TSTR (*((volatile unsigned char*)TSTR_ADDR))
211#define TSNC (*((volatile unsigned char*)TSNC_ADDR))
212#define TMDR (*((volatile unsigned char*)TMDR_ADDR))
213#define TFCR (*((volatile unsigned char*)TFCR_ADDR))
214#define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
215#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
216#define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
217#define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
218#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
219#define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
220#define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
221#define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
222#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
223#define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
224#define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
225#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
226#define GRA1 (*((volatile unsigned short*)GRA1_ADDR))
227#define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
228#define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
229#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
230#define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
231#define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
232#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
233#define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
234#define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
235#define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
236#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
237#define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
238#define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
239#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
240#define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
241#define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
242#define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
243#define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
244#define TOCR (*((volatile unsigned char*)TOCR_ADDR))
245#define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
246#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
247#define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
248#define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
249#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
250#define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
251#define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
252#define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
253#define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
254
255#define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
256#define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
257#define DMAOR (*((volatile unsigned short*)DMAOR_ADDR))
258#define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR))
259#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
260#define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
261#define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
262#define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR))
263#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
264#define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
265#define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
266#define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR))
267#define CHCR2 (*((volatile unsigned short*)CHCR2_ADDR))
268#define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
269#define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
270#define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR))
271#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
272
273#define IPRA (*((volatile unsigned short*)IPRA_ADDR))
274#define IPRB (*((volatile unsigned short*)IPRB_ADDR))
275#define IPRC (*((volatile unsigned short*)IPRC_ADDR))
276#define IPRD (*((volatile unsigned short*)IPRD_ADDR))
277#define IPRE (*((volatile unsigned short*)IPRE_ADDR))
278#define ICR (*((volatile unsigned short*)ICR_ADDR))
279
280#define BAR (*((volatile unsigned long*)BARH_ADDR)) /* combined */
281#define BARH (*((volatile unsigned short*)BARH_ADDR))
282#define BARL (*((volatile unsigned short*)BARL_ADDR))
283#define BAMR (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */
284#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
285#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
286#define BBR (*((volatile unsigned short*)BBR_ADDR))
287
288#define BCR (*((volatile unsigned short*)BCR_ADDR))
289#define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
290#define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
291#define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
292#define DCR (*((volatile unsigned short*)DCR_ADDR))
293#define PCR (*((volatile unsigned short*)PCR_ADDR))
294#define RCR (*((volatile unsigned short*)RCR_ADDR))
295#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
296#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
297#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
298
299#define TCSR_R (*((volatile unsigned char*)TCSR_ADDR))
300#define TCSR_W (*((volatile unsigned short*)(TCSR_ADDR & ~1)))
301#define TCNT_R (*((volatile unsigned char*)TCNT_ADDR))
302#define TCNT_W (*((volatile unsigned short*)(TCNT_ADDR & ~1)))
303#define RSTCSR_R (*((volatile unsigned char*)RSTCSR_ADDR))
304#define RSTCSR_W (*((volatile unsigned short*)(RSTCSR_ADDR & ~1)))
305
306#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
307
308#define PADR (*((volatile unsigned short*)PADR_ADDR))
309#define PBDR (*((volatile unsigned short*)PBDR_ADDR))
310#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
311#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
312#define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
313#define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
314#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
315#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
316#define PCDR (*((volatile unsigned short*)PCDR_ADDR))
317
318#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
319
320/* byte halves of the ports */
321#define PADRH (*((volatile unsigned char*)PADRH_ADDR))
322#define PADRL (*((volatile unsigned char*)PADRL_ADDR))
323#define PBDRH (*((volatile unsigned char*)PBDRH_ADDR))
324#define PBDRL (*((volatile unsigned char*)PBDRL_ADDR))
325#define PAIORH (*((volatile unsigned char*)PAIORH_ADDR))
326#define PAIORL (*((volatile unsigned char*)PAIORL_ADDR))
327#define PBIORH (*((volatile unsigned char*)PBIORH_ADDR))
328#define PBIORL (*((volatile unsigned char*)PBIORL_ADDR))
329
330
331/***************************************************************************
332 * Register bit definitions
333 **************************************************************************/
334
335/*
336 * Serial mode register bits
337 */
338
339#define SYNC_MODE 0x80
340#define SEVEN_BIT_DATA 0x40
341#define PARITY_ON 0x20
342#define ODD_PARITY 0x10
343#define STOP_BITS_2 0x08
344#define ENABLE_MULTIP 0x04
345#define PHI_64 0x03
346#define PHI_16 0x02
347#define PHI_4 0x01
348
349/*
350 * Serial control register bits
351 */
352#define SCI_TIE 0x80 /* Transmit interrupt enable */
353#define SCI_RIE 0x40 /* Receive interrupt enable */
354#define SCI_TE 0x20 /* Transmit enable */
355#define SCI_RE 0x10 /* Receive enable */
356#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
357#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
358#define SCI_CKE1 0x02 /* Clock enable 1 */
359#define SCI_CKE0 0x01 /* Clock enable 0 */
360
361/*
362 * Serial status register bits
363 */
364#define SCI_TDRE 0x80 /* Transmit data register empty */
365#define SCI_RDRF 0x40 /* Receive data register full */
366#define SCI_ORER 0x20 /* Overrun error */
367#define SCI_FER 0x10 /* Framing error */
368#define SCI_PER 0x08 /* Parity error */
369#define SCI_TEND 0x04 /* Transmit end */
370#define SCI_MPB 0x02 /* Multiprocessor bit */
371#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
372
373/* Timer frequency */
374#define TIMER_FREQ CPU_FREQ
375
376#endif
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