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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
| commit | cff83c78c7ddce36bd42ec992e201f947f7b4a0a (patch) | |
| tree | 3e8c83f51807f7c88b2b591ce35279deb349abda /firmware/crt0.S | |
| parent | aa9c329dbee3c91c7473c174a9502ec3a7b3df43 (diff) | |
| download | rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.tar.gz rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.zip | |
ColdFire: DCR is a 16-bit register
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/crt0.S')
| -rw-r--r-- | firmware/crt0.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index ee8beb7f2f..887f7de1f9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
| @@ -190,8 +190,8 @@ irq_handler: | |||
| 190 | 190 | ||
| 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
| 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
| 193 | move.l #0x80010000,%d0 | 193 | move.w #0x8001,%d0 |
| 194 | move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ | 194 | move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ |
| 195 | 195 | ||
| 196 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because | 196 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because |
| 197 | the 5249 BGA chip has a fault which disables the use of A24. The | 197 | the 5249 BGA chip has a fault which disables the use of A24. The |