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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
commit | cff83c78c7ddce36bd42ec992e201f947f7b4a0a (patch) | |
tree | 3e8c83f51807f7c88b2b591ce35279deb349abda | |
parent | aa9c329dbee3c91c7473c174a9502ec3a7b3df43 (diff) | |
download | rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.tar.gz rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.zip |
ColdFire: DCR is a 16-bit register
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/crt0.S | 4 | ||||
-rw-r--r-- | firmware/export/mcf5249.h | 2 | ||||
-rw-r--r-- | firmware/system.c | 10 |
3 files changed, 8 insertions, 8 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index ee8beb7f2f..887f7de1f9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -190,8 +190,8 @@ irq_handler: | |||
190 | 190 | ||
191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
193 | move.l #0x80010000,%d0 | 193 | move.w #0x8001,%d0 |
194 | move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ | 194 | move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ |
195 | 195 | ||
196 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because | 196 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because |
197 | the 5249 BGA chip has a fault which disables the use of A24. The | 197 | the 5249 BGA chip has a fault which disables the use of A24. The |
diff --git a/firmware/export/mcf5249.h b/firmware/export/mcf5249.h index d4ed2849ce..398b31156d 100644 --- a/firmware/export/mcf5249.h +++ b/firmware/export/mcf5249.h | |||
@@ -44,7 +44,7 @@ | |||
44 | #define CSMR3 (*(volatile unsigned long *)(MBAR + 0x0a8)) | 44 | #define CSMR3 (*(volatile unsigned long *)(MBAR + 0x0a8)) |
45 | #define CSCR3 (*(volatile unsigned long *)(MBAR + 0x0ac)) | 45 | #define CSCR3 (*(volatile unsigned long *)(MBAR + 0x0ac)) |
46 | 46 | ||
47 | #define DCR (*(volatile unsigned long *)(MBAR + 0x100)) | 47 | #define DCR (*(volatile unsigned short *)(MBAR + 0x100)) |
48 | #define DACR0 (*(volatile unsigned long *)(MBAR + 0x108)) | 48 | #define DACR0 (*(volatile unsigned long *)(MBAR + 0x108)) |
49 | #define DMR0 (*(volatile unsigned long *)(MBAR + 0x10c)) | 49 | #define DMR0 (*(volatile unsigned long *)(MBAR + 0x10c)) |
50 | #define DACR1 (*(volatile unsigned long *)(MBAR + 0x110)) | 50 | #define DACR1 (*(volatile unsigned long *)(MBAR + 0x110)) |
diff --git a/firmware/system.c b/firmware/system.c index be6be1dfaa..d095e1574a 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -480,7 +480,7 @@ void set_cpu_frequency(long frequency) | |||
480 | switch(frequency) | 480 | switch(frequency) |
481 | { | 481 | { |
482 | case CPUFREQ_MAX: | 482 | case CPUFREQ_MAX: |
483 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 483 | DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass |
484 | frequency */ | 484 | frequency */ |
485 | PLLCR &= ~1; /* Bypass mode */ | 485 | PLLCR &= ~1; /* Bypass mode */ |
486 | PLLCR = 0x11853005; | 486 | PLLCR = 0x11853005; |
@@ -488,7 +488,7 @@ void set_cpu_frequency(long frequency) | |||
488 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ | 488 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ |
489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
490 | This may take up to 10ms! */ | 490 | This may take up to 10ms! */ |
491 | DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ | 491 | DCR = (DCR & ~0x01ff) | 28; /* Refresh timer */ |
492 | cpu_frequency = CPUFREQ_MAX; | 492 | cpu_frequency = CPUFREQ_MAX; |
493 | tick_start(1000/HZ); | 493 | tick_start(1000/HZ); |
494 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 494 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
@@ -499,7 +499,7 @@ void set_cpu_frequency(long frequency) | |||
499 | break; | 499 | break; |
500 | 500 | ||
501 | case CPUFREQ_NORMAL: | 501 | case CPUFREQ_NORMAL: |
502 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 502 | DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass |
503 | frequency */ | 503 | frequency */ |
504 | PLLCR &= ~1; /* Bypass mode */ | 504 | PLLCR &= ~1; /* Bypass mode */ |
505 | PLLCR = 0x10886001; | 505 | PLLCR = 0x10886001; |
@@ -507,7 +507,7 @@ void set_cpu_frequency(long frequency) | |||
507 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 507 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
508 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 508 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
509 | This may take up to 10ms! */ | 509 | This may take up to 10ms! */ |
510 | DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */ | 510 | DCR = (DCR & ~0x01ff) | 10; /* Refresh timer */ |
511 | cpu_frequency = CPUFREQ_NORMAL; | 511 | cpu_frequency = CPUFREQ_NORMAL; |
512 | tick_start(1000/HZ); | 512 | tick_start(1000/HZ); |
513 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 513 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ |
@@ -517,7 +517,7 @@ void set_cpu_frequency(long frequency) | |||
517 | MFDR2 = 0x13; | 517 | MFDR2 = 0x13; |
518 | break; | 518 | break; |
519 | default: | 519 | default: |
520 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 520 | DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass |
521 | frequency */ | 521 | frequency */ |
522 | PLLCR = 0x00000000; /* Bypass mode */ | 522 | PLLCR = 0x00000000; /* Bypass mode */ |
523 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 523 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |