From cff83c78c7ddce36bd42ec992e201f947f7b4a0a Mon Sep 17 00:00:00 2001 From: Linus Nielsen Feltzing Date: Wed, 8 Jun 2005 07:37:32 +0000 Subject: ColdFire: DCR is a 16-bit register git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657 --- firmware/crt0.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'firmware/crt0.S') diff --git a/firmware/crt0.S b/firmware/crt0.S index ee8beb7f2f..887f7de1f9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S @@ -190,8 +190,8 @@ irq_handler: /* Set up the DRAM controller. The refresh is based on the 11.2896MHz clock (5.6448MHz bus frequency). We haven't yet started the PLL */ - move.l #0x80010000,%d0 - move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ + move.w #0x8001,%d0 + move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ /* Note: we place the SDRAM on an 0x1000000 (16M) offset because the 5249 BGA chip has a fault which disables the use of A24. The -- cgit v1.2.3