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| author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-29 16:34:32 +0100 |
|---|---|---|
| committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-29 16:34:32 +0100 |
| commit | f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf (patch) | |
| tree | 7b919f493c0dc5263d7c2c91894fc26bc0503b30 | |
| parent | 8056b7fd1a333fe4d0c7ed8d3de0caf702f89164 (diff) | |
| download | rockbox-f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf.tar.gz rockbox-f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf.zip | |
x1000: Complete the register definitions
I think this covers everything now, although some fields are missing
enum values. Those can be added in if and when they are needed.
Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/aic.h | 258 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/efuse.h | 173 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/pcm.h | 251 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/ssi.h | 323 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/uart.h | 390 | ||||
| -rw-r--r-- | utils/reggen-ng/x1000.reggen | 297 |
6 files changed, 1692 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h index e9c68511d7..d212ddc4e1 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/aic.h +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
| @@ -356,4 +356,262 @@ | |||
| 356 | #define JN_AIC_DR AIC_DR | 356 | #define JN_AIC_DR AIC_DR |
| 357 | #define JI_AIC_DR | 357 | #define JI_AIC_DR |
| 358 | 358 | ||
| 359 | #define REG_AIC_SPENA jz_reg(AIC_SPENA) | ||
| 360 | #define JA_AIC_SPENA (0xb0020000 + 0x80) | ||
| 361 | #define JT_AIC_SPENA JIO_32_RW | ||
| 362 | #define JN_AIC_SPENA AIC_SPENA | ||
| 363 | #define JI_AIC_SPENA | ||
| 364 | |||
| 365 | #define REG_AIC_SPCTRL jz_reg(AIC_SPCTRL) | ||
| 366 | #define JA_AIC_SPCTRL (0xb0020000 + 0x84) | ||
| 367 | #define JT_AIC_SPCTRL JIO_32_RW | ||
| 368 | #define JN_AIC_SPCTRL AIC_SPCTRL | ||
| 369 | #define JI_AIC_SPCTRL | ||
| 370 | #define BP_AIC_SPCTRL_DMA_EN 15 | ||
| 371 | #define BM_AIC_SPCTRL_DMA_EN 0x8000 | ||
| 372 | #define BF_AIC_SPCTRL_DMA_EN(v) (((v) & 0x1) << 15) | ||
| 373 | #define BFM_AIC_SPCTRL_DMA_EN(v) BM_AIC_SPCTRL_DMA_EN | ||
| 374 | #define BF_AIC_SPCTRL_DMA_EN_V(e) BF_AIC_SPCTRL_DMA_EN(BV_AIC_SPCTRL_DMA_EN__##e) | ||
| 375 | #define BFM_AIC_SPCTRL_DMA_EN_V(v) BM_AIC_SPCTRL_DMA_EN | ||
| 376 | #define BP_AIC_SPCTRL_D_TYPE 14 | ||
| 377 | #define BM_AIC_SPCTRL_D_TYPE 0x4000 | ||
| 378 | #define BF_AIC_SPCTRL_D_TYPE(v) (((v) & 0x1) << 14) | ||
| 379 | #define BFM_AIC_SPCTRL_D_TYPE(v) BM_AIC_SPCTRL_D_TYPE | ||
| 380 | #define BF_AIC_SPCTRL_D_TYPE_V(e) BF_AIC_SPCTRL_D_TYPE(BV_AIC_SPCTRL_D_TYPE__##e) | ||
| 381 | #define BFM_AIC_SPCTRL_D_TYPE_V(v) BM_AIC_SPCTRL_D_TYPE | ||
| 382 | #define BP_AIC_SPCTRL_SIGN_N 13 | ||
| 383 | #define BM_AIC_SPCTRL_SIGN_N 0x2000 | ||
| 384 | #define BF_AIC_SPCTRL_SIGN_N(v) (((v) & 0x1) << 13) | ||
| 385 | #define BFM_AIC_SPCTRL_SIGN_N(v) BM_AIC_SPCTRL_SIGN_N | ||
| 386 | #define BF_AIC_SPCTRL_SIGN_N_V(e) BF_AIC_SPCTRL_SIGN_N(BV_AIC_SPCTRL_SIGN_N__##e) | ||
| 387 | #define BFM_AIC_SPCTRL_SIGN_N_V(v) BM_AIC_SPCTRL_SIGN_N | ||
| 388 | #define BP_AIC_SPCTRL_INVALID 12 | ||
| 389 | #define BM_AIC_SPCTRL_INVALID 0x1000 | ||
| 390 | #define BF_AIC_SPCTRL_INVALID(v) (((v) & 0x1) << 12) | ||
| 391 | #define BFM_AIC_SPCTRL_INVALID(v) BM_AIC_SPCTRL_INVALID | ||
| 392 | #define BF_AIC_SPCTRL_INVALID_V(e) BF_AIC_SPCTRL_INVALID(BV_AIC_SPCTRL_INVALID__##e) | ||
| 393 | #define BFM_AIC_SPCTRL_INVALID_V(v) BM_AIC_SPCTRL_INVALID | ||
| 394 | #define BP_AIC_SPCTRL_SFT_RST 11 | ||
| 395 | #define BM_AIC_SPCTRL_SFT_RST 0x800 | ||
| 396 | #define BF_AIC_SPCTRL_SFT_RST(v) (((v) & 0x1) << 11) | ||
| 397 | #define BFM_AIC_SPCTRL_SFT_RST(v) BM_AIC_SPCTRL_SFT_RST | ||
| 398 | #define BF_AIC_SPCTRL_SFT_RST_V(e) BF_AIC_SPCTRL_SFT_RST(BV_AIC_SPCTRL_SFT_RST__##e) | ||
| 399 | #define BFM_AIC_SPCTRL_SFT_RST_V(v) BM_AIC_SPCTRL_SFT_RST | ||
| 400 | #define BP_AIC_SPCTRL_SPDIF_I2S 10 | ||
| 401 | #define BM_AIC_SPCTRL_SPDIF_I2S 0x400 | ||
| 402 | #define BF_AIC_SPCTRL_SPDIF_I2S(v) (((v) & 0x1) << 10) | ||
| 403 | #define BFM_AIC_SPCTRL_SPDIF_I2S(v) BM_AIC_SPCTRL_SPDIF_I2S | ||
| 404 | #define BF_AIC_SPCTRL_SPDIF_I2S_V(e) BF_AIC_SPCTRL_SPDIF_I2S(BV_AIC_SPCTRL_SPDIF_I2S__##e) | ||
| 405 | #define BFM_AIC_SPCTRL_SPDIF_I2S_V(v) BM_AIC_SPCTRL_SPDIF_I2S | ||
| 406 | #define BP_AIC_SPCTRL_M_TRIG 1 | ||
| 407 | #define BM_AIC_SPCTRL_M_TRIG 0x2 | ||
| 408 | #define BF_AIC_SPCTRL_M_TRIG(v) (((v) & 0x1) << 1) | ||
| 409 | #define BFM_AIC_SPCTRL_M_TRIG(v) BM_AIC_SPCTRL_M_TRIG | ||
| 410 | #define BF_AIC_SPCTRL_M_TRIG_V(e) BF_AIC_SPCTRL_M_TRIG(BV_AIC_SPCTRL_M_TRIG__##e) | ||
| 411 | #define BFM_AIC_SPCTRL_M_TRIG_V(v) BM_AIC_SPCTRL_M_TRIG | ||
| 412 | #define BP_AIC_SPCTRL_M_FFUR 0 | ||
| 413 | #define BM_AIC_SPCTRL_M_FFUR 0x1 | ||
| 414 | #define BF_AIC_SPCTRL_M_FFUR(v) (((v) & 0x1) << 0) | ||
| 415 | #define BFM_AIC_SPCTRL_M_FFUR(v) BM_AIC_SPCTRL_M_FFUR | ||
| 416 | #define BF_AIC_SPCTRL_M_FFUR_V(e) BF_AIC_SPCTRL_M_FFUR(BV_AIC_SPCTRL_M_FFUR__##e) | ||
| 417 | #define BFM_AIC_SPCTRL_M_FFUR_V(v) BM_AIC_SPCTRL_M_FFUR | ||
| 418 | |||
| 419 | #define REG_AIC_SPSTATE jz_reg(AIC_SPSTATE) | ||
| 420 | #define JA_AIC_SPSTATE (0xb0020000 + 0x88) | ||
| 421 | #define JT_AIC_SPSTATE JIO_32_RW | ||
| 422 | #define JN_AIC_SPSTATE AIC_SPSTATE | ||
| 423 | #define JI_AIC_SPSTATE | ||
| 424 | #define BP_AIC_SPSTATE_FIFO_LEVEL 8 | ||
| 425 | #define BM_AIC_SPSTATE_FIFO_LEVEL 0x7f00 | ||
| 426 | #define BF_AIC_SPSTATE_FIFO_LEVEL(v) (((v) & 0x7f) << 8) | ||
| 427 | #define BFM_AIC_SPSTATE_FIFO_LEVEL(v) BM_AIC_SPSTATE_FIFO_LEVEL | ||
| 428 | #define BF_AIC_SPSTATE_FIFO_LEVEL_V(e) BF_AIC_SPSTATE_FIFO_LEVEL(BV_AIC_SPSTATE_FIFO_LEVEL__##e) | ||
| 429 | #define BFM_AIC_SPSTATE_FIFO_LEVEL_V(v) BM_AIC_SPSTATE_FIFO_LEVEL | ||
| 430 | #define BP_AIC_SPSTATE_BUSY 7 | ||
| 431 | #define BM_AIC_SPSTATE_BUSY 0x80 | ||
| 432 | #define BF_AIC_SPSTATE_BUSY(v) (((v) & 0x1) << 7) | ||
| 433 | #define BFM_AIC_SPSTATE_BUSY(v) BM_AIC_SPSTATE_BUSY | ||
| 434 | #define BF_AIC_SPSTATE_BUSY_V(e) BF_AIC_SPSTATE_BUSY(BV_AIC_SPSTATE_BUSY__##e) | ||
| 435 | #define BFM_AIC_SPSTATE_BUSY_V(v) BM_AIC_SPSTATE_BUSY | ||
| 436 | #define BP_AIC_SPSTATE_F_TRIG 1 | ||
| 437 | #define BM_AIC_SPSTATE_F_TRIG 0x2 | ||
| 438 | #define BF_AIC_SPSTATE_F_TRIG(v) (((v) & 0x1) << 1) | ||
| 439 | #define BFM_AIC_SPSTATE_F_TRIG(v) BM_AIC_SPSTATE_F_TRIG | ||
| 440 | #define BF_AIC_SPSTATE_F_TRIG_V(e) BF_AIC_SPSTATE_F_TRIG(BV_AIC_SPSTATE_F_TRIG__##e) | ||
| 441 | #define BFM_AIC_SPSTATE_F_TRIG_V(v) BM_AIC_SPSTATE_F_TRIG | ||
| 442 | #define BP_AIC_SPSTATE_F_FFUR 0 | ||
| 443 | #define BM_AIC_SPSTATE_F_FFUR 0x1 | ||
| 444 | #define BF_AIC_SPSTATE_F_FFUR(v) (((v) & 0x1) << 0) | ||
| 445 | #define BFM_AIC_SPSTATE_F_FFUR(v) BM_AIC_SPSTATE_F_FFUR | ||
| 446 | #define BF_AIC_SPSTATE_F_FFUR_V(e) BF_AIC_SPSTATE_F_FFUR(BV_AIC_SPSTATE_F_FFUR__##e) | ||
| 447 | #define BFM_AIC_SPSTATE_F_FFUR_V(v) BM_AIC_SPSTATE_F_FFUR | ||
| 448 | |||
| 449 | #define REG_AIC_SPCFG1 jz_reg(AIC_SPCFG1) | ||
| 450 | #define JA_AIC_SPCFG1 (0xb0020000 + 0x8c) | ||
| 451 | #define JT_AIC_SPCFG1 JIO_32_RW | ||
| 452 | #define JN_AIC_SPCFG1 AIC_SPCFG1 | ||
| 453 | #define JI_AIC_SPCFG1 | ||
| 454 | #define BP_AIC_SPCFG1_TRIG 12 | ||
| 455 | #define BM_AIC_SPCFG1_TRIG 0x3000 | ||
| 456 | #define BF_AIC_SPCFG1_TRIG(v) (((v) & 0x3) << 12) | ||
| 457 | #define BFM_AIC_SPCFG1_TRIG(v) BM_AIC_SPCFG1_TRIG | ||
| 458 | #define BF_AIC_SPCFG1_TRIG_V(e) BF_AIC_SPCFG1_TRIG(BV_AIC_SPCFG1_TRIG__##e) | ||
| 459 | #define BFM_AIC_SPCFG1_TRIG_V(v) BM_AIC_SPCFG1_TRIG | ||
| 460 | #define BP_AIC_SPCFG1_SRC_NUM 8 | ||
| 461 | #define BM_AIC_SPCFG1_SRC_NUM 0xf00 | ||
| 462 | #define BF_AIC_SPCFG1_SRC_NUM(v) (((v) & 0xf) << 8) | ||
| 463 | #define BFM_AIC_SPCFG1_SRC_NUM(v) BM_AIC_SPCFG1_SRC_NUM | ||
| 464 | #define BF_AIC_SPCFG1_SRC_NUM_V(e) BF_AIC_SPCFG1_SRC_NUM(BV_AIC_SPCFG1_SRC_NUM__##e) | ||
| 465 | #define BFM_AIC_SPCFG1_SRC_NUM_V(v) BM_AIC_SPCFG1_SRC_NUM | ||
| 466 | #define BP_AIC_SPCFG1_CH1_NUM 4 | ||
| 467 | #define BM_AIC_SPCFG1_CH1_NUM 0xf0 | ||
| 468 | #define BF_AIC_SPCFG1_CH1_NUM(v) (((v) & 0xf) << 4) | ||
| 469 | #define BFM_AIC_SPCFG1_CH1_NUM(v) BM_AIC_SPCFG1_CH1_NUM | ||
| 470 | #define BF_AIC_SPCFG1_CH1_NUM_V(e) BF_AIC_SPCFG1_CH1_NUM(BV_AIC_SPCFG1_CH1_NUM__##e) | ||
| 471 | #define BFM_AIC_SPCFG1_CH1_NUM_V(v) BM_AIC_SPCFG1_CH1_NUM | ||
| 472 | #define BP_AIC_SPCFG1_CH2_NUM 0 | ||
| 473 | #define BM_AIC_SPCFG1_CH2_NUM 0xf | ||
| 474 | #define BF_AIC_SPCFG1_CH2_NUM(v) (((v) & 0xf) << 0) | ||
| 475 | #define BFM_AIC_SPCFG1_CH2_NUM(v) BM_AIC_SPCFG1_CH2_NUM | ||
| 476 | #define BF_AIC_SPCFG1_CH2_NUM_V(e) BF_AIC_SPCFG1_CH2_NUM(BV_AIC_SPCFG1_CH2_NUM__##e) | ||
| 477 | #define BFM_AIC_SPCFG1_CH2_NUM_V(v) BM_AIC_SPCFG1_CH2_NUM | ||
| 478 | #define BP_AIC_SPCFG1_INIT_LEVEL 17 | ||
| 479 | #define BM_AIC_SPCFG1_INIT_LEVEL 0x20000 | ||
| 480 | #define BF_AIC_SPCFG1_INIT_LEVEL(v) (((v) & 0x1) << 17) | ||
| 481 | #define BFM_AIC_SPCFG1_INIT_LEVEL(v) BM_AIC_SPCFG1_INIT_LEVEL | ||
| 482 | #define BF_AIC_SPCFG1_INIT_LEVEL_V(e) BF_AIC_SPCFG1_INIT_LEVEL(BV_AIC_SPCFG1_INIT_LEVEL__##e) | ||
| 483 | #define BFM_AIC_SPCFG1_INIT_LEVEL_V(v) BM_AIC_SPCFG1_INIT_LEVEL | ||
| 484 | #define BP_AIC_SPCFG1_ZERO_VALID 16 | ||
| 485 | #define BM_AIC_SPCFG1_ZERO_VALID 0x10000 | ||
| 486 | #define BF_AIC_SPCFG1_ZERO_VALID(v) (((v) & 0x1) << 16) | ||
| 487 | #define BFM_AIC_SPCFG1_ZERO_VALID(v) BM_AIC_SPCFG1_ZERO_VALID | ||
| 488 | #define BF_AIC_SPCFG1_ZERO_VALID_V(e) BF_AIC_SPCFG1_ZERO_VALID(BV_AIC_SPCFG1_ZERO_VALID__##e) | ||
| 489 | #define BFM_AIC_SPCFG1_ZERO_VALID_V(v) BM_AIC_SPCFG1_ZERO_VALID | ||
| 490 | |||
| 491 | #define REG_AIC_SPCFG2 jz_reg(AIC_SPCFG2) | ||
| 492 | #define JA_AIC_SPCFG2 (0xb0020000 + 0x90) | ||
| 493 | #define JT_AIC_SPCFG2 JIO_32_RW | ||
| 494 | #define JN_AIC_SPCFG2 AIC_SPCFG2 | ||
| 495 | #define JI_AIC_SPCFG2 | ||
| 496 | #define BP_AIC_SPCFG2_FS 26 | ||
| 497 | #define BM_AIC_SPCFG2_FS 0x3c000000 | ||
| 498 | #define BF_AIC_SPCFG2_FS(v) (((v) & 0xf) << 26) | ||
| 499 | #define BFM_AIC_SPCFG2_FS(v) BM_AIC_SPCFG2_FS | ||
| 500 | #define BF_AIC_SPCFG2_FS_V(e) BF_AIC_SPCFG2_FS(BV_AIC_SPCFG2_FS__##e) | ||
| 501 | #define BFM_AIC_SPCFG2_FS_V(v) BM_AIC_SPCFG2_FS | ||
| 502 | #define BP_AIC_SPCFG2_ORG_FRQ 22 | ||
| 503 | #define BM_AIC_SPCFG2_ORG_FRQ 0x3c00000 | ||
| 504 | #define BF_AIC_SPCFG2_ORG_FRQ(v) (((v) & 0xf) << 22) | ||
| 505 | #define BFM_AIC_SPCFG2_ORG_FRQ(v) BM_AIC_SPCFG2_ORG_FRQ | ||
| 506 | #define BF_AIC_SPCFG2_ORG_FRQ_V(e) BF_AIC_SPCFG2_ORG_FRQ(BV_AIC_SPCFG2_ORG_FRQ__##e) | ||
| 507 | #define BFM_AIC_SPCFG2_ORG_FRQ_V(v) BM_AIC_SPCFG2_ORG_FRQ | ||
| 508 | #define BP_AIC_SPCFG2_SAMPL_WL 19 | ||
| 509 | #define BM_AIC_SPCFG2_SAMPL_WL 0x380000 | ||
| 510 | #define BF_AIC_SPCFG2_SAMPL_WL(v) (((v) & 0x7) << 19) | ||
| 511 | #define BFM_AIC_SPCFG2_SAMPL_WL(v) BM_AIC_SPCFG2_SAMPL_WL | ||
| 512 | #define BF_AIC_SPCFG2_SAMPL_WL_V(e) BF_AIC_SPCFG2_SAMPL_WL(BV_AIC_SPCFG2_SAMPL_WL__##e) | ||
| 513 | #define BFM_AIC_SPCFG2_SAMPL_WL_V(v) BM_AIC_SPCFG2_SAMPL_WL | ||
| 514 | #define BP_AIC_SPCFG2_CLK_ACU 16 | ||
| 515 | #define BM_AIC_SPCFG2_CLK_ACU 0x30000 | ||
| 516 | #define BF_AIC_SPCFG2_CLK_ACU(v) (((v) & 0x3) << 16) | ||
| 517 | #define BFM_AIC_SPCFG2_CLK_ACU(v) BM_AIC_SPCFG2_CLK_ACU | ||
| 518 | #define BF_AIC_SPCFG2_CLK_ACU_V(e) BF_AIC_SPCFG2_CLK_ACU(BV_AIC_SPCFG2_CLK_ACU__##e) | ||
| 519 | #define BFM_AIC_SPCFG2_CLK_ACU_V(v) BM_AIC_SPCFG2_CLK_ACU | ||
| 520 | #define BP_AIC_SPCFG2_CAT_CODE 8 | ||
| 521 | #define BM_AIC_SPCFG2_CAT_CODE 0xff00 | ||
| 522 | #define BF_AIC_SPCFG2_CAT_CODE(v) (((v) & 0xff) << 8) | ||
| 523 | #define BFM_AIC_SPCFG2_CAT_CODE(v) BM_AIC_SPCFG2_CAT_CODE | ||
| 524 | #define BF_AIC_SPCFG2_CAT_CODE_V(e) BF_AIC_SPCFG2_CAT_CODE(BV_AIC_SPCFG2_CAT_CODE__##e) | ||
| 525 | #define BFM_AIC_SPCFG2_CAT_CODE_V(v) BM_AIC_SPCFG2_CAT_CODE | ||
| 526 | #define BP_AIC_SPCFG2_CH_MD 6 | ||
| 527 | #define BM_AIC_SPCFG2_CH_MD 0xc0 | ||
| 528 | #define BF_AIC_SPCFG2_CH_MD(v) (((v) & 0x3) << 6) | ||
| 529 | #define BFM_AIC_SPCFG2_CH_MD(v) BM_AIC_SPCFG2_CH_MD | ||
| 530 | #define BF_AIC_SPCFG2_CH_MD_V(e) BF_AIC_SPCFG2_CH_MD(BV_AIC_SPCFG2_CH_MD__##e) | ||
| 531 | #define BFM_AIC_SPCFG2_CH_MD_V(v) BM_AIC_SPCFG2_CH_MD | ||
| 532 | #define BP_AIC_SPCFG2_MAX_WL 18 | ||
| 533 | #define BM_AIC_SPCFG2_MAX_WL 0x40000 | ||
| 534 | #define BF_AIC_SPCFG2_MAX_WL(v) (((v) & 0x1) << 18) | ||
| 535 | #define BFM_AIC_SPCFG2_MAX_WL(v) BM_AIC_SPCFG2_MAX_WL | ||
| 536 | #define BF_AIC_SPCFG2_MAX_WL_V(e) BF_AIC_SPCFG2_MAX_WL(BV_AIC_SPCFG2_MAX_WL__##e) | ||
| 537 | #define BFM_AIC_SPCFG2_MAX_WL_V(v) BM_AIC_SPCFG2_MAX_WL | ||
| 538 | #define BP_AIC_SPCFG2_PRE 3 | ||
| 539 | #define BM_AIC_SPCFG2_PRE 0x8 | ||
| 540 | #define BF_AIC_SPCFG2_PRE(v) (((v) & 0x1) << 3) | ||
| 541 | #define BFM_AIC_SPCFG2_PRE(v) BM_AIC_SPCFG2_PRE | ||
| 542 | #define BF_AIC_SPCFG2_PRE_V(e) BF_AIC_SPCFG2_PRE(BV_AIC_SPCFG2_PRE__##e) | ||
| 543 | #define BFM_AIC_SPCFG2_PRE_V(v) BM_AIC_SPCFG2_PRE | ||
| 544 | #define BP_AIC_SPCFG2_COPY_N 2 | ||
| 545 | #define BM_AIC_SPCFG2_COPY_N 0x4 | ||
| 546 | #define BF_AIC_SPCFG2_COPY_N(v) (((v) & 0x1) << 2) | ||
| 547 | #define BFM_AIC_SPCFG2_COPY_N(v) BM_AIC_SPCFG2_COPY_N | ||
| 548 | #define BF_AIC_SPCFG2_COPY_N_V(e) BF_AIC_SPCFG2_COPY_N(BV_AIC_SPCFG2_COPY_N__##e) | ||
| 549 | #define BFM_AIC_SPCFG2_COPY_N_V(v) BM_AIC_SPCFG2_COPY_N | ||
| 550 | #define BP_AIC_SPCFG2_AUDIO_N 1 | ||
| 551 | #define BM_AIC_SPCFG2_AUDIO_N 0x2 | ||
| 552 | #define BF_AIC_SPCFG2_AUDIO_N(v) (((v) & 0x1) << 1) | ||
| 553 | #define BFM_AIC_SPCFG2_AUDIO_N(v) BM_AIC_SPCFG2_AUDIO_N | ||
| 554 | #define BF_AIC_SPCFG2_AUDIO_N_V(e) BF_AIC_SPCFG2_AUDIO_N(BV_AIC_SPCFG2_AUDIO_N__##e) | ||
| 555 | #define BFM_AIC_SPCFG2_AUDIO_N_V(v) BM_AIC_SPCFG2_AUDIO_N | ||
| 556 | #define BP_AIC_SPCFG2_CON_PRO 0 | ||
| 557 | #define BM_AIC_SPCFG2_CON_PRO 0x1 | ||
| 558 | #define BF_AIC_SPCFG2_CON_PRO(v) (((v) & 0x1) << 0) | ||
| 559 | #define BFM_AIC_SPCFG2_CON_PRO(v) BM_AIC_SPCFG2_CON_PRO | ||
| 560 | #define BF_AIC_SPCFG2_CON_PRO_V(e) BF_AIC_SPCFG2_CON_PRO(BV_AIC_SPCFG2_CON_PRO__##e) | ||
| 561 | #define BFM_AIC_SPCFG2_CON_PRO_V(v) BM_AIC_SPCFG2_CON_PRO | ||
| 562 | |||
| 563 | #define REG_AIC_SPFIFO jz_reg(AIC_SPFIFO) | ||
| 564 | #define JA_AIC_SPFIFO (0xb0020000 + 0x94) | ||
| 565 | #define JT_AIC_SPFIFO JIO_32_RW | ||
| 566 | #define JN_AIC_SPFIFO AIC_SPFIFO | ||
| 567 | #define JI_AIC_SPFIFO | ||
| 568 | |||
| 569 | #define REG_AIC_RGADW jz_reg(AIC_RGADW) | ||
| 570 | #define JA_AIC_RGADW (0xb0020000 + 0xa4) | ||
| 571 | #define JT_AIC_RGADW JIO_32_RW | ||
| 572 | #define JN_AIC_RGADW AIC_RGADW | ||
| 573 | #define JI_AIC_RGADW | ||
| 574 | #define BP_AIC_RGADW_ADDR 8 | ||
| 575 | #define BM_AIC_RGADW_ADDR 0x7f00 | ||
| 576 | #define BF_AIC_RGADW_ADDR(v) (((v) & 0x7f) << 8) | ||
| 577 | #define BFM_AIC_RGADW_ADDR(v) BM_AIC_RGADW_ADDR | ||
| 578 | #define BF_AIC_RGADW_ADDR_V(e) BF_AIC_RGADW_ADDR(BV_AIC_RGADW_ADDR__##e) | ||
| 579 | #define BFM_AIC_RGADW_ADDR_V(v) BM_AIC_RGADW_ADDR | ||
| 580 | #define BP_AIC_RGADW_DATA 0 | ||
| 581 | #define BM_AIC_RGADW_DATA 0xff | ||
| 582 | #define BF_AIC_RGADW_DATA(v) (((v) & 0xff) << 0) | ||
| 583 | #define BFM_AIC_RGADW_DATA(v) BM_AIC_RGADW_DATA | ||
| 584 | #define BF_AIC_RGADW_DATA_V(e) BF_AIC_RGADW_DATA(BV_AIC_RGADW_DATA__##e) | ||
| 585 | #define BFM_AIC_RGADW_DATA_V(v) BM_AIC_RGADW_DATA | ||
| 586 | #define BP_AIC_RGADW_ICRST 31 | ||
| 587 | #define BM_AIC_RGADW_ICRST 0x80000000 | ||
| 588 | #define BF_AIC_RGADW_ICRST(v) (((v) & 0x1) << 31) | ||
| 589 | #define BFM_AIC_RGADW_ICRST(v) BM_AIC_RGADW_ICRST | ||
| 590 | #define BF_AIC_RGADW_ICRST_V(e) BF_AIC_RGADW_ICRST(BV_AIC_RGADW_ICRST__##e) | ||
| 591 | #define BFM_AIC_RGADW_ICRST_V(v) BM_AIC_RGADW_ICRST | ||
| 592 | #define BP_AIC_RGADW_RGWR 16 | ||
| 593 | #define BM_AIC_RGADW_RGWR 0x10000 | ||
| 594 | #define BF_AIC_RGADW_RGWR(v) (((v) & 0x1) << 16) | ||
| 595 | #define BFM_AIC_RGADW_RGWR(v) BM_AIC_RGADW_RGWR | ||
| 596 | #define BF_AIC_RGADW_RGWR_V(e) BF_AIC_RGADW_RGWR(BV_AIC_RGADW_RGWR__##e) | ||
| 597 | #define BFM_AIC_RGADW_RGWR_V(v) BM_AIC_RGADW_RGWR | ||
| 598 | |||
| 599 | #define REG_AIC_RGDATA jz_reg(AIC_RGDATA) | ||
| 600 | #define JA_AIC_RGDATA (0xb0020000 + 0xa8) | ||
| 601 | #define JT_AIC_RGDATA JIO_32_RW | ||
| 602 | #define JN_AIC_RGDATA AIC_RGDATA | ||
| 603 | #define JI_AIC_RGDATA | ||
| 604 | #define BP_AIC_RGDATA_DATA 0 | ||
| 605 | #define BM_AIC_RGDATA_DATA 0xff | ||
| 606 | #define BF_AIC_RGDATA_DATA(v) (((v) & 0xff) << 0) | ||
| 607 | #define BFM_AIC_RGDATA_DATA(v) BM_AIC_RGDATA_DATA | ||
| 608 | #define BF_AIC_RGDATA_DATA_V(e) BF_AIC_RGDATA_DATA(BV_AIC_RGDATA_DATA__##e) | ||
| 609 | #define BFM_AIC_RGDATA_DATA_V(v) BM_AIC_RGDATA_DATA | ||
| 610 | #define BP_AIC_RGDATA_IRQ 8 | ||
| 611 | #define BM_AIC_RGDATA_IRQ 0x100 | ||
| 612 | #define BF_AIC_RGDATA_IRQ(v) (((v) & 0x1) << 8) | ||
| 613 | #define BFM_AIC_RGDATA_IRQ(v) BM_AIC_RGDATA_IRQ | ||
| 614 | #define BF_AIC_RGDATA_IRQ_V(e) BF_AIC_RGDATA_IRQ(BV_AIC_RGDATA_IRQ__##e) | ||
| 615 | #define BFM_AIC_RGDATA_IRQ_V(v) BM_AIC_RGDATA_IRQ | ||
| 616 | |||
| 359 | #endif /* __HEADERGEN_AIC_H__*/ | 617 | #endif /* __HEADERGEN_AIC_H__*/ |
diff --git a/firmware/target/mips/ingenic_x1000/x1000/efuse.h b/firmware/target/mips/ingenic_x1000/x1000/efuse.h new file mode 100644 index 0000000000..8628cfd08b --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/efuse.h | |||
| @@ -0,0 +1,173 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_EFUSE_H__ | ||
| 25 | #define __HEADERGEN_EFUSE_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_EFUSE_CTRL jz_reg(EFUSE_CTRL) | ||
| 30 | #define JA_EFUSE_CTRL (0xb3540000 + 0x0) | ||
| 31 | #define JT_EFUSE_CTRL JIO_32_RW | ||
| 32 | #define JN_EFUSE_CTRL EFUSE_CTRL | ||
| 33 | #define JI_EFUSE_CTRL | ||
| 34 | #define BP_EFUSE_CTRL_ADDR 21 | ||
| 35 | #define BM_EFUSE_CTRL_ADDR 0xfe00000 | ||
| 36 | #define BF_EFUSE_CTRL_ADDR(v) (((v) & 0x7f) << 21) | ||
| 37 | #define BFM_EFUSE_CTRL_ADDR(v) BM_EFUSE_CTRL_ADDR | ||
| 38 | #define BF_EFUSE_CTRL_ADDR_V(e) BF_EFUSE_CTRL_ADDR(BV_EFUSE_CTRL_ADDR__##e) | ||
| 39 | #define BFM_EFUSE_CTRL_ADDR_V(v) BM_EFUSE_CTRL_ADDR | ||
| 40 | #define BP_EFUSE_CTRL_LENGTH 16 | ||
| 41 | #define BM_EFUSE_CTRL_LENGTH 0x1f0000 | ||
| 42 | #define BF_EFUSE_CTRL_LENGTH(v) (((v) & 0x1f) << 16) | ||
| 43 | #define BFM_EFUSE_CTRL_LENGTH(v) BM_EFUSE_CTRL_LENGTH | ||
| 44 | #define BF_EFUSE_CTRL_LENGTH_V(e) BF_EFUSE_CTRL_LENGTH(BV_EFUSE_CTRL_LENGTH__##e) | ||
| 45 | #define BFM_EFUSE_CTRL_LENGTH_V(v) BM_EFUSE_CTRL_LENGTH | ||
| 46 | #define BP_EFUSE_CTRL_PG_EN 15 | ||
| 47 | #define BM_EFUSE_CTRL_PG_EN 0x8000 | ||
| 48 | #define BF_EFUSE_CTRL_PG_EN(v) (((v) & 0x1) << 15) | ||
| 49 | #define BFM_EFUSE_CTRL_PG_EN(v) BM_EFUSE_CTRL_PG_EN | ||
| 50 | #define BF_EFUSE_CTRL_PG_EN_V(e) BF_EFUSE_CTRL_PG_EN(BV_EFUSE_CTRL_PG_EN__##e) | ||
| 51 | #define BFM_EFUSE_CTRL_PG_EN_V(v) BM_EFUSE_CTRL_PG_EN | ||
| 52 | #define BP_EFUSE_CTRL_WR_EN 1 | ||
| 53 | #define BM_EFUSE_CTRL_WR_EN 0x2 | ||
| 54 | #define BF_EFUSE_CTRL_WR_EN(v) (((v) & 0x1) << 1) | ||
| 55 | #define BFM_EFUSE_CTRL_WR_EN(v) BM_EFUSE_CTRL_WR_EN | ||
| 56 | #define BF_EFUSE_CTRL_WR_EN_V(e) BF_EFUSE_CTRL_WR_EN(BV_EFUSE_CTRL_WR_EN__##e) | ||
| 57 | #define BFM_EFUSE_CTRL_WR_EN_V(v) BM_EFUSE_CTRL_WR_EN | ||
| 58 | #define BP_EFUSE_CTRL_RD_EN 0 | ||
| 59 | #define BM_EFUSE_CTRL_RD_EN 0x1 | ||
| 60 | #define BF_EFUSE_CTRL_RD_EN(v) (((v) & 0x1) << 0) | ||
| 61 | #define BFM_EFUSE_CTRL_RD_EN(v) BM_EFUSE_CTRL_RD_EN | ||
| 62 | #define BF_EFUSE_CTRL_RD_EN_V(e) BF_EFUSE_CTRL_RD_EN(BV_EFUSE_CTRL_RD_EN__##e) | ||
| 63 | #define BFM_EFUSE_CTRL_RD_EN_V(v) BM_EFUSE_CTRL_RD_EN | ||
| 64 | |||
| 65 | #define REG_EFUSE_CFG jz_reg(EFUSE_CFG) | ||
| 66 | #define JA_EFUSE_CFG (0xb3540000 + 0x4) | ||
| 67 | #define JT_EFUSE_CFG JIO_32_RW | ||
| 68 | #define JN_EFUSE_CFG EFUSE_CFG | ||
| 69 | #define JI_EFUSE_CFG | ||
| 70 | #define BP_EFUSE_CFG_RD_AJD 20 | ||
| 71 | #define BM_EFUSE_CFG_RD_AJD 0x300000 | ||
| 72 | #define BF_EFUSE_CFG_RD_AJD(v) (((v) & 0x3) << 20) | ||
| 73 | #define BFM_EFUSE_CFG_RD_AJD(v) BM_EFUSE_CFG_RD_AJD | ||
| 74 | #define BF_EFUSE_CFG_RD_AJD_V(e) BF_EFUSE_CFG_RD_AJD(BV_EFUSE_CFG_RD_AJD__##e) | ||
| 75 | #define BFM_EFUSE_CFG_RD_AJD_V(v) BM_EFUSE_CFG_RD_AJD | ||
| 76 | #define BP_EFUSE_CFG_RD_STROBE 16 | ||
| 77 | #define BM_EFUSE_CFG_RD_STROBE 0x70000 | ||
| 78 | #define BF_EFUSE_CFG_RD_STROBE(v) (((v) & 0x7) << 16) | ||
| 79 | #define BFM_EFUSE_CFG_RD_STROBE(v) BM_EFUSE_CFG_RD_STROBE | ||
| 80 | #define BF_EFUSE_CFG_RD_STROBE_V(e) BF_EFUSE_CFG_RD_STROBE(BV_EFUSE_CFG_RD_STROBE__##e) | ||
| 81 | #define BFM_EFUSE_CFG_RD_STROBE_V(v) BM_EFUSE_CFG_RD_STROBE | ||
| 82 | #define BP_EFUSE_CFG_WR_ADJ 12 | ||
| 83 | #define BM_EFUSE_CFG_WR_ADJ 0x3000 | ||
| 84 | #define BF_EFUSE_CFG_WR_ADJ(v) (((v) & 0x3) << 12) | ||
| 85 | #define BFM_EFUSE_CFG_WR_ADJ(v) BM_EFUSE_CFG_WR_ADJ | ||
| 86 | #define BF_EFUSE_CFG_WR_ADJ_V(e) BF_EFUSE_CFG_WR_ADJ(BV_EFUSE_CFG_WR_ADJ__##e) | ||
| 87 | #define BFM_EFUSE_CFG_WR_ADJ_V(v) BM_EFUSE_CFG_WR_ADJ | ||
| 88 | #define BP_EFUSE_CFG_WR_STROBE 0 | ||
| 89 | #define BM_EFUSE_CFG_WR_STROBE 0x1ff | ||
| 90 | #define BF_EFUSE_CFG_WR_STROBE(v) (((v) & 0x1ff) << 0) | ||
| 91 | #define BFM_EFUSE_CFG_WR_STROBE(v) BM_EFUSE_CFG_WR_STROBE | ||
| 92 | #define BF_EFUSE_CFG_WR_STROBE_V(e) BF_EFUSE_CFG_WR_STROBE(BV_EFUSE_CFG_WR_STROBE__##e) | ||
| 93 | #define BFM_EFUSE_CFG_WR_STROBE_V(v) BM_EFUSE_CFG_WR_STROBE | ||
| 94 | #define BP_EFUSE_CFG_INT_EN 31 | ||
| 95 | #define BM_EFUSE_CFG_INT_EN 0x80000000 | ||
| 96 | #define BF_EFUSE_CFG_INT_EN(v) (((v) & 0x1) << 31) | ||
| 97 | #define BFM_EFUSE_CFG_INT_EN(v) BM_EFUSE_CFG_INT_EN | ||
| 98 | #define BF_EFUSE_CFG_INT_EN_V(e) BF_EFUSE_CFG_INT_EN(BV_EFUSE_CFG_INT_EN__##e) | ||
| 99 | #define BFM_EFUSE_CFG_INT_EN_V(v) BM_EFUSE_CFG_INT_EN | ||
| 100 | |||
| 101 | #define REG_EFUSE_STATE jz_reg(EFUSE_STATE) | ||
| 102 | #define JA_EFUSE_STATE (0xb3540000 + 0x8) | ||
| 103 | #define JT_EFUSE_STATE JIO_32_RW | ||
| 104 | #define JN_EFUSE_STATE EFUSE_STATE | ||
| 105 | #define JI_EFUSE_STATE | ||
| 106 | #define BP_EFUSE_STATE_UK_PRT 23 | ||
| 107 | #define BM_EFUSE_STATE_UK_PRT 0x800000 | ||
| 108 | #define BF_EFUSE_STATE_UK_PRT(v) (((v) & 0x1) << 23) | ||
| 109 | #define BFM_EFUSE_STATE_UK_PRT(v) BM_EFUSE_STATE_UK_PRT | ||
| 110 | #define BF_EFUSE_STATE_UK_PRT_V(e) BF_EFUSE_STATE_UK_PRT(BV_EFUSE_STATE_UK_PRT__##e) | ||
| 111 | #define BFM_EFUSE_STATE_UK_PRT_V(v) BM_EFUSE_STATE_UK_PRT | ||
| 112 | #define BP_EFUSE_STATE_NKU_PRT 22 | ||
| 113 | #define BM_EFUSE_STATE_NKU_PRT 0x400000 | ||
| 114 | #define BF_EFUSE_STATE_NKU_PRT(v) (((v) & 0x1) << 22) | ||
| 115 | #define BFM_EFUSE_STATE_NKU_PRT(v) BM_EFUSE_STATE_NKU_PRT | ||
| 116 | #define BF_EFUSE_STATE_NKU_PRT_V(e) BF_EFUSE_STATE_NKU_PRT(BV_EFUSE_STATE_NKU_PRT__##e) | ||
| 117 | #define BFM_EFUSE_STATE_NKU_PRT_V(v) BM_EFUSE_STATE_NKU_PRT | ||
| 118 | #define BP_EFUSE_STATE_EXKEY_EN 21 | ||
| 119 | #define BM_EFUSE_STATE_EXKEY_EN 0x200000 | ||
| 120 | #define BF_EFUSE_STATE_EXKEY_EN(v) (((v) & 0x1) << 21) | ||
| 121 | #define BFM_EFUSE_STATE_EXKEY_EN(v) BM_EFUSE_STATE_EXKEY_EN | ||
| 122 | #define BF_EFUSE_STATE_EXKEY_EN_V(e) BF_EFUSE_STATE_EXKEY_EN(BV_EFUSE_STATE_EXKEY_EN__##e) | ||
| 123 | #define BFM_EFUSE_STATE_EXKEY_EN_V(v) BM_EFUSE_STATE_EXKEY_EN | ||
| 124 | #define BP_EFUSE_STATE_CUSTID_PRT 15 | ||
| 125 | #define BM_EFUSE_STATE_CUSTID_PRT 0x8000 | ||
| 126 | #define BF_EFUSE_STATE_CUSTID_PRT(v) (((v) & 0x1) << 15) | ||
| 127 | #define BFM_EFUSE_STATE_CUSTID_PRT(v) BM_EFUSE_STATE_CUSTID_PRT | ||
| 128 | #define BF_EFUSE_STATE_CUSTID_PRT_V(e) BF_EFUSE_STATE_CUSTID_PRT(BV_EFUSE_STATE_CUSTID_PRT__##e) | ||
| 129 | #define BFM_EFUSE_STATE_CUSTID_PRT_V(v) BM_EFUSE_STATE_CUSTID_PRT | ||
| 130 | #define BP_EFUSE_STATE_CHIPID_PRT 14 | ||
| 131 | #define BM_EFUSE_STATE_CHIPID_PRT 0x4000 | ||
| 132 | #define BF_EFUSE_STATE_CHIPID_PRT(v) (((v) & 0x1) << 14) | ||
| 133 | #define BFM_EFUSE_STATE_CHIPID_PRT(v) BM_EFUSE_STATE_CHIPID_PRT | ||
| 134 | #define BF_EFUSE_STATE_CHIPID_PRT_V(e) BF_EFUSE_STATE_CHIPID_PRT(BV_EFUSE_STATE_CHIPID_PRT__##e) | ||
| 135 | #define BFM_EFUSE_STATE_CHIPID_PRT_V(v) BM_EFUSE_STATE_CHIPID_PRT | ||
| 136 | #define BP_EFUSE_STATE_SECBOOT_PRT 12 | ||
| 137 | #define BM_EFUSE_STATE_SECBOOT_PRT 0x1000 | ||
| 138 | #define BF_EFUSE_STATE_SECBOOT_PRT(v) (((v) & 0x1) << 12) | ||
| 139 | #define BFM_EFUSE_STATE_SECBOOT_PRT(v) BM_EFUSE_STATE_SECBOOT_PRT | ||
| 140 | #define BF_EFUSE_STATE_SECBOOT_PRT_V(e) BF_EFUSE_STATE_SECBOOT_PRT(BV_EFUSE_STATE_SECBOOT_PRT__##e) | ||
| 141 | #define BFM_EFUSE_STATE_SECBOOT_PRT_V(v) BM_EFUSE_STATE_SECBOOT_PRT | ||
| 142 | #define BP_EFUSE_STATE_DIS_JTAG 11 | ||
| 143 | #define BM_EFUSE_STATE_DIS_JTAG 0x800 | ||
| 144 | #define BF_EFUSE_STATE_DIS_JTAG(v) (((v) & 0x1) << 11) | ||
| 145 | #define BFM_EFUSE_STATE_DIS_JTAG(v) BM_EFUSE_STATE_DIS_JTAG | ||
| 146 | #define BF_EFUSE_STATE_DIS_JTAG_V(e) BF_EFUSE_STATE_DIS_JTAG(BV_EFUSE_STATE_DIS_JTAG__##e) | ||
| 147 | #define BFM_EFUSE_STATE_DIS_JTAG_V(v) BM_EFUSE_STATE_DIS_JTAG | ||
| 148 | #define BP_EFUSE_STATE_SECBOOT_EN 8 | ||
| 149 | #define BM_EFUSE_STATE_SECBOOT_EN 0x100 | ||
| 150 | #define BF_EFUSE_STATE_SECBOOT_EN(v) (((v) & 0x1) << 8) | ||
| 151 | #define BFM_EFUSE_STATE_SECBOOT_EN(v) BM_EFUSE_STATE_SECBOOT_EN | ||
| 152 | #define BF_EFUSE_STATE_SECBOOT_EN_V(e) BF_EFUSE_STATE_SECBOOT_EN(BV_EFUSE_STATE_SECBOOT_EN__##e) | ||
| 153 | #define BFM_EFUSE_STATE_SECBOOT_EN_V(v) BM_EFUSE_STATE_SECBOOT_EN | ||
| 154 | #define BP_EFUSE_STATE_WR_DONE 1 | ||
| 155 | #define BM_EFUSE_STATE_WR_DONE 0x2 | ||
| 156 | #define BF_EFUSE_STATE_WR_DONE(v) (((v) & 0x1) << 1) | ||
| 157 | #define BFM_EFUSE_STATE_WR_DONE(v) BM_EFUSE_STATE_WR_DONE | ||
| 158 | #define BF_EFUSE_STATE_WR_DONE_V(e) BF_EFUSE_STATE_WR_DONE(BV_EFUSE_STATE_WR_DONE__##e) | ||
| 159 | #define BFM_EFUSE_STATE_WR_DONE_V(v) BM_EFUSE_STATE_WR_DONE | ||
| 160 | #define BP_EFUSE_STATE_RD_DONE 0 | ||
| 161 | #define BM_EFUSE_STATE_RD_DONE 0x1 | ||
| 162 | #define BF_EFUSE_STATE_RD_DONE(v) (((v) & 0x1) << 0) | ||
| 163 | #define BFM_EFUSE_STATE_RD_DONE(v) BM_EFUSE_STATE_RD_DONE | ||
| 164 | #define BF_EFUSE_STATE_RD_DONE_V(e) BF_EFUSE_STATE_RD_DONE(BV_EFUSE_STATE_RD_DONE__##e) | ||
| 165 | #define BFM_EFUSE_STATE_RD_DONE_V(v) BM_EFUSE_STATE_RD_DONE | ||
| 166 | |||
| 167 | #define REG_EFUSE_DATA(_n1) jz_reg(EFUSE_DATA(_n1)) | ||
| 168 | #define JA_EFUSE_DATA(_n1) (0xb3540000 + 0xc + (_n1) * 0x4) | ||
| 169 | #define JT_EFUSE_DATA(_n1) JIO_32_RW | ||
| 170 | #define JN_EFUSE_DATA(_n1) EFUSE_DATA | ||
| 171 | #define JI_EFUSE_DATA(_n1) (_n1) | ||
| 172 | |||
| 173 | #endif /* __HEADERGEN_EFUSE_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/pcm.h b/firmware/target/mips/ingenic_x1000/x1000/pcm.h new file mode 100644 index 0000000000..e47a2e5c13 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/pcm.h | |||
| @@ -0,0 +1,251 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_PCM_H__ | ||
| 25 | #define __HEADERGEN_PCM_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_PCM_CTL jz_reg(PCM_CTL) | ||
| 30 | #define JA_PCM_CTL (0xb0071000 + 0x0) | ||
| 31 | #define JT_PCM_CTL JIO_32_RW | ||
| 32 | #define JN_PCM_CTL PCM_CTL | ||
| 33 | #define JI_PCM_CTL | ||
| 34 | #define BP_PCM_CTL_ERDMA 9 | ||
| 35 | #define BM_PCM_CTL_ERDMA 0x200 | ||
| 36 | #define BF_PCM_CTL_ERDMA(v) (((v) & 0x1) << 9) | ||
| 37 | #define BFM_PCM_CTL_ERDMA(v) BM_PCM_CTL_ERDMA | ||
| 38 | #define BF_PCM_CTL_ERDMA_V(e) BF_PCM_CTL_ERDMA(BV_PCM_CTL_ERDMA__##e) | ||
| 39 | #define BFM_PCM_CTL_ERDMA_V(v) BM_PCM_CTL_ERDMA | ||
| 40 | #define BP_PCM_CTL_ETDMA 8 | ||
| 41 | #define BM_PCM_CTL_ETDMA 0x100 | ||
| 42 | #define BF_PCM_CTL_ETDMA(v) (((v) & 0x1) << 8) | ||
| 43 | #define BFM_PCM_CTL_ETDMA(v) BM_PCM_CTL_ETDMA | ||
| 44 | #define BF_PCM_CTL_ETDMA_V(e) BF_PCM_CTL_ETDMA(BV_PCM_CTL_ETDMA__##e) | ||
| 45 | #define BFM_PCM_CTL_ETDMA_V(v) BM_PCM_CTL_ETDMA | ||
| 46 | #define BP_PCM_CTL_LSMP 7 | ||
| 47 | #define BM_PCM_CTL_LSMP 0x80 | ||
| 48 | #define BF_PCM_CTL_LSMP(v) (((v) & 0x1) << 7) | ||
| 49 | #define BFM_PCM_CTL_LSMP(v) BM_PCM_CTL_LSMP | ||
| 50 | #define BF_PCM_CTL_LSMP_V(e) BF_PCM_CTL_LSMP(BV_PCM_CTL_LSMP__##e) | ||
| 51 | #define BFM_PCM_CTL_LSMP_V(v) BM_PCM_CTL_LSMP | ||
| 52 | #define BP_PCM_CTL_ERPL 6 | ||
| 53 | #define BM_PCM_CTL_ERPL 0x40 | ||
| 54 | #define BF_PCM_CTL_ERPL(v) (((v) & 0x1) << 6) | ||
| 55 | #define BFM_PCM_CTL_ERPL(v) BM_PCM_CTL_ERPL | ||
| 56 | #define BF_PCM_CTL_ERPL_V(e) BF_PCM_CTL_ERPL(BV_PCM_CTL_ERPL__##e) | ||
| 57 | #define BFM_PCM_CTL_ERPL_V(v) BM_PCM_CTL_ERPL | ||
| 58 | #define BP_PCM_CTL_EREC 5 | ||
| 59 | #define BM_PCM_CTL_EREC 0x20 | ||
| 60 | #define BF_PCM_CTL_EREC(v) (((v) & 0x1) << 5) | ||
| 61 | #define BFM_PCM_CTL_EREC(v) BM_PCM_CTL_EREC | ||
| 62 | #define BF_PCM_CTL_EREC_V(e) BF_PCM_CTL_EREC(BV_PCM_CTL_EREC__##e) | ||
| 63 | #define BFM_PCM_CTL_EREC_V(v) BM_PCM_CTL_EREC | ||
| 64 | #define BP_PCM_CTL_FLUSH 4 | ||
| 65 | #define BM_PCM_CTL_FLUSH 0x10 | ||
| 66 | #define BF_PCM_CTL_FLUSH(v) (((v) & 0x1) << 4) | ||
| 67 | #define BFM_PCM_CTL_FLUSH(v) BM_PCM_CTL_FLUSH | ||
| 68 | #define BF_PCM_CTL_FLUSH_V(e) BF_PCM_CTL_FLUSH(BV_PCM_CTL_FLUSH__##e) | ||
| 69 | #define BFM_PCM_CTL_FLUSH_V(v) BM_PCM_CTL_FLUSH | ||
| 70 | #define BP_PCM_CTL_RST 3 | ||
| 71 | #define BM_PCM_CTL_RST 0x8 | ||
| 72 | #define BF_PCM_CTL_RST(v) (((v) & 0x1) << 3) | ||
| 73 | #define BFM_PCM_CTL_RST(v) BM_PCM_CTL_RST | ||
| 74 | #define BF_PCM_CTL_RST_V(e) BF_PCM_CTL_RST(BV_PCM_CTL_RST__##e) | ||
| 75 | #define BFM_PCM_CTL_RST_V(v) BM_PCM_CTL_RST | ||
| 76 | #define BP_PCM_CTL_CLKEN 1 | ||
| 77 | #define BM_PCM_CTL_CLKEN 0x2 | ||
| 78 | #define BF_PCM_CTL_CLKEN(v) (((v) & 0x1) << 1) | ||
| 79 | #define BFM_PCM_CTL_CLKEN(v) BM_PCM_CTL_CLKEN | ||
| 80 | #define BF_PCM_CTL_CLKEN_V(e) BF_PCM_CTL_CLKEN(BV_PCM_CTL_CLKEN__##e) | ||
| 81 | #define BFM_PCM_CTL_CLKEN_V(v) BM_PCM_CTL_CLKEN | ||
| 82 | #define BP_PCM_CTL_PCMEN 0 | ||
| 83 | #define BM_PCM_CTL_PCMEN 0x1 | ||
| 84 | #define BF_PCM_CTL_PCMEN(v) (((v) & 0x1) << 0) | ||
| 85 | #define BFM_PCM_CTL_PCMEN(v) BM_PCM_CTL_PCMEN | ||
| 86 | #define BF_PCM_CTL_PCMEN_V(e) BF_PCM_CTL_PCMEN(BV_PCM_CTL_PCMEN__##e) | ||
| 87 | #define BFM_PCM_CTL_PCMEN_V(v) BM_PCM_CTL_PCMEN | ||
| 88 | |||
| 89 | #define REG_PCM_CFG jz_reg(PCM_CFG) | ||
| 90 | #define JA_PCM_CFG (0xb0071000 + 0x4) | ||
| 91 | #define JT_PCM_CFG JIO_32_RW | ||
| 92 | #define JN_PCM_CFG PCM_CFG | ||
| 93 | #define JI_PCM_CFG | ||
| 94 | #define BP_PCM_CFG_SLOT 13 | ||
| 95 | #define BM_PCM_CFG_SLOT 0x6000 | ||
| 96 | #define BF_PCM_CFG_SLOT(v) (((v) & 0x3) << 13) | ||
| 97 | #define BFM_PCM_CFG_SLOT(v) BM_PCM_CFG_SLOT | ||
| 98 | #define BF_PCM_CFG_SLOT_V(e) BF_PCM_CFG_SLOT(BV_PCM_CFG_SLOT__##e) | ||
| 99 | #define BFM_PCM_CFG_SLOT_V(v) BM_PCM_CFG_SLOT | ||
| 100 | #define BP_PCM_CFG_RFTH 5 | ||
| 101 | #define BM_PCM_CFG_RFTH 0x1e0 | ||
| 102 | #define BF_PCM_CFG_RFTH(v) (((v) & 0xf) << 5) | ||
| 103 | #define BFM_PCM_CFG_RFTH(v) BM_PCM_CFG_RFTH | ||
| 104 | #define BF_PCM_CFG_RFTH_V(e) BF_PCM_CFG_RFTH(BV_PCM_CFG_RFTH__##e) | ||
| 105 | #define BFM_PCM_CFG_RFTH_V(v) BM_PCM_CFG_RFTH | ||
| 106 | #define BP_PCM_CFG_TFTH 1 | ||
| 107 | #define BM_PCM_CFG_TFTH 0x1e | ||
| 108 | #define BF_PCM_CFG_TFTH(v) (((v) & 0xf) << 1) | ||
| 109 | #define BFM_PCM_CFG_TFTH(v) BM_PCM_CFG_TFTH | ||
| 110 | #define BF_PCM_CFG_TFTH_V(e) BF_PCM_CFG_TFTH(BV_PCM_CFG_TFTH__##e) | ||
| 111 | #define BFM_PCM_CFG_TFTH_V(v) BM_PCM_CFG_TFTH | ||
| 112 | #define BP_PCM_CFG_ISS 12 | ||
| 113 | #define BM_PCM_CFG_ISS 0x1000 | ||
| 114 | #define BF_PCM_CFG_ISS(v) (((v) & 0x1) << 12) | ||
| 115 | #define BFM_PCM_CFG_ISS(v) BM_PCM_CFG_ISS | ||
| 116 | #define BF_PCM_CFG_ISS_V(e) BF_PCM_CFG_ISS(BV_PCM_CFG_ISS__##e) | ||
| 117 | #define BFM_PCM_CFG_ISS_V(v) BM_PCM_CFG_ISS | ||
| 118 | #define BP_PCM_CFG_OSS 11 | ||
| 119 | #define BM_PCM_CFG_OSS 0x800 | ||
| 120 | #define BF_PCM_CFG_OSS(v) (((v) & 0x1) << 11) | ||
| 121 | #define BFM_PCM_CFG_OSS(v) BM_PCM_CFG_OSS | ||
| 122 | #define BF_PCM_CFG_OSS_V(e) BF_PCM_CFG_OSS(BV_PCM_CFG_OSS__##e) | ||
| 123 | #define BFM_PCM_CFG_OSS_V(v) BM_PCM_CFG_OSS | ||
| 124 | #define BP_PCM_CFG_IMSBPOS 10 | ||
| 125 | #define BM_PCM_CFG_IMSBPOS 0x400 | ||
| 126 | #define BF_PCM_CFG_IMSBPOS(v) (((v) & 0x1) << 10) | ||
| 127 | #define BFM_PCM_CFG_IMSBPOS(v) BM_PCM_CFG_IMSBPOS | ||
| 128 | #define BF_PCM_CFG_IMSBPOS_V(e) BF_PCM_CFG_IMSBPOS(BV_PCM_CFG_IMSBPOS__##e) | ||
| 129 | #define BFM_PCM_CFG_IMSBPOS_V(v) BM_PCM_CFG_IMSBPOS | ||
| 130 | #define BP_PCM_CFG_OMSBPOS 9 | ||
| 131 | #define BM_PCM_CFG_OMSBPOS 0x200 | ||
| 132 | #define BF_PCM_CFG_OMSBPOS(v) (((v) & 0x1) << 9) | ||
| 133 | #define BFM_PCM_CFG_OMSBPOS(v) BM_PCM_CFG_OMSBPOS | ||
| 134 | #define BF_PCM_CFG_OMSBPOS_V(e) BF_PCM_CFG_OMSBPOS(BV_PCM_CFG_OMSBPOS__##e) | ||
| 135 | #define BFM_PCM_CFG_OMSBPOS_V(v) BM_PCM_CFG_OMSBPOS | ||
| 136 | #define BP_PCM_CFG_PCMMOD 0 | ||
| 137 | #define BM_PCM_CFG_PCMMOD 0x1 | ||
| 138 | #define BF_PCM_CFG_PCMMOD(v) (((v) & 0x1) << 0) | ||
| 139 | #define BFM_PCM_CFG_PCMMOD(v) BM_PCM_CFG_PCMMOD | ||
| 140 | #define BF_PCM_CFG_PCMMOD_V(e) BF_PCM_CFG_PCMMOD(BV_PCM_CFG_PCMMOD__##e) | ||
| 141 | #define BFM_PCM_CFG_PCMMOD_V(v) BM_PCM_CFG_PCMMOD | ||
| 142 | |||
| 143 | #define REG_PCM_DP jz_reg(PCM_DP) | ||
| 144 | #define JA_PCM_DP (0xb0071000 + 0x8) | ||
| 145 | #define JT_PCM_DP JIO_32_RW | ||
| 146 | #define JN_PCM_DP PCM_DP | ||
| 147 | #define JI_PCM_DP | ||
| 148 | |||
| 149 | #define REG_PCM_INTC jz_reg(PCM_INTC) | ||
| 150 | #define JA_PCM_INTC (0xb0071000 + 0xc) | ||
| 151 | #define JT_PCM_INTC JIO_32_RW | ||
| 152 | #define JN_PCM_INTC PCM_INTC | ||
| 153 | #define JI_PCM_INTC | ||
| 154 | #define BP_PCM_INTC_ETFS 3 | ||
| 155 | #define BM_PCM_INTC_ETFS 0x8 | ||
| 156 | #define BF_PCM_INTC_ETFS(v) (((v) & 0x1) << 3) | ||
| 157 | #define BFM_PCM_INTC_ETFS(v) BM_PCM_INTC_ETFS | ||
| 158 | #define BF_PCM_INTC_ETFS_V(e) BF_PCM_INTC_ETFS(BV_PCM_INTC_ETFS__##e) | ||
| 159 | #define BFM_PCM_INTC_ETFS_V(v) BM_PCM_INTC_ETFS | ||
| 160 | #define BP_PCM_INTC_ETUR 2 | ||
| 161 | #define BM_PCM_INTC_ETUR 0x4 | ||
| 162 | #define BF_PCM_INTC_ETUR(v) (((v) & 0x1) << 2) | ||
| 163 | #define BFM_PCM_INTC_ETUR(v) BM_PCM_INTC_ETUR | ||
| 164 | #define BF_PCM_INTC_ETUR_V(e) BF_PCM_INTC_ETUR(BV_PCM_INTC_ETUR__##e) | ||
| 165 | #define BFM_PCM_INTC_ETUR_V(v) BM_PCM_INTC_ETUR | ||
| 166 | #define BP_PCM_INTC_ERFS 1 | ||
| 167 | #define BM_PCM_INTC_ERFS 0x2 | ||
| 168 | #define BF_PCM_INTC_ERFS(v) (((v) & 0x1) << 1) | ||
| 169 | #define BFM_PCM_INTC_ERFS(v) BM_PCM_INTC_ERFS | ||
| 170 | #define BF_PCM_INTC_ERFS_V(e) BF_PCM_INTC_ERFS(BV_PCM_INTC_ERFS__##e) | ||
| 171 | #define BFM_PCM_INTC_ERFS_V(v) BM_PCM_INTC_ERFS | ||
| 172 | #define BP_PCM_INTC_EROR 0 | ||
| 173 | #define BM_PCM_INTC_EROR 0x1 | ||
| 174 | #define BF_PCM_INTC_EROR(v) (((v) & 0x1) << 0) | ||
| 175 | #define BFM_PCM_INTC_EROR(v) BM_PCM_INTC_EROR | ||
| 176 | #define BF_PCM_INTC_EROR_V(e) BF_PCM_INTC_EROR(BV_PCM_INTC_EROR__##e) | ||
| 177 | #define BFM_PCM_INTC_EROR_V(v) BM_PCM_INTC_EROR | ||
| 178 | |||
| 179 | #define REG_PCM_INTS jz_reg(PCM_INTS) | ||
| 180 | #define JA_PCM_INTS (0xb0071000 + 0x10) | ||
| 181 | #define JT_PCM_INTS JIO_32_RW | ||
| 182 | #define JN_PCM_INTS PCM_INTS | ||
| 183 | #define JI_PCM_INTS | ||
| 184 | #define BP_PCM_INTS_TFL 9 | ||
| 185 | #define BM_PCM_INTS_TFL 0x3e00 | ||
| 186 | #define BF_PCM_INTS_TFL(v) (((v) & 0x1f) << 9) | ||
| 187 | #define BFM_PCM_INTS_TFL(v) BM_PCM_INTS_TFL | ||
| 188 | #define BF_PCM_INTS_TFL_V(e) BF_PCM_INTS_TFL(BV_PCM_INTS_TFL__##e) | ||
| 189 | #define BFM_PCM_INTS_TFL_V(v) BM_PCM_INTS_TFL | ||
| 190 | #define BP_PCM_INTS_RSTS 14 | ||
| 191 | #define BM_PCM_INTS_RSTS 0x4000 | ||
| 192 | #define BF_PCM_INTS_RSTS(v) (((v) & 0x1) << 14) | ||
| 193 | #define BFM_PCM_INTS_RSTS(v) BM_PCM_INTS_RSTS | ||
| 194 | #define BF_PCM_INTS_RSTS_V(e) BF_PCM_INTS_RSTS(BV_PCM_INTS_RSTS__##e) | ||
| 195 | #define BFM_PCM_INTS_RSTS_V(v) BM_PCM_INTS_RSTS | ||
| 196 | #define BP_PCM_INTS_TFS 8 | ||
| 197 | #define BM_PCM_INTS_TFS 0x100 | ||
| 198 | #define BF_PCM_INTS_TFS(v) (((v) & 0x1) << 8) | ||
| 199 | #define BFM_PCM_INTS_TFS(v) BM_PCM_INTS_TFS | ||
| 200 | #define BF_PCM_INTS_TFS_V(e) BF_PCM_INTS_TFS(BV_PCM_INTS_TFS__##e) | ||
| 201 | #define BFM_PCM_INTS_TFS_V(v) BM_PCM_INTS_TFS | ||
| 202 | #define BP_PCM_INTS_TUR 7 | ||
| 203 | #define BM_PCM_INTS_TUR 0x80 | ||
| 204 | #define BF_PCM_INTS_TUR(v) (((v) & 0x1) << 7) | ||
| 205 | #define BFM_PCM_INTS_TUR(v) BM_PCM_INTS_TUR | ||
| 206 | #define BF_PCM_INTS_TUR_V(e) BF_PCM_INTS_TUR(BV_PCM_INTS_TUR__##e) | ||
| 207 | #define BFM_PCM_INTS_TUR_V(v) BM_PCM_INTS_TUR | ||
| 208 | #define BP_PCM_INTS_RFL 2 | ||
| 209 | #define BM_PCM_INTS_RFL 0x7c | ||
| 210 | #define BF_PCM_INTS_RFL(v) (((v) & 0x1f) << 2) | ||
| 211 | #define BFM_PCM_INTS_RFL(v) BM_PCM_INTS_RFL | ||
| 212 | #define BF_PCM_INTS_RFL_V(e) BF_PCM_INTS_RFL(BV_PCM_INTS_RFL__##e) | ||
| 213 | #define BFM_PCM_INTS_RFL_V(v) BM_PCM_INTS_RFL | ||
| 214 | #define BP_PCM_INTS_RFS 1 | ||
| 215 | #define BM_PCM_INTS_RFS 0x2 | ||
| 216 | #define BF_PCM_INTS_RFS(v) (((v) & 0x1) << 1) | ||
| 217 | #define BFM_PCM_INTS_RFS(v) BM_PCM_INTS_RFS | ||
| 218 | #define BF_PCM_INTS_RFS_V(e) BF_PCM_INTS_RFS(BV_PCM_INTS_RFS__##e) | ||
| 219 | #define BFM_PCM_INTS_RFS_V(v) BM_PCM_INTS_RFS | ||
| 220 | #define BP_PCM_INTS_ROR 0 | ||
| 221 | #define BM_PCM_INTS_ROR 0x1 | ||
| 222 | #define BF_PCM_INTS_ROR(v) (((v) & 0x1) << 0) | ||
| 223 | #define BFM_PCM_INTS_ROR(v) BM_PCM_INTS_ROR | ||
| 224 | #define BF_PCM_INTS_ROR_V(e) BF_PCM_INTS_ROR(BV_PCM_INTS_ROR__##e) | ||
| 225 | #define BFM_PCM_INTS_ROR_V(v) BM_PCM_INTS_ROR | ||
| 226 | |||
| 227 | #define REG_PCM_DIV jz_reg(PCM_DIV) | ||
| 228 | #define JA_PCM_DIV (0xb0071000 + 0x14) | ||
| 229 | #define JT_PCM_DIV JIO_32_RW | ||
| 230 | #define JN_PCM_DIV PCM_DIV | ||
| 231 | #define JI_PCM_DIV | ||
| 232 | #define BP_PCM_DIV_SYNL 11 | ||
| 233 | #define BM_PCM_DIV_SYNL 0x1f800 | ||
| 234 | #define BF_PCM_DIV_SYNL(v) (((v) & 0x3f) << 11) | ||
| 235 | #define BFM_PCM_DIV_SYNL(v) BM_PCM_DIV_SYNL | ||
| 236 | #define BF_PCM_DIV_SYNL_V(e) BF_PCM_DIV_SYNL(BV_PCM_DIV_SYNL__##e) | ||
| 237 | #define BFM_PCM_DIV_SYNL_V(v) BM_PCM_DIV_SYNL | ||
| 238 | #define BP_PCM_DIV_SYNDIV 6 | ||
| 239 | #define BM_PCM_DIV_SYNDIV 0x7c0 | ||
| 240 | #define BF_PCM_DIV_SYNDIV(v) (((v) & 0x1f) << 6) | ||
| 241 | #define BFM_PCM_DIV_SYNDIV(v) BM_PCM_DIV_SYNDIV | ||
| 242 | #define BF_PCM_DIV_SYNDIV_V(e) BF_PCM_DIV_SYNDIV(BV_PCM_DIV_SYNDIV__##e) | ||
| 243 | #define BFM_PCM_DIV_SYNDIV_V(v) BM_PCM_DIV_SYNDIV | ||
| 244 | #define BP_PCM_DIV_CLKDIV 0 | ||
| 245 | #define BM_PCM_DIV_CLKDIV 0x3f | ||
| 246 | #define BF_PCM_DIV_CLKDIV(v) (((v) & 0x3f) << 0) | ||
| 247 | #define BFM_PCM_DIV_CLKDIV(v) BM_PCM_DIV_CLKDIV | ||
| 248 | #define BF_PCM_DIV_CLKDIV_V(e) BF_PCM_DIV_CLKDIV(BV_PCM_DIV_CLKDIV__##e) | ||
| 249 | #define BFM_PCM_DIV_CLKDIV_V(v) BM_PCM_DIV_CLKDIV | ||
| 250 | |||
| 251 | #endif /* __HEADERGEN_PCM_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ssi.h b/firmware/target/mips/ingenic_x1000/x1000/ssi.h new file mode 100644 index 0000000000..731e73c3a6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ssi.h | |||
| @@ -0,0 +1,323 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_SSI_H__ | ||
| 25 | #define __HEADERGEN_SSI_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_SSI_DR jz_reg(SSI_DR) | ||
| 30 | #define JA_SSI_DR (0xb0043000 + 0x0) | ||
| 31 | #define JT_SSI_DR JIO_32_RW | ||
| 32 | #define JN_SSI_DR SSI_DR | ||
| 33 | #define JI_SSI_DR | ||
| 34 | |||
| 35 | #define REG_SSI_CR0 jz_reg(SSI_CR0) | ||
| 36 | #define JA_SSI_CR0 (0xb0043000 + 0x4) | ||
| 37 | #define JT_SSI_CR0 JIO_32_RW | ||
| 38 | #define JN_SSI_CR0 SSI_CR0 | ||
| 39 | #define JI_SSI_CR0 | ||
| 40 | #define BP_SSI_CR0_TENDIAN 18 | ||
| 41 | #define BM_SSI_CR0_TENDIAN 0xc0000 | ||
| 42 | #define BF_SSI_CR0_TENDIAN(v) (((v) & 0x3) << 18) | ||
| 43 | #define BFM_SSI_CR0_TENDIAN(v) BM_SSI_CR0_TENDIAN | ||
| 44 | #define BF_SSI_CR0_TENDIAN_V(e) BF_SSI_CR0_TENDIAN(BV_SSI_CR0_TENDIAN__##e) | ||
| 45 | #define BFM_SSI_CR0_TENDIAN_V(v) BM_SSI_CR0_TENDIAN | ||
| 46 | #define BP_SSI_CR0_RENDIAN 16 | ||
| 47 | #define BM_SSI_CR0_RENDIAN 0x30000 | ||
| 48 | #define BF_SSI_CR0_RENDIAN(v) (((v) & 0x3) << 16) | ||
| 49 | #define BFM_SSI_CR0_RENDIAN(v) BM_SSI_CR0_RENDIAN | ||
| 50 | #define BF_SSI_CR0_RENDIAN_V(e) BF_SSI_CR0_RENDIAN(BV_SSI_CR0_RENDIAN__##e) | ||
| 51 | #define BFM_SSI_CR0_RENDIAN_V(v) BM_SSI_CR0_RENDIAN | ||
| 52 | #define BP_SSI_CR0_SSIE 15 | ||
| 53 | #define BM_SSI_CR0_SSIE 0x8000 | ||
| 54 | #define BF_SSI_CR0_SSIE(v) (((v) & 0x1) << 15) | ||
| 55 | #define BFM_SSI_CR0_SSIE(v) BM_SSI_CR0_SSIE | ||
| 56 | #define BF_SSI_CR0_SSIE_V(e) BF_SSI_CR0_SSIE(BV_SSI_CR0_SSIE__##e) | ||
| 57 | #define BFM_SSI_CR0_SSIE_V(v) BM_SSI_CR0_SSIE | ||
| 58 | #define BP_SSI_CR0_TIE 14 | ||
| 59 | #define BM_SSI_CR0_TIE 0x4000 | ||
| 60 | #define BF_SSI_CR0_TIE(v) (((v) & 0x1) << 14) | ||
| 61 | #define BFM_SSI_CR0_TIE(v) BM_SSI_CR0_TIE | ||
| 62 | #define BF_SSI_CR0_TIE_V(e) BF_SSI_CR0_TIE(BV_SSI_CR0_TIE__##e) | ||
| 63 | #define BFM_SSI_CR0_TIE_V(v) BM_SSI_CR0_TIE | ||
| 64 | #define BP_SSI_CR0_RIE 13 | ||
| 65 | #define BM_SSI_CR0_RIE 0x2000 | ||
| 66 | #define BF_SSI_CR0_RIE(v) (((v) & 0x1) << 13) | ||
| 67 | #define BFM_SSI_CR0_RIE(v) BM_SSI_CR0_RIE | ||
| 68 | #define BF_SSI_CR0_RIE_V(e) BF_SSI_CR0_RIE(BV_SSI_CR0_RIE__##e) | ||
| 69 | #define BFM_SSI_CR0_RIE_V(v) BM_SSI_CR0_RIE | ||
| 70 | #define BP_SSI_CR0_TEIE 12 | ||
| 71 | #define BM_SSI_CR0_TEIE 0x1000 | ||
| 72 | #define BF_SSI_CR0_TEIE(v) (((v) & 0x1) << 12) | ||
| 73 | #define BFM_SSI_CR0_TEIE(v) BM_SSI_CR0_TEIE | ||
| 74 | #define BF_SSI_CR0_TEIE_V(e) BF_SSI_CR0_TEIE(BV_SSI_CR0_TEIE__##e) | ||
| 75 | #define BFM_SSI_CR0_TEIE_V(v) BM_SSI_CR0_TEIE | ||
| 76 | #define BP_SSI_CR0_REIE 11 | ||
| 77 | #define BM_SSI_CR0_REIE 0x800 | ||
| 78 | #define BF_SSI_CR0_REIE(v) (((v) & 0x1) << 11) | ||
| 79 | #define BFM_SSI_CR0_REIE(v) BM_SSI_CR0_REIE | ||
| 80 | #define BF_SSI_CR0_REIE_V(e) BF_SSI_CR0_REIE(BV_SSI_CR0_REIE__##e) | ||
| 81 | #define BFM_SSI_CR0_REIE_V(v) BM_SSI_CR0_REIE | ||
| 82 | #define BP_SSI_CR0_LOOP 10 | ||
| 83 | #define BM_SSI_CR0_LOOP 0x400 | ||
| 84 | #define BF_SSI_CR0_LOOP(v) (((v) & 0x1) << 10) | ||
| 85 | #define BFM_SSI_CR0_LOOP(v) BM_SSI_CR0_LOOP | ||
| 86 | #define BF_SSI_CR0_LOOP_V(e) BF_SSI_CR0_LOOP(BV_SSI_CR0_LOOP__##e) | ||
| 87 | #define BFM_SSI_CR0_LOOP_V(v) BM_SSI_CR0_LOOP | ||
| 88 | #define BP_SSI_CR0_RFINE 9 | ||
| 89 | #define BM_SSI_CR0_RFINE 0x200 | ||
| 90 | #define BF_SSI_CR0_RFINE(v) (((v) & 0x1) << 9) | ||
| 91 | #define BFM_SSI_CR0_RFINE(v) BM_SSI_CR0_RFINE | ||
| 92 | #define BF_SSI_CR0_RFINE_V(e) BF_SSI_CR0_RFINE(BV_SSI_CR0_RFINE__##e) | ||
| 93 | #define BFM_SSI_CR0_RFINE_V(v) BM_SSI_CR0_RFINE | ||
| 94 | #define BP_SSI_CR0_RFINC 8 | ||
| 95 | #define BM_SSI_CR0_RFINC 0x100 | ||
| 96 | #define BF_SSI_CR0_RFINC(v) (((v) & 0x1) << 8) | ||
| 97 | #define BFM_SSI_CR0_RFINC(v) BM_SSI_CR0_RFINC | ||
| 98 | #define BF_SSI_CR0_RFINC_V(e) BF_SSI_CR0_RFINC(BV_SSI_CR0_RFINC__##e) | ||
| 99 | #define BFM_SSI_CR0_RFINC_V(v) BM_SSI_CR0_RFINC | ||
| 100 | #define BP_SSI_CR0_EACLRUN 7 | ||
| 101 | #define BM_SSI_CR0_EACLRUN 0x80 | ||
| 102 | #define BF_SSI_CR0_EACLRUN(v) (((v) & 0x1) << 7) | ||
| 103 | #define BFM_SSI_CR0_EACLRUN(v) BM_SSI_CR0_EACLRUN | ||
| 104 | #define BF_SSI_CR0_EACLRUN_V(e) BF_SSI_CR0_EACLRUN(BV_SSI_CR0_EACLRUN__##e) | ||
| 105 | #define BFM_SSI_CR0_EACLRUN_V(v) BM_SSI_CR0_EACLRUN | ||
| 106 | #define BP_SSI_CR0_FSEL 6 | ||
| 107 | #define BM_SSI_CR0_FSEL 0x40 | ||
| 108 | #define BF_SSI_CR0_FSEL(v) (((v) & 0x1) << 6) | ||
| 109 | #define BFM_SSI_CR0_FSEL(v) BM_SSI_CR0_FSEL | ||
| 110 | #define BF_SSI_CR0_FSEL_V(e) BF_SSI_CR0_FSEL(BV_SSI_CR0_FSEL__##e) | ||
| 111 | #define BFM_SSI_CR0_FSEL_V(v) BM_SSI_CR0_FSEL | ||
| 112 | #define BP_SSI_CR0_VRCNT 4 | ||
| 113 | #define BM_SSI_CR0_VRCNT 0x10 | ||
| 114 | #define BF_SSI_CR0_VRCNT(v) (((v) & 0x1) << 4) | ||
| 115 | #define BFM_SSI_CR0_VRCNT(v) BM_SSI_CR0_VRCNT | ||
| 116 | #define BF_SSI_CR0_VRCNT_V(e) BF_SSI_CR0_VRCNT(BV_SSI_CR0_VRCNT__##e) | ||
| 117 | #define BFM_SSI_CR0_VRCNT_V(v) BM_SSI_CR0_VRCNT | ||
| 118 | #define BP_SSI_CR0_TFMODE 3 | ||
| 119 | #define BM_SSI_CR0_TFMODE 0x8 | ||
| 120 | #define BF_SSI_CR0_TFMODE(v) (((v) & 0x1) << 3) | ||
| 121 | #define BFM_SSI_CR0_TFMODE(v) BM_SSI_CR0_TFMODE | ||
| 122 | #define BF_SSI_CR0_TFMODE_V(e) BF_SSI_CR0_TFMODE(BV_SSI_CR0_TFMODE__##e) | ||
| 123 | #define BFM_SSI_CR0_TFMODE_V(v) BM_SSI_CR0_TFMODE | ||
| 124 | #define BP_SSI_CR0_TFLUSH 2 | ||
| 125 | #define BM_SSI_CR0_TFLUSH 0x4 | ||
| 126 | #define BF_SSI_CR0_TFLUSH(v) (((v) & 0x1) << 2) | ||
| 127 | #define BFM_SSI_CR0_TFLUSH(v) BM_SSI_CR0_TFLUSH | ||
| 128 | #define BF_SSI_CR0_TFLUSH_V(e) BF_SSI_CR0_TFLUSH(BV_SSI_CR0_TFLUSH__##e) | ||
| 129 | #define BFM_SSI_CR0_TFLUSH_V(v) BM_SSI_CR0_TFLUSH | ||
| 130 | #define BP_SSI_CR0_RFLUSH 1 | ||
| 131 | #define BM_SSI_CR0_RFLUSH 0x2 | ||
| 132 | #define BF_SSI_CR0_RFLUSH(v) (((v) & 0x1) << 1) | ||
| 133 | #define BFM_SSI_CR0_RFLUSH(v) BM_SSI_CR0_RFLUSH | ||
| 134 | #define BF_SSI_CR0_RFLUSH_V(e) BF_SSI_CR0_RFLUSH(BV_SSI_CR0_RFLUSH__##e) | ||
| 135 | #define BFM_SSI_CR0_RFLUSH_V(v) BM_SSI_CR0_RFLUSH | ||
| 136 | #define BP_SSI_CR0_DISREV 0 | ||
| 137 | #define BM_SSI_CR0_DISREV 0x1 | ||
| 138 | #define BF_SSI_CR0_DISREV(v) (((v) & 0x1) << 0) | ||
| 139 | #define BFM_SSI_CR0_DISREV(v) BM_SSI_CR0_DISREV | ||
| 140 | #define BF_SSI_CR0_DISREV_V(e) BF_SSI_CR0_DISREV(BV_SSI_CR0_DISREV__##e) | ||
| 141 | #define BFM_SSI_CR0_DISREV_V(v) BM_SSI_CR0_DISREV | ||
| 142 | |||
| 143 | #define REG_SSI_CR1 jz_reg(SSI_CR1) | ||
| 144 | #define JA_SSI_CR1 (0xb0043000 + 0x8) | ||
| 145 | #define JT_SSI_CR1 JIO_32_RW | ||
| 146 | #define JN_SSI_CR1 SSI_CR1 | ||
| 147 | #define JI_SSI_CR1 | ||
| 148 | #define BP_SSI_CR1_FRMHL 30 | ||
| 149 | #define BM_SSI_CR1_FRMHL 0xc0000000 | ||
| 150 | #define BF_SSI_CR1_FRMHL(v) (((v) & 0x3) << 30) | ||
| 151 | #define BFM_SSI_CR1_FRMHL(v) BM_SSI_CR1_FRMHL | ||
| 152 | #define BF_SSI_CR1_FRMHL_V(e) BF_SSI_CR1_FRMHL(BV_SSI_CR1_FRMHL__##e) | ||
| 153 | #define BFM_SSI_CR1_FRMHL_V(v) BM_SSI_CR1_FRMHL | ||
| 154 | #define BP_SSI_CR1_TFVCK 28 | ||
| 155 | #define BM_SSI_CR1_TFVCK 0x30000000 | ||
| 156 | #define BF_SSI_CR1_TFVCK(v) (((v) & 0x3) << 28) | ||
| 157 | #define BFM_SSI_CR1_TFVCK(v) BM_SSI_CR1_TFVCK | ||
| 158 | #define BF_SSI_CR1_TFVCK_V(e) BF_SSI_CR1_TFVCK(BV_SSI_CR1_TFVCK__##e) | ||
| 159 | #define BFM_SSI_CR1_TFVCK_V(v) BM_SSI_CR1_TFVCK | ||
| 160 | #define BP_SSI_CR1_TCKFI 26 | ||
| 161 | #define BM_SSI_CR1_TCKFI 0xc000000 | ||
| 162 | #define BF_SSI_CR1_TCKFI(v) (((v) & 0x3) << 26) | ||
| 163 | #define BFM_SSI_CR1_TCKFI(v) BM_SSI_CR1_TCKFI | ||
| 164 | #define BF_SSI_CR1_TCKFI_V(e) BF_SSI_CR1_TCKFI(BV_SSI_CR1_TCKFI__##e) | ||
| 165 | #define BFM_SSI_CR1_TCKFI_V(v) BM_SSI_CR1_TCKFI | ||
| 166 | #define BP_SSI_CR1_FMAT 20 | ||
| 167 | #define BM_SSI_CR1_FMAT 0x300000 | ||
| 168 | #define BF_SSI_CR1_FMAT(v) (((v) & 0x3) << 20) | ||
| 169 | #define BFM_SSI_CR1_FMAT(v) BM_SSI_CR1_FMAT | ||
| 170 | #define BF_SSI_CR1_FMAT_V(e) BF_SSI_CR1_FMAT(BV_SSI_CR1_FMAT__##e) | ||
| 171 | #define BFM_SSI_CR1_FMAT_V(v) BM_SSI_CR1_FMAT | ||
| 172 | #define BP_SSI_CR1_TTRG 16 | ||
| 173 | #define BM_SSI_CR1_TTRG 0xf0000 | ||
| 174 | #define BF_SSI_CR1_TTRG(v) (((v) & 0xf) << 16) | ||
| 175 | #define BFM_SSI_CR1_TTRG(v) BM_SSI_CR1_TTRG | ||
| 176 | #define BF_SSI_CR1_TTRG_V(e) BF_SSI_CR1_TTRG(BV_SSI_CR1_TTRG__##e) | ||
| 177 | #define BFM_SSI_CR1_TTRG_V(v) BM_SSI_CR1_TTRG | ||
| 178 | #define BP_SSI_CR1_MCOM 12 | ||
| 179 | #define BM_SSI_CR1_MCOM 0xf000 | ||
| 180 | #define BF_SSI_CR1_MCOM(v) (((v) & 0xf) << 12) | ||
| 181 | #define BFM_SSI_CR1_MCOM(v) BM_SSI_CR1_MCOM | ||
| 182 | #define BF_SSI_CR1_MCOM_V(e) BF_SSI_CR1_MCOM(BV_SSI_CR1_MCOM__##e) | ||
| 183 | #define BFM_SSI_CR1_MCOM_V(v) BM_SSI_CR1_MCOM | ||
| 184 | #define BP_SSI_CR1_RTRG 8 | ||
| 185 | #define BM_SSI_CR1_RTRG 0xf00 | ||
| 186 | #define BF_SSI_CR1_RTRG(v) (((v) & 0xf) << 8) | ||
| 187 | #define BFM_SSI_CR1_RTRG(v) BM_SSI_CR1_RTRG | ||
| 188 | #define BF_SSI_CR1_RTRG_V(e) BF_SSI_CR1_RTRG(BV_SSI_CR1_RTRG__##e) | ||
| 189 | #define BFM_SSI_CR1_RTRG_V(v) BM_SSI_CR1_RTRG | ||
| 190 | #define BP_SSI_CR1_FLEN 3 | ||
| 191 | #define BM_SSI_CR1_FLEN 0xf8 | ||
| 192 | #define BF_SSI_CR1_FLEN(v) (((v) & 0x1f) << 3) | ||
| 193 | #define BFM_SSI_CR1_FLEN(v) BM_SSI_CR1_FLEN | ||
| 194 | #define BF_SSI_CR1_FLEN_V(e) BF_SSI_CR1_FLEN(BV_SSI_CR1_FLEN__##e) | ||
| 195 | #define BFM_SSI_CR1_FLEN_V(v) BM_SSI_CR1_FLEN | ||
| 196 | #define BP_SSI_CR1_ITFRM 24 | ||
| 197 | #define BM_SSI_CR1_ITFRM 0x1000000 | ||
| 198 | #define BF_SSI_CR1_ITFRM(v) (((v) & 0x1) << 24) | ||
| 199 | #define BFM_SSI_CR1_ITFRM(v) BM_SSI_CR1_ITFRM | ||
| 200 | #define BF_SSI_CR1_ITFRM_V(e) BF_SSI_CR1_ITFRM(BV_SSI_CR1_ITFRM__##e) | ||
| 201 | #define BFM_SSI_CR1_ITFRM_V(v) BM_SSI_CR1_ITFRM | ||
| 202 | #define BP_SSI_CR1_UNFIN 23 | ||
| 203 | #define BM_SSI_CR1_UNFIN 0x800000 | ||
| 204 | #define BF_SSI_CR1_UNFIN(v) (((v) & 0x1) << 23) | ||
| 205 | #define BFM_SSI_CR1_UNFIN(v) BM_SSI_CR1_UNFIN | ||
| 206 | #define BF_SSI_CR1_UNFIN_V(e) BF_SSI_CR1_UNFIN(BV_SSI_CR1_UNFIN__##e) | ||
| 207 | #define BFM_SSI_CR1_UNFIN_V(v) BM_SSI_CR1_UNFIN | ||
| 208 | #define BP_SSI_CR1_PHA 1 | ||
| 209 | #define BM_SSI_CR1_PHA 0x2 | ||
| 210 | #define BF_SSI_CR1_PHA(v) (((v) & 0x1) << 1) | ||
| 211 | #define BFM_SSI_CR1_PHA(v) BM_SSI_CR1_PHA | ||
| 212 | #define BF_SSI_CR1_PHA_V(e) BF_SSI_CR1_PHA(BV_SSI_CR1_PHA__##e) | ||
| 213 | #define BFM_SSI_CR1_PHA_V(v) BM_SSI_CR1_PHA | ||
| 214 | #define BP_SSI_CR1_POL 0 | ||
| 215 | #define BM_SSI_CR1_POL 0x1 | ||
| 216 | #define BF_SSI_CR1_POL(v) (((v) & 0x1) << 0) | ||
| 217 | #define BFM_SSI_CR1_POL(v) BM_SSI_CR1_POL | ||
| 218 | #define BF_SSI_CR1_POL_V(e) BF_SSI_CR1_POL(BV_SSI_CR1_POL__##e) | ||
| 219 | #define BFM_SSI_CR1_POL_V(v) BM_SSI_CR1_POL | ||
| 220 | |||
| 221 | #define REG_SSI_SR jz_reg(SSI_SR) | ||
| 222 | #define JA_SSI_SR (0xb0043000 + 0xc) | ||
| 223 | #define JT_SSI_SR JIO_32_RW | ||
| 224 | #define JN_SSI_SR SSI_SR | ||
| 225 | #define JI_SSI_SR | ||
| 226 | #define BP_SSI_SR_TFIFO_NUM 16 | ||
| 227 | #define BM_SSI_SR_TFIFO_NUM 0x1ff0000 | ||
| 228 | #define BF_SSI_SR_TFIFO_NUM(v) (((v) & 0x1ff) << 16) | ||
| 229 | #define BFM_SSI_SR_TFIFO_NUM(v) BM_SSI_SR_TFIFO_NUM | ||
| 230 | #define BF_SSI_SR_TFIFO_NUM_V(e) BF_SSI_SR_TFIFO_NUM(BV_SSI_SR_TFIFO_NUM__##e) | ||
| 231 | #define BFM_SSI_SR_TFIFO_NUM_V(v) BM_SSI_SR_TFIFO_NUM | ||
| 232 | #define BP_SSI_SR_RFIFO_NUM 8 | ||
| 233 | #define BM_SSI_SR_RFIFO_NUM 0xff00 | ||
| 234 | #define BF_SSI_SR_RFIFO_NUM(v) (((v) & 0xff) << 8) | ||
| 235 | #define BFM_SSI_SR_RFIFO_NUM(v) BM_SSI_SR_RFIFO_NUM | ||
| 236 | #define BF_SSI_SR_RFIFO_NUM_V(e) BF_SSI_SR_RFIFO_NUM(BV_SSI_SR_RFIFO_NUM__##e) | ||
| 237 | #define BFM_SSI_SR_RFIFO_NUM_V(v) BM_SSI_SR_RFIFO_NUM | ||
| 238 | #define BP_SSI_SR_END 7 | ||
| 239 | #define BM_SSI_SR_END 0x80 | ||
| 240 | #define BF_SSI_SR_END(v) (((v) & 0x1) << 7) | ||
| 241 | #define BFM_SSI_SR_END(v) BM_SSI_SR_END | ||
| 242 | #define BF_SSI_SR_END_V(e) BF_SSI_SR_END(BV_SSI_SR_END__##e) | ||
| 243 | #define BFM_SSI_SR_END_V(v) BM_SSI_SR_END | ||
| 244 | #define BP_SSI_SR_BUSY 6 | ||
| 245 | #define BM_SSI_SR_BUSY 0x40 | ||
| 246 | #define BF_SSI_SR_BUSY(v) (((v) & 0x1) << 6) | ||
| 247 | #define BFM_SSI_SR_BUSY(v) BM_SSI_SR_BUSY | ||
| 248 | #define BF_SSI_SR_BUSY_V(e) BF_SSI_SR_BUSY(BV_SSI_SR_BUSY__##e) | ||
| 249 | #define BFM_SSI_SR_BUSY_V(v) BM_SSI_SR_BUSY | ||
| 250 | #define BP_SSI_SR_TFF 5 | ||
| 251 | #define BM_SSI_SR_TFF 0x20 | ||
| 252 | #define BF_SSI_SR_TFF(v) (((v) & 0x1) << 5) | ||
| 253 | #define BFM_SSI_SR_TFF(v) BM_SSI_SR_TFF | ||
| 254 | #define BF_SSI_SR_TFF_V(e) BF_SSI_SR_TFF(BV_SSI_SR_TFF__##e) | ||
| 255 | #define BFM_SSI_SR_TFF_V(v) BM_SSI_SR_TFF | ||
| 256 | #define BP_SSI_SR_RFE 4 | ||
| 257 | #define BM_SSI_SR_RFE 0x10 | ||
| 258 | #define BF_SSI_SR_RFE(v) (((v) & 0x1) << 4) | ||
| 259 | #define BFM_SSI_SR_RFE(v) BM_SSI_SR_RFE | ||
| 260 | #define BF_SSI_SR_RFE_V(e) BF_SSI_SR_RFE(BV_SSI_SR_RFE__##e) | ||
| 261 | #define BFM_SSI_SR_RFE_V(v) BM_SSI_SR_RFE | ||
| 262 | #define BP_SSI_SR_TFHE 3 | ||
| 263 | #define BM_SSI_SR_TFHE 0x8 | ||
| 264 | #define BF_SSI_SR_TFHE(v) (((v) & 0x1) << 3) | ||
| 265 | #define BFM_SSI_SR_TFHE(v) BM_SSI_SR_TFHE | ||
| 266 | #define BF_SSI_SR_TFHE_V(e) BF_SSI_SR_TFHE(BV_SSI_SR_TFHE__##e) | ||
| 267 | #define BFM_SSI_SR_TFHE_V(v) BM_SSI_SR_TFHE | ||
| 268 | #define BP_SSI_SR_RFHF 2 | ||
| 269 | #define BM_SSI_SR_RFHF 0x4 | ||
| 270 | #define BF_SSI_SR_RFHF(v) (((v) & 0x1) << 2) | ||
| 271 | #define BFM_SSI_SR_RFHF(v) BM_SSI_SR_RFHF | ||
| 272 | #define BF_SSI_SR_RFHF_V(e) BF_SSI_SR_RFHF(BV_SSI_SR_RFHF__##e) | ||
| 273 | #define BFM_SSI_SR_RFHF_V(v) BM_SSI_SR_RFHF | ||
| 274 | #define BP_SSI_SR_UNDR 1 | ||
| 275 | #define BM_SSI_SR_UNDR 0x2 | ||
| 276 | #define BF_SSI_SR_UNDR(v) (((v) & 0x1) << 1) | ||
| 277 | #define BFM_SSI_SR_UNDR(v) BM_SSI_SR_UNDR | ||
| 278 | #define BF_SSI_SR_UNDR_V(e) BF_SSI_SR_UNDR(BV_SSI_SR_UNDR__##e) | ||
| 279 | #define BFM_SSI_SR_UNDR_V(v) BM_SSI_SR_UNDR | ||
| 280 | #define BP_SSI_SR_OVER 0 | ||
| 281 | #define BM_SSI_SR_OVER 0x1 | ||
| 282 | #define BF_SSI_SR_OVER(v) (((v) & 0x1) << 0) | ||
| 283 | #define BFM_SSI_SR_OVER(v) BM_SSI_SR_OVER | ||
| 284 | #define BF_SSI_SR_OVER_V(e) BF_SSI_SR_OVER(BV_SSI_SR_OVER__##e) | ||
| 285 | #define BFM_SSI_SR_OVER_V(v) BM_SSI_SR_OVER | ||
| 286 | |||
| 287 | #define REG_SSI_ITR jz_reg(SSI_ITR) | ||
| 288 | #define JA_SSI_ITR (0xb0043000 + 0x10) | ||
| 289 | #define JT_SSI_ITR JIO_32_RW | ||
| 290 | #define JN_SSI_ITR SSI_ITR | ||
| 291 | #define JI_SSI_ITR | ||
| 292 | #define BP_SSI_ITR_IVLTM 0 | ||
| 293 | #define BM_SSI_ITR_IVLTM 0x7fff | ||
| 294 | #define BF_SSI_ITR_IVLTM(v) (((v) & 0x7fff) << 0) | ||
| 295 | #define BFM_SSI_ITR_IVLTM(v) BM_SSI_ITR_IVLTM | ||
| 296 | #define BF_SSI_ITR_IVLTM_V(e) BF_SSI_ITR_IVLTM(BV_SSI_ITR_IVLTM__##e) | ||
| 297 | #define BFM_SSI_ITR_IVLTM_V(v) BM_SSI_ITR_IVLTM | ||
| 298 | #define BP_SSI_ITR_CNTCLK 15 | ||
| 299 | #define BM_SSI_ITR_CNTCLK 0x8000 | ||
| 300 | #define BF_SSI_ITR_CNTCLK(v) (((v) & 0x1) << 15) | ||
| 301 | #define BFM_SSI_ITR_CNTCLK(v) BM_SSI_ITR_CNTCLK | ||
| 302 | #define BF_SSI_ITR_CNTCLK_V(e) BF_SSI_ITR_CNTCLK(BV_SSI_ITR_CNTCLK__##e) | ||
| 303 | #define BFM_SSI_ITR_CNTCLK_V(v) BM_SSI_ITR_CNTCLK | ||
| 304 | |||
| 305 | #define REG_SSI_ICR jz_reg(SSI_ICR) | ||
| 306 | #define JA_SSI_ICR (0xb0043000 + 0x14) | ||
| 307 | #define JT_SSI_ICR JIO_32_RW | ||
| 308 | #define JN_SSI_ICR SSI_ICR | ||
| 309 | #define JI_SSI_ICR | ||
| 310 | |||
| 311 | #define REG_SSI_GR jz_reg(SSI_GR) | ||
| 312 | #define JA_SSI_GR (0xb0043000 + 0x18) | ||
| 313 | #define JT_SSI_GR JIO_32_RW | ||
| 314 | #define JN_SSI_GR SSI_GR | ||
| 315 | #define JI_SSI_GR | ||
| 316 | |||
| 317 | #define REG_SSI_RCNT jz_reg(SSI_RCNT) | ||
| 318 | #define JA_SSI_RCNT (0xb0043000 + 0x1c) | ||
| 319 | #define JT_SSI_RCNT JIO_32_RW | ||
| 320 | #define JN_SSI_RCNT SSI_RCNT | ||
| 321 | #define JI_SSI_RCNT | ||
| 322 | |||
| 323 | #endif /* __HEADERGEN_SSI_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/uart.h b/firmware/target/mips/ingenic_x1000/x1000/uart.h new file mode 100644 index 0000000000..6b42740bb7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/uart.h | |||
| @@ -0,0 +1,390 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_UART_H__ | ||
| 25 | #define __HEADERGEN_UART_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_UART_URBR(_n1) jz_reg(UART_URBR(_n1)) | ||
| 30 | #define JA_UART_URBR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) | ||
| 31 | #define JT_UART_URBR(_n1) JIO_32_RW | ||
| 32 | #define JN_UART_URBR(_n1) UART_URBR | ||
| 33 | #define JI_UART_URBR(_n1) (_n1) | ||
| 34 | |||
| 35 | #define REG_UART_UTHR(_n1) jz_reg(UART_UTHR(_n1)) | ||
| 36 | #define JA_UART_UTHR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) | ||
| 37 | #define JT_UART_UTHR(_n1) JIO_32_RW | ||
| 38 | #define JN_UART_UTHR(_n1) UART_UTHR | ||
| 39 | #define JI_UART_UTHR(_n1) (_n1) | ||
| 40 | |||
| 41 | #define REG_UART_UDLLR(_n1) jz_reg(UART_UDLLR(_n1)) | ||
| 42 | #define JA_UART_UDLLR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) | ||
| 43 | #define JT_UART_UDLLR(_n1) JIO_32_RW | ||
| 44 | #define JN_UART_UDLLR(_n1) UART_UDLLR | ||
| 45 | #define JI_UART_UDLLR(_n1) (_n1) | ||
| 46 | |||
| 47 | #define REG_UART_UDLHR(_n1) jz_reg(UART_UDLHR(_n1)) | ||
| 48 | #define JA_UART_UDLHR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x4) | ||
| 49 | #define JT_UART_UDLHR(_n1) JIO_32_RW | ||
| 50 | #define JN_UART_UDLHR(_n1) UART_UDLHR | ||
| 51 | #define JI_UART_UDLHR(_n1) (_n1) | ||
| 52 | |||
| 53 | #define REG_UART_UIER(_n1) jz_reg(UART_UIER(_n1)) | ||
| 54 | #define JA_UART_UIER(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x4) | ||
| 55 | #define JT_UART_UIER(_n1) JIO_32_RW | ||
| 56 | #define JN_UART_UIER(_n1) UART_UIER | ||
| 57 | #define JI_UART_UIER(_n1) (_n1) | ||
| 58 | #define BP_UART_UIER_RTOIE 4 | ||
| 59 | #define BM_UART_UIER_RTOIE 0x10 | ||
| 60 | #define BF_UART_UIER_RTOIE(v) (((v) & 0x1) << 4) | ||
| 61 | #define BFM_UART_UIER_RTOIE(v) BM_UART_UIER_RTOIE | ||
| 62 | #define BF_UART_UIER_RTOIE_V(e) BF_UART_UIER_RTOIE(BV_UART_UIER_RTOIE__##e) | ||
| 63 | #define BFM_UART_UIER_RTOIE_V(v) BM_UART_UIER_RTOIE | ||
| 64 | #define BP_UART_UIER_MSIE 3 | ||
| 65 | #define BM_UART_UIER_MSIE 0x8 | ||
| 66 | #define BF_UART_UIER_MSIE(v) (((v) & 0x1) << 3) | ||
| 67 | #define BFM_UART_UIER_MSIE(v) BM_UART_UIER_MSIE | ||
| 68 | #define BF_UART_UIER_MSIE_V(e) BF_UART_UIER_MSIE(BV_UART_UIER_MSIE__##e) | ||
| 69 | #define BFM_UART_UIER_MSIE_V(v) BM_UART_UIER_MSIE | ||
| 70 | #define BP_UART_UIER_RLSIE 2 | ||
| 71 | #define BM_UART_UIER_RLSIE 0x4 | ||
| 72 | #define BF_UART_UIER_RLSIE(v) (((v) & 0x1) << 2) | ||
| 73 | #define BFM_UART_UIER_RLSIE(v) BM_UART_UIER_RLSIE | ||
| 74 | #define BF_UART_UIER_RLSIE_V(e) BF_UART_UIER_RLSIE(BV_UART_UIER_RLSIE__##e) | ||
| 75 | #define BFM_UART_UIER_RLSIE_V(v) BM_UART_UIER_RLSIE | ||
| 76 | #define BP_UART_UIER_TDRIE 1 | ||
| 77 | #define BM_UART_UIER_TDRIE 0x2 | ||
| 78 | #define BF_UART_UIER_TDRIE(v) (((v) & 0x1) << 1) | ||
| 79 | #define BFM_UART_UIER_TDRIE(v) BM_UART_UIER_TDRIE | ||
| 80 | #define BF_UART_UIER_TDRIE_V(e) BF_UART_UIER_TDRIE(BV_UART_UIER_TDRIE__##e) | ||
| 81 | #define BFM_UART_UIER_TDRIE_V(v) BM_UART_UIER_TDRIE | ||
| 82 | #define BP_UART_UIER_RDRIE 0 | ||
| 83 | #define BM_UART_UIER_RDRIE 0x1 | ||
| 84 | #define BF_UART_UIER_RDRIE(v) (((v) & 0x1) << 0) | ||
| 85 | #define BFM_UART_UIER_RDRIE(v) BM_UART_UIER_RDRIE | ||
| 86 | #define BF_UART_UIER_RDRIE_V(e) BF_UART_UIER_RDRIE(BV_UART_UIER_RDRIE__##e) | ||
| 87 | #define BFM_UART_UIER_RDRIE_V(v) BM_UART_UIER_RDRIE | ||
| 88 | |||
| 89 | #define REG_UART_UIIR(_n1) jz_reg(UART_UIIR(_n1)) | ||
| 90 | #define JA_UART_UIIR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x8) | ||
| 91 | #define JT_UART_UIIR(_n1) JIO_32_RW | ||
| 92 | #define JN_UART_UIIR(_n1) UART_UIIR | ||
| 93 | #define JI_UART_UIIR(_n1) (_n1) | ||
| 94 | #define BP_UART_UIIR_FFMSEL 6 | ||
| 95 | #define BM_UART_UIIR_FFMSEL 0xc0 | ||
| 96 | #define BV_UART_UIIR_FFMSEL__NON_FIFO_MODE 0x0 | ||
| 97 | #define BV_UART_UIIR_FFMSEL__FIFO_MODE 0x1 | ||
| 98 | #define BF_UART_UIIR_FFMSEL(v) (((v) & 0x3) << 6) | ||
| 99 | #define BFM_UART_UIIR_FFMSEL(v) BM_UART_UIIR_FFMSEL | ||
| 100 | #define BF_UART_UIIR_FFMSEL_V(e) BF_UART_UIIR_FFMSEL(BV_UART_UIIR_FFMSEL__##e) | ||
| 101 | #define BFM_UART_UIIR_FFMSEL_V(v) BM_UART_UIIR_FFMSEL | ||
| 102 | #define BP_UART_UIIR_INID 1 | ||
| 103 | #define BM_UART_UIIR_INID 0xe | ||
| 104 | #define BV_UART_UIIR_INID__MODEM_STATUS 0x0 | ||
| 105 | #define BV_UART_UIIR_INID__TRANSMIT_DATA_REQ 0x1 | ||
| 106 | #define BV_UART_UIIR_INID__RECEIVE_DATA_READY 0x2 | ||
| 107 | #define BV_UART_UIIR_INID__RECEIVE_LINE_STATUS 0x3 | ||
| 108 | #define BV_UART_UIIR_INID__RECEIVE_TIME_OUT 0x6 | ||
| 109 | #define BF_UART_UIIR_INID(v) (((v) & 0x7) << 1) | ||
| 110 | #define BFM_UART_UIIR_INID(v) BM_UART_UIIR_INID | ||
| 111 | #define BF_UART_UIIR_INID_V(e) BF_UART_UIIR_INID(BV_UART_UIIR_INID__##e) | ||
| 112 | #define BFM_UART_UIIR_INID_V(v) BM_UART_UIIR_INID | ||
| 113 | #define BP_UART_UIIR_INPEND 0 | ||
| 114 | #define BM_UART_UIIR_INPEND 0x1 | ||
| 115 | #define BF_UART_UIIR_INPEND(v) (((v) & 0x1) << 0) | ||
| 116 | #define BFM_UART_UIIR_INPEND(v) BM_UART_UIIR_INPEND | ||
| 117 | #define BF_UART_UIIR_INPEND_V(e) BF_UART_UIIR_INPEND(BV_UART_UIIR_INPEND__##e) | ||
| 118 | #define BFM_UART_UIIR_INPEND_V(v) BM_UART_UIIR_INPEND | ||
| 119 | |||
| 120 | #define REG_UART_UFCR(_n1) jz_reg(UART_UFCR(_n1)) | ||
| 121 | #define JA_UART_UFCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x8) | ||
| 122 | #define JT_UART_UFCR(_n1) JIO_32_RW | ||
| 123 | #define JN_UART_UFCR(_n1) UART_UFCR | ||
| 124 | #define JI_UART_UFCR(_n1) (_n1) | ||
| 125 | #define BP_UART_UFCR_RDTR 6 | ||
| 126 | #define BM_UART_UFCR_RDTR 0xc0 | ||
| 127 | #define BV_UART_UFCR_RDTR__1BYTE 0x0 | ||
| 128 | #define BV_UART_UFCR_RDTR__16BYTE 0x1 | ||
| 129 | #define BV_UART_UFCR_RDTR__32BYTE 0x2 | ||
| 130 | #define BV_UART_UFCR_RDTR__60BYTE 0x3 | ||
| 131 | #define BF_UART_UFCR_RDTR(v) (((v) & 0x3) << 6) | ||
| 132 | #define BFM_UART_UFCR_RDTR(v) BM_UART_UFCR_RDTR | ||
| 133 | #define BF_UART_UFCR_RDTR_V(e) BF_UART_UFCR_RDTR(BV_UART_UFCR_RDTR__##e) | ||
| 134 | #define BFM_UART_UFCR_RDTR_V(v) BM_UART_UFCR_RDTR | ||
| 135 | #define BP_UART_UFCR_UME 4 | ||
| 136 | #define BM_UART_UFCR_UME 0x10 | ||
| 137 | #define BF_UART_UFCR_UME(v) (((v) & 0x1) << 4) | ||
| 138 | #define BFM_UART_UFCR_UME(v) BM_UART_UFCR_UME | ||
| 139 | #define BF_UART_UFCR_UME_V(e) BF_UART_UFCR_UME(BV_UART_UFCR_UME__##e) | ||
| 140 | #define BFM_UART_UFCR_UME_V(v) BM_UART_UFCR_UME | ||
| 141 | #define BP_UART_UFCR_DME 3 | ||
| 142 | #define BM_UART_UFCR_DME 0x8 | ||
| 143 | #define BF_UART_UFCR_DME(v) (((v) & 0x1) << 3) | ||
| 144 | #define BFM_UART_UFCR_DME(v) BM_UART_UFCR_DME | ||
| 145 | #define BF_UART_UFCR_DME_V(e) BF_UART_UFCR_DME(BV_UART_UFCR_DME__##e) | ||
| 146 | #define BFM_UART_UFCR_DME_V(v) BM_UART_UFCR_DME | ||
| 147 | #define BP_UART_UFCR_TFRT 2 | ||
| 148 | #define BM_UART_UFCR_TFRT 0x4 | ||
| 149 | #define BF_UART_UFCR_TFRT(v) (((v) & 0x1) << 2) | ||
| 150 | #define BFM_UART_UFCR_TFRT(v) BM_UART_UFCR_TFRT | ||
| 151 | #define BF_UART_UFCR_TFRT_V(e) BF_UART_UFCR_TFRT(BV_UART_UFCR_TFRT__##e) | ||
| 152 | #define BFM_UART_UFCR_TFRT_V(v) BM_UART_UFCR_TFRT | ||
| 153 | #define BP_UART_UFCR_RFRT 1 | ||
| 154 | #define BM_UART_UFCR_RFRT 0x2 | ||
| 155 | #define BF_UART_UFCR_RFRT(v) (((v) & 0x1) << 1) | ||
| 156 | #define BFM_UART_UFCR_RFRT(v) BM_UART_UFCR_RFRT | ||
| 157 | #define BF_UART_UFCR_RFRT_V(e) BF_UART_UFCR_RFRT(BV_UART_UFCR_RFRT__##e) | ||
| 158 | #define BFM_UART_UFCR_RFRT_V(v) BM_UART_UFCR_RFRT | ||
| 159 | #define BP_UART_UFCR_FME 0 | ||
| 160 | #define BM_UART_UFCR_FME 0x1 | ||
| 161 | #define BF_UART_UFCR_FME(v) (((v) & 0x1) << 0) | ||
| 162 | #define BFM_UART_UFCR_FME(v) BM_UART_UFCR_FME | ||
| 163 | #define BF_UART_UFCR_FME_V(e) BF_UART_UFCR_FME(BV_UART_UFCR_FME__##e) | ||
| 164 | #define BFM_UART_UFCR_FME_V(v) BM_UART_UFCR_FME | ||
| 165 | |||
| 166 | #define REG_UART_ULCR(_n1) jz_reg(UART_ULCR(_n1)) | ||
| 167 | #define JA_UART_ULCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0xc) | ||
| 168 | #define JT_UART_ULCR(_n1) JIO_32_RW | ||
| 169 | #define JN_UART_ULCR(_n1) UART_ULCR | ||
| 170 | #define JI_UART_ULCR(_n1) (_n1) | ||
| 171 | #define BP_UART_ULCR_WLS 0 | ||
| 172 | #define BM_UART_ULCR_WLS 0x3 | ||
| 173 | #define BV_UART_ULCR_WLS__5BITS 0x0 | ||
| 174 | #define BV_UART_ULCR_WLS__6BITS 0x1 | ||
| 175 | #define BV_UART_ULCR_WLS__7BITS 0x2 | ||
| 176 | #define BV_UART_ULCR_WLS__8BITS 0x3 | ||
| 177 | #define BF_UART_ULCR_WLS(v) (((v) & 0x3) << 0) | ||
| 178 | #define BFM_UART_ULCR_WLS(v) BM_UART_ULCR_WLS | ||
| 179 | #define BF_UART_ULCR_WLS_V(e) BF_UART_ULCR_WLS(BV_UART_ULCR_WLS__##e) | ||
| 180 | #define BFM_UART_ULCR_WLS_V(v) BM_UART_ULCR_WLS | ||
| 181 | #define BP_UART_ULCR_DLAB 7 | ||
| 182 | #define BM_UART_ULCR_DLAB 0x80 | ||
| 183 | #define BF_UART_ULCR_DLAB(v) (((v) & 0x1) << 7) | ||
| 184 | #define BFM_UART_ULCR_DLAB(v) BM_UART_ULCR_DLAB | ||
| 185 | #define BF_UART_ULCR_DLAB_V(e) BF_UART_ULCR_DLAB(BV_UART_ULCR_DLAB__##e) | ||
| 186 | #define BFM_UART_ULCR_DLAB_V(v) BM_UART_ULCR_DLAB | ||
| 187 | #define BP_UART_ULCR_SBK 6 | ||
| 188 | #define BM_UART_ULCR_SBK 0x40 | ||
| 189 | #define BF_UART_ULCR_SBK(v) (((v) & 0x1) << 6) | ||
| 190 | #define BFM_UART_ULCR_SBK(v) BM_UART_ULCR_SBK | ||
| 191 | #define BF_UART_ULCR_SBK_V(e) BF_UART_ULCR_SBK(BV_UART_ULCR_SBK__##e) | ||
| 192 | #define BFM_UART_ULCR_SBK_V(v) BM_UART_ULCR_SBK | ||
| 193 | #define BP_UART_ULCR_STPAR 5 | ||
| 194 | #define BM_UART_ULCR_STPAR 0x20 | ||
| 195 | #define BF_UART_ULCR_STPAR(v) (((v) & 0x1) << 5) | ||
| 196 | #define BFM_UART_ULCR_STPAR(v) BM_UART_ULCR_STPAR | ||
| 197 | #define BF_UART_ULCR_STPAR_V(e) BF_UART_ULCR_STPAR(BV_UART_ULCR_STPAR__##e) | ||
| 198 | #define BFM_UART_ULCR_STPAR_V(v) BM_UART_ULCR_STPAR | ||
| 199 | #define BP_UART_ULCR_PARM 4 | ||
| 200 | #define BM_UART_ULCR_PARM 0x10 | ||
| 201 | #define BV_UART_ULCR_PARM__ODD 0x0 | ||
| 202 | #define BV_UART_ULCR_PARM__EVEN 0x1 | ||
| 203 | #define BF_UART_ULCR_PARM(v) (((v) & 0x1) << 4) | ||
| 204 | #define BFM_UART_ULCR_PARM(v) BM_UART_ULCR_PARM | ||
| 205 | #define BF_UART_ULCR_PARM_V(e) BF_UART_ULCR_PARM(BV_UART_ULCR_PARM__##e) | ||
| 206 | #define BFM_UART_ULCR_PARM_V(v) BM_UART_ULCR_PARM | ||
| 207 | #define BP_UART_ULCR_PARE 3 | ||
| 208 | #define BM_UART_ULCR_PARE 0x8 | ||
| 209 | #define BF_UART_ULCR_PARE(v) (((v) & 0x1) << 3) | ||
| 210 | #define BFM_UART_ULCR_PARE(v) BM_UART_ULCR_PARE | ||
| 211 | #define BF_UART_ULCR_PARE_V(e) BF_UART_ULCR_PARE(BV_UART_ULCR_PARE__##e) | ||
| 212 | #define BFM_UART_ULCR_PARE_V(v) BM_UART_ULCR_PARE | ||
| 213 | #define BP_UART_ULCR_SBLS 2 | ||
| 214 | #define BM_UART_ULCR_SBLS 0x4 | ||
| 215 | #define BV_UART_ULCR_SBLS__1_STOP_BIT 0x0 | ||
| 216 | #define BV_UART_ULCR_SBLS__2_STOP_BITS 0x1 | ||
| 217 | #define BF_UART_ULCR_SBLS(v) (((v) & 0x1) << 2) | ||
| 218 | #define BFM_UART_ULCR_SBLS(v) BM_UART_ULCR_SBLS | ||
| 219 | #define BF_UART_ULCR_SBLS_V(e) BF_UART_ULCR_SBLS(BV_UART_ULCR_SBLS__##e) | ||
| 220 | #define BFM_UART_ULCR_SBLS_V(v) BM_UART_ULCR_SBLS | ||
| 221 | |||
| 222 | #define REG_UART_UMCR(_n1) jz_reg(UART_UMCR(_n1)) | ||
| 223 | #define JA_UART_UMCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x10) | ||
| 224 | #define JT_UART_UMCR(_n1) JIO_32_RW | ||
| 225 | #define JN_UART_UMCR(_n1) UART_UMCR | ||
| 226 | #define JI_UART_UMCR(_n1) (_n1) | ||
| 227 | #define BP_UART_UMCR_MDCE 7 | ||
| 228 | #define BM_UART_UMCR_MDCE 0x80 | ||
| 229 | #define BF_UART_UMCR_MDCE(v) (((v) & 0x1) << 7) | ||
| 230 | #define BFM_UART_UMCR_MDCE(v) BM_UART_UMCR_MDCE | ||
| 231 | #define BF_UART_UMCR_MDCE_V(e) BF_UART_UMCR_MDCE(BV_UART_UMCR_MDCE__##e) | ||
| 232 | #define BFM_UART_UMCR_MDCE_V(v) BM_UART_UMCR_MDCE | ||
| 233 | #define BP_UART_UMCR_FCM 6 | ||
| 234 | #define BM_UART_UMCR_FCM 0x40 | ||
| 235 | #define BF_UART_UMCR_FCM(v) (((v) & 0x1) << 6) | ||
| 236 | #define BFM_UART_UMCR_FCM(v) BM_UART_UMCR_FCM | ||
| 237 | #define BF_UART_UMCR_FCM_V(e) BF_UART_UMCR_FCM(BV_UART_UMCR_FCM__##e) | ||
| 238 | #define BFM_UART_UMCR_FCM_V(v) BM_UART_UMCR_FCM | ||
| 239 | #define BP_UART_UMCR_LOOP 4 | ||
| 240 | #define BM_UART_UMCR_LOOP 0x10 | ||
| 241 | #define BF_UART_UMCR_LOOP(v) (((v) & 0x1) << 4) | ||
| 242 | #define BFM_UART_UMCR_LOOP(v) BM_UART_UMCR_LOOP | ||
| 243 | #define BF_UART_UMCR_LOOP_V(e) BF_UART_UMCR_LOOP(BV_UART_UMCR_LOOP__##e) | ||
| 244 | #define BFM_UART_UMCR_LOOP_V(v) BM_UART_UMCR_LOOP | ||
| 245 | #define BP_UART_UMCR_RTS 1 | ||
| 246 | #define BM_UART_UMCR_RTS 0x2 | ||
| 247 | #define BF_UART_UMCR_RTS(v) (((v) & 0x1) << 1) | ||
| 248 | #define BFM_UART_UMCR_RTS(v) BM_UART_UMCR_RTS | ||
| 249 | #define BF_UART_UMCR_RTS_V(e) BF_UART_UMCR_RTS(BV_UART_UMCR_RTS__##e) | ||
| 250 | #define BFM_UART_UMCR_RTS_V(v) BM_UART_UMCR_RTS | ||
| 251 | |||
| 252 | #define REG_UART_ULSR(_n1) jz_reg(UART_ULSR(_n1)) | ||
| 253 | #define JA_UART_ULSR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x14) | ||
| 254 | #define JT_UART_ULSR(_n1) JIO_32_RW | ||
| 255 | #define JN_UART_ULSR(_n1) UART_ULSR | ||
| 256 | #define JI_UART_ULSR(_n1) (_n1) | ||
| 257 | #define BP_UART_ULSR_FIFOE 7 | ||
| 258 | #define BM_UART_ULSR_FIFOE 0x80 | ||
| 259 | #define BF_UART_ULSR_FIFOE(v) (((v) & 0x1) << 7) | ||
| 260 | #define BFM_UART_ULSR_FIFOE(v) BM_UART_ULSR_FIFOE | ||
| 261 | #define BF_UART_ULSR_FIFOE_V(e) BF_UART_ULSR_FIFOE(BV_UART_ULSR_FIFOE__##e) | ||
| 262 | #define BFM_UART_ULSR_FIFOE_V(v) BM_UART_ULSR_FIFOE | ||
| 263 | #define BP_UART_ULSR_TEMP 6 | ||
| 264 | #define BM_UART_ULSR_TEMP 0x40 | ||
| 265 | #define BF_UART_ULSR_TEMP(v) (((v) & 0x1) << 6) | ||
| 266 | #define BFM_UART_ULSR_TEMP(v) BM_UART_ULSR_TEMP | ||
| 267 | #define BF_UART_ULSR_TEMP_V(e) BF_UART_ULSR_TEMP(BV_UART_ULSR_TEMP__##e) | ||
| 268 | #define BFM_UART_ULSR_TEMP_V(v) BM_UART_ULSR_TEMP | ||
| 269 | #define BP_UART_ULSR_TDRQ 5 | ||
| 270 | #define BM_UART_ULSR_TDRQ 0x20 | ||
| 271 | #define BF_UART_ULSR_TDRQ(v) (((v) & 0x1) << 5) | ||
| 272 | #define BFM_UART_ULSR_TDRQ(v) BM_UART_ULSR_TDRQ | ||
| 273 | #define BF_UART_ULSR_TDRQ_V(e) BF_UART_ULSR_TDRQ(BV_UART_ULSR_TDRQ__##e) | ||
| 274 | #define BFM_UART_ULSR_TDRQ_V(v) BM_UART_ULSR_TDRQ | ||
| 275 | #define BP_UART_ULSR_BI 4 | ||
| 276 | #define BM_UART_ULSR_BI 0x10 | ||
| 277 | #define BF_UART_ULSR_BI(v) (((v) & 0x1) << 4) | ||
| 278 | #define BFM_UART_ULSR_BI(v) BM_UART_ULSR_BI | ||
| 279 | #define BF_UART_ULSR_BI_V(e) BF_UART_ULSR_BI(BV_UART_ULSR_BI__##e) | ||
| 280 | #define BFM_UART_ULSR_BI_V(v) BM_UART_ULSR_BI | ||
| 281 | #define BP_UART_ULSR_FMER 3 | ||
| 282 | #define BM_UART_ULSR_FMER 0x8 | ||
| 283 | #define BF_UART_ULSR_FMER(v) (((v) & 0x1) << 3) | ||
| 284 | #define BFM_UART_ULSR_FMER(v) BM_UART_ULSR_FMER | ||
| 285 | #define BF_UART_ULSR_FMER_V(e) BF_UART_ULSR_FMER(BV_UART_ULSR_FMER__##e) | ||
| 286 | #define BFM_UART_ULSR_FMER_V(v) BM_UART_ULSR_FMER | ||
| 287 | #define BP_UART_ULSR_PARER 2 | ||
| 288 | #define BM_UART_ULSR_PARER 0x4 | ||
| 289 | #define BF_UART_ULSR_PARER(v) (((v) & 0x1) << 2) | ||
| 290 | #define BFM_UART_ULSR_PARER(v) BM_UART_ULSR_PARER | ||
| 291 | #define BF_UART_ULSR_PARER_V(e) BF_UART_ULSR_PARER(BV_UART_ULSR_PARER__##e) | ||
| 292 | #define BFM_UART_ULSR_PARER_V(v) BM_UART_ULSR_PARER | ||
| 293 | #define BP_UART_ULSR_OVER 1 | ||
| 294 | #define BM_UART_ULSR_OVER 0x2 | ||
| 295 | #define BF_UART_ULSR_OVER(v) (((v) & 0x1) << 1) | ||
| 296 | #define BFM_UART_ULSR_OVER(v) BM_UART_ULSR_OVER | ||
| 297 | #define BF_UART_ULSR_OVER_V(e) BF_UART_ULSR_OVER(BV_UART_ULSR_OVER__##e) | ||
| 298 | #define BFM_UART_ULSR_OVER_V(v) BM_UART_ULSR_OVER | ||
| 299 | #define BP_UART_ULSR_DRY 0 | ||
| 300 | #define BM_UART_ULSR_DRY 0x1 | ||
| 301 | #define BF_UART_ULSR_DRY(v) (((v) & 0x1) << 0) | ||
| 302 | #define BFM_UART_ULSR_DRY(v) BM_UART_ULSR_DRY | ||
| 303 | #define BF_UART_ULSR_DRY_V(e) BF_UART_ULSR_DRY(BV_UART_ULSR_DRY__##e) | ||
| 304 | #define BFM_UART_ULSR_DRY_V(v) BM_UART_ULSR_DRY | ||
| 305 | |||
| 306 | #define REG_UART_UMSR(_n1) jz_reg(UART_UMSR(_n1)) | ||
| 307 | #define JA_UART_UMSR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x18) | ||
| 308 | #define JT_UART_UMSR(_n1) JIO_32_RW | ||
| 309 | #define JN_UART_UMSR(_n1) UART_UMSR | ||
| 310 | #define JI_UART_UMSR(_n1) (_n1) | ||
| 311 | #define BP_UART_UMSR_CTS 4 | ||
| 312 | #define BM_UART_UMSR_CTS 0x10 | ||
| 313 | #define BF_UART_UMSR_CTS(v) (((v) & 0x1) << 4) | ||
| 314 | #define BFM_UART_UMSR_CTS(v) BM_UART_UMSR_CTS | ||
| 315 | #define BF_UART_UMSR_CTS_V(e) BF_UART_UMSR_CTS(BV_UART_UMSR_CTS__##e) | ||
| 316 | #define BFM_UART_UMSR_CTS_V(v) BM_UART_UMSR_CTS | ||
| 317 | #define BP_UART_UMSR_CCTS 0 | ||
| 318 | #define BM_UART_UMSR_CCTS 0x1 | ||
| 319 | #define BF_UART_UMSR_CCTS(v) (((v) & 0x1) << 0) | ||
| 320 | #define BFM_UART_UMSR_CCTS(v) BM_UART_UMSR_CCTS | ||
| 321 | #define BF_UART_UMSR_CCTS_V(e) BF_UART_UMSR_CCTS(BV_UART_UMSR_CCTS__##e) | ||
| 322 | #define BFM_UART_UMSR_CCTS_V(v) BM_UART_UMSR_CCTS | ||
| 323 | |||
| 324 | #define REG_UART_USPR(_n1) jz_reg(UART_USPR(_n1)) | ||
| 325 | #define JA_UART_USPR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x1c) | ||
| 326 | #define JT_UART_USPR(_n1) JIO_32_RW | ||
| 327 | #define JN_UART_USPR(_n1) UART_USPR | ||
| 328 | #define JI_UART_USPR(_n1) (_n1) | ||
| 329 | |||
| 330 | #define REG_UART_ISR(_n1) jz_reg(UART_ISR(_n1)) | ||
| 331 | #define JA_UART_ISR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x20) | ||
| 332 | #define JT_UART_ISR(_n1) JIO_32_RW | ||
| 333 | #define JN_UART_ISR(_n1) UART_ISR | ||
| 334 | #define JI_UART_ISR(_n1) (_n1) | ||
| 335 | #define BP_UART_ISR_RDPL 4 | ||
| 336 | #define BM_UART_ISR_RDPL 0x10 | ||
| 337 | #define BF_UART_ISR_RDPL(v) (((v) & 0x1) << 4) | ||
| 338 | #define BFM_UART_ISR_RDPL(v) BM_UART_ISR_RDPL | ||
| 339 | #define BF_UART_ISR_RDPL_V(e) BF_UART_ISR_RDPL(BV_UART_ISR_RDPL__##e) | ||
| 340 | #define BFM_UART_ISR_RDPL_V(v) BM_UART_ISR_RDPL | ||
| 341 | #define BP_UART_ISR_TDPL 3 | ||
| 342 | #define BM_UART_ISR_TDPL 0x8 | ||
| 343 | #define BF_UART_ISR_TDPL(v) (((v) & 0x1) << 3) | ||
| 344 | #define BFM_UART_ISR_TDPL(v) BM_UART_ISR_TDPL | ||
| 345 | #define BF_UART_ISR_TDPL_V(e) BF_UART_ISR_TDPL(BV_UART_ISR_TDPL__##e) | ||
| 346 | #define BFM_UART_ISR_TDPL_V(v) BM_UART_ISR_TDPL | ||
| 347 | #define BP_UART_ISR_XMODE 2 | ||
| 348 | #define BM_UART_ISR_XMODE 0x4 | ||
| 349 | #define BF_UART_ISR_XMODE(v) (((v) & 0x1) << 2) | ||
| 350 | #define BFM_UART_ISR_XMODE(v) BM_UART_ISR_XMODE | ||
| 351 | #define BF_UART_ISR_XMODE_V(e) BF_UART_ISR_XMODE(BV_UART_ISR_XMODE__##e) | ||
| 352 | #define BFM_UART_ISR_XMODE_V(v) BM_UART_ISR_XMODE | ||
| 353 | #define BP_UART_ISR_RCVEIR 1 | ||
| 354 | #define BM_UART_ISR_RCVEIR 0x2 | ||
| 355 | #define BF_UART_ISR_RCVEIR(v) (((v) & 0x1) << 1) | ||
| 356 | #define BFM_UART_ISR_RCVEIR(v) BM_UART_ISR_RCVEIR | ||
| 357 | #define BF_UART_ISR_RCVEIR_V(e) BF_UART_ISR_RCVEIR(BV_UART_ISR_RCVEIR__##e) | ||
| 358 | #define BFM_UART_ISR_RCVEIR_V(v) BM_UART_ISR_RCVEIR | ||
| 359 | #define BP_UART_ISR_XMITIR 0 | ||
| 360 | #define BM_UART_ISR_XMITIR 0x1 | ||
| 361 | #define BF_UART_ISR_XMITIR(v) (((v) & 0x1) << 0) | ||
| 362 | #define BFM_UART_ISR_XMITIR(v) BM_UART_ISR_XMITIR | ||
| 363 | #define BF_UART_ISR_XMITIR_V(e) BF_UART_ISR_XMITIR(BV_UART_ISR_XMITIR__##e) | ||
| 364 | #define BFM_UART_ISR_XMITIR_V(v) BM_UART_ISR_XMITIR | ||
| 365 | |||
| 366 | #define REG_UART_UMR(_n1) jz_reg(UART_UMR(_n1)) | ||
| 367 | #define JA_UART_UMR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x24) | ||
| 368 | #define JT_UART_UMR(_n1) JIO_32_RW | ||
| 369 | #define JN_UART_UMR(_n1) UART_UMR | ||
| 370 | #define JI_UART_UMR(_n1) (_n1) | ||
| 371 | |||
| 372 | #define REG_UART_UACR(_n1) jz_reg(UART_UACR(_n1)) | ||
| 373 | #define JA_UART_UACR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x28) | ||
| 374 | #define JT_UART_UACR(_n1) JIO_32_RW | ||
| 375 | #define JN_UART_UACR(_n1) UART_UACR | ||
| 376 | #define JI_UART_UACR(_n1) (_n1) | ||
| 377 | |||
| 378 | #define REG_UART_URCR(_n1) jz_reg(UART_URCR(_n1)) | ||
| 379 | #define JA_UART_URCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x40) | ||
| 380 | #define JT_UART_URCR(_n1) JIO_32_RW | ||
| 381 | #define JN_UART_URCR(_n1) UART_URCR | ||
| 382 | #define JI_UART_URCR(_n1) (_n1) | ||
| 383 | |||
| 384 | #define REG_UART_UTCR(_n1) jz_reg(UART_UTCR(_n1)) | ||
| 385 | #define JA_UART_UTCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x44) | ||
| 386 | #define JT_UART_UTCR(_n1) JIO_32_RW | ||
| 387 | #define JN_UART_UTCR(_n1) UART_UTCR | ||
| 388 | #define JI_UART_UTCR(_n1) (_n1) | ||
| 389 | |||
| 390 | #endif /* __HEADERGEN_UART_H__*/ | ||
diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index 0d971c59f8..4620378c19 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen | |||
| @@ -190,6 +190,115 @@ node AIC { | |||
| 190 | 190 | ||
| 191 | reg I2SDIV 0x30 | 191 | reg I2SDIV 0x30 |
| 192 | reg DR 0x34 | 192 | reg DR 0x34 |
| 193 | reg SPENA 0x80 | ||
| 194 | |||
| 195 | reg SPCTRL 0x84 { | ||
| 196 | bit 15 DMA_EN | ||
| 197 | bit 14 D_TYPE | ||
| 198 | bit 13 SIGN_N | ||
| 199 | bit 12 INVALID | ||
| 200 | bit 11 SFT_RST | ||
| 201 | bit 10 SPDIF_I2S | ||
| 202 | bit 1 M_TRIG | ||
| 203 | bit 0 M_FFUR | ||
| 204 | } | ||
| 205 | |||
| 206 | reg SPSTATE 0x88 { | ||
| 207 | fld 14 8 FIFO_LEVEL | ||
| 208 | bit 7 BUSY | ||
| 209 | bit 1 F_TRIG | ||
| 210 | bit 0 F_FFUR | ||
| 211 | } | ||
| 212 | |||
| 213 | reg SPCFG1 0x8c { | ||
| 214 | bit 17 INIT_LEVEL | ||
| 215 | bit 16 ZERO_VALID | ||
| 216 | fld 13 12 TRIG | ||
| 217 | fld 11 8 SRC_NUM | ||
| 218 | fld 7 4 CH1_NUM | ||
| 219 | fld 3 0 CH2_NUM | ||
| 220 | } | ||
| 221 | |||
| 222 | reg SPCFG2 0x90 { | ||
| 223 | fld 29 26 FS | ||
| 224 | fld 25 22 ORG_FRQ | ||
| 225 | fld 21 19 SAMPL_WL | ||
| 226 | bit 18 MAX_WL | ||
| 227 | fld 17 16 CLK_ACU | ||
| 228 | fld 15 8 CAT_CODE | ||
| 229 | fld 7 6 CH_MD | ||
| 230 | bit 3 PRE | ||
| 231 | bit 2 COPY_N | ||
| 232 | bit 1 AUDIO_N | ||
| 233 | bit 0 CON_PRO | ||
| 234 | } | ||
| 235 | |||
| 236 | reg SPFIFO 0x94 | ||
| 237 | |||
| 238 | reg RGADW 0xa4 { | ||
| 239 | bit 31 ICRST | ||
| 240 | bit 16 RGWR | ||
| 241 | fld 14 8 ADDR | ||
| 242 | fld 7 0 DATA | ||
| 243 | } | ||
| 244 | |||
| 245 | reg RGDATA 0xa8 { | ||
| 246 | bit 8 IRQ | ||
| 247 | fld 7 0 DATA | ||
| 248 | } | ||
| 249 | } | ||
| 250 | |||
| 251 | node PCM { | ||
| 252 | title "PCM interface controller" | ||
| 253 | addr 0xb0071000 | ||
| 254 | |||
| 255 | reg CTL 0x00 { | ||
| 256 | bit 9 ERDMA | ||
| 257 | bit 8 ETDMA | ||
| 258 | bit 7 LSMP | ||
| 259 | bit 6 ERPL | ||
| 260 | bit 5 EREC | ||
| 261 | bit 4 FLUSH | ||
| 262 | bit 3 RST | ||
| 263 | bit 1 CLKEN | ||
| 264 | bit 0 PCMEN | ||
| 265 | } | ||
| 266 | |||
| 267 | reg CFG 0x04 { | ||
| 268 | fld 14 13 SLOT | ||
| 269 | bit 12 ISS | ||
| 270 | bit 11 OSS | ||
| 271 | bit 10 IMSBPOS | ||
| 272 | bit 9 OMSBPOS | ||
| 273 | fld 8 5 RFTH | ||
| 274 | fld 4 1 TFTH | ||
| 275 | bit 0 PCMMOD | ||
| 276 | } | ||
| 277 | |||
| 278 | reg DP 0x08 | ||
| 279 | |||
| 280 | reg INTC 0x0c { | ||
| 281 | bit 3 ETFS | ||
| 282 | bit 2 ETUR | ||
| 283 | bit 1 ERFS | ||
| 284 | bit 0 EROR | ||
| 285 | } | ||
| 286 | |||
| 287 | reg INTS 0x10 { | ||
| 288 | bit 14 RSTS | ||
| 289 | fld 13 9 TFL | ||
| 290 | bit 8 TFS | ||
| 291 | bit 7 TUR | ||
| 292 | bit 6 2 RFL | ||
| 293 | bit 1 RFS | ||
| 294 | bit 0 ROR | ||
| 295 | } | ||
| 296 | |||
| 297 | reg DIV 0x14 { | ||
| 298 | fld 16 11 SYNL | ||
| 299 | fld 10 6 SYNDIV | ||
| 300 | fld 5 0 CLKDIV | ||
| 301 | } | ||
| 193 | } | 302 | } |
| 194 | 303 | ||
| 195 | node DDRC { | 304 | node DDRC { |
| @@ -851,6 +960,44 @@ node RTC { | |||
| 851 | reg WKUPPINCR 0x48 | 960 | reg WKUPPINCR 0x48 |
| 852 | } | 961 | } |
| 853 | 962 | ||
| 963 | node EFUSE { | ||
| 964 | title "EFUSE interface" | ||
| 965 | instance 0xb3540000 | ||
| 966 | |||
| 967 | reg CTRL 0x00 { | ||
| 968 | fld 27 21 ADDR | ||
| 969 | fld 20 16 LENGTH | ||
| 970 | bit 15 PG_EN | ||
| 971 | bit 1 WR_EN | ||
| 972 | bit 0 RD_EN | ||
| 973 | } | ||
| 974 | |||
| 975 | reg CFG 0x04 { | ||
| 976 | bit 31 INT_EN | ||
| 977 | fld 21 20 RD_AJD | ||
| 978 | fld 18 16 RD_STROBE | ||
| 979 | fld 13 12 WR_ADJ | ||
| 980 | fld 8 0 WR_STROBE | ||
| 981 | } | ||
| 982 | |||
| 983 | reg STATE 0x08 { | ||
| 984 | bit 23 UK_PRT | ||
| 985 | bit 22 NKU_PRT | ||
| 986 | bit 21 EXKEY_EN | ||
| 987 | bit 15 CUSTID_PRT | ||
| 988 | bit 14 CHIPID_PRT | ||
| 989 | bit 12 SECBOOT_PRT | ||
| 990 | bit 11 DIS_JTAG | ||
| 991 | bit 8 SECBOOT_EN | ||
| 992 | bit 1 WR_DONE | ||
| 993 | bit 0 RD_DONE | ||
| 994 | } | ||
| 995 | |||
| 996 | reg DATA { | ||
| 997 | instance 0x0c 0x04 8 | ||
| 998 | } | ||
| 999 | } | ||
| 1000 | |||
| 854 | node GPIO { | 1001 | node GPIO { |
| 855 | title "General purpose I/O" | 1002 | title "General purpose I/O" |
| 856 | addr 0xb0010000 | 1003 | addr 0xb0010000 |
| @@ -1003,6 +1150,156 @@ node I2C { | |||
| 1003 | reg CGC 0x68 | 1150 | reg CGC 0x68 |
| 1004 | } | 1151 | } |
| 1005 | 1152 | ||
| 1153 | node SSI { | ||
| 1154 | title "Synchronous serial interface" | ||
| 1155 | instance 0xb0043000 | ||
| 1156 | |||
| 1157 | reg DR 0x00 | ||
| 1158 | |||
| 1159 | reg CR0 0x04 { | ||
| 1160 | fld 19 18 TENDIAN | ||
| 1161 | fld 17 16 RENDIAN | ||
| 1162 | bit 15 SSIE | ||
| 1163 | bit 14 TIE | ||
| 1164 | bit 13 RIE | ||
| 1165 | bit 12 TEIE | ||
| 1166 | bit 11 REIE | ||
| 1167 | bit 10 LOOP | ||
| 1168 | bit 9 RFINE | ||
| 1169 | bit 8 RFINC | ||
| 1170 | bit 7 EACLRUN | ||
| 1171 | bit 6 FSEL | ||
| 1172 | bit 4 VRCNT | ||
| 1173 | bit 3 TFMODE | ||
| 1174 | bit 2 TFLUSH | ||
| 1175 | bit 1 RFLUSH | ||
| 1176 | bit 0 DISREV | ||
| 1177 | } | ||
| 1178 | |||
| 1179 | reg CR1 0x08 { | ||
| 1180 | fld 31 30 FRMHL | ||
| 1181 | fld 29 28 TFVCK | ||
| 1182 | fld 27 26 TCKFI | ||
| 1183 | bit 24 ITFRM | ||
| 1184 | bit 23 UNFIN | ||
| 1185 | fld 21 20 FMAT | ||
| 1186 | fld 19 16 TTRG | ||
| 1187 | fld 15 12 MCOM | ||
| 1188 | fld 11 8 RTRG | ||
| 1189 | fld 7 3 FLEN | ||
| 1190 | bit 1 PHA | ||
| 1191 | bit 0 POL | ||
| 1192 | } | ||
| 1193 | |||
| 1194 | reg SR 0x0c { | ||
| 1195 | fld 24 16 TFIFO_NUM | ||
| 1196 | fld 15 8 RFIFO_NUM | ||
| 1197 | bit 7 END | ||
| 1198 | bit 6 BUSY | ||
| 1199 | bit 5 TFF | ||
| 1200 | bit 4 RFE | ||
| 1201 | bit 3 TFHE | ||
| 1202 | bit 2 RFHF | ||
| 1203 | bit 1 UNDR | ||
| 1204 | bit 0 OVER | ||
| 1205 | } | ||
| 1206 | |||
| 1207 | reg ITR 0x10 { | ||
| 1208 | bit 15 CNTCLK | ||
| 1209 | fld 14 0 IVLTM | ||
| 1210 | } | ||
| 1211 | |||
| 1212 | reg ICR 0x14 | ||
| 1213 | reg GR 0x18 | ||
| 1214 | reg RCNT 0x1c | ||
| 1215 | } | ||
| 1216 | |||
| 1217 | node UART { | ||
| 1218 | title "UART controller" | ||
| 1219 | instance 0xb0030000 0x1000 3 | ||
| 1220 | |||
| 1221 | # Note there is some hardware multiplexing controlled by the | ||
| 1222 | # ULCR register going on here which is why some registers share | ||
| 1223 | # the same address. | ||
| 1224 | |||
| 1225 | reg URBR 0x00 | ||
| 1226 | reg UTHR 0x00 | ||
| 1227 | reg UDLLR 0x00 | ||
| 1228 | reg UDLHR 0x04 | ||
| 1229 | |||
| 1230 | reg UIER 0x04 { | ||
| 1231 | bit 4 RTOIE | ||
| 1232 | bit 3 MSIE | ||
| 1233 | bit 2 RLSIE | ||
| 1234 | bit 1 TDRIE | ||
| 1235 | bit 0 RDRIE | ||
| 1236 | } | ||
| 1237 | |||
| 1238 | reg UIIR 0x08 { | ||
| 1239 | fld 7 6 FFMSEL { enum NON_FIFO_MODE 0; enum FIFO_MODE 1; } | ||
| 1240 | fld 3 1 INID { enum MODEM_STATUS 0; enum TRANSMIT_DATA_REQ 1; enum RECEIVE_DATA_READY 2 | ||
| 1241 | enum RECEIVE_LINE_STATUS 3; enum RECEIVE_TIME_OUT 6 } | ||
| 1242 | bit 0 INPEND | ||
| 1243 | } | ||
| 1244 | |||
| 1245 | reg UFCR 0x08 { | ||
| 1246 | fld 7 6 RDTR { enum 1BYTE 0; enum 16BYTE 1; enum 32BYTE 2; enum 60BYTE 3; } | ||
| 1247 | bit 4 UME | ||
| 1248 | bit 3 DME | ||
| 1249 | bit 2 TFRT | ||
| 1250 | bit 1 RFRT | ||
| 1251 | bit 0 FME | ||
| 1252 | } | ||
| 1253 | |||
| 1254 | reg ULCR 0x0c { | ||
| 1255 | bit 7 DLAB | ||
| 1256 | bit 6 SBK | ||
| 1257 | bit 5 STPAR | ||
| 1258 | bit 4 PARM { enum ODD 0; enum EVEN 1; } | ||
| 1259 | bit 3 PARE | ||
| 1260 | bit 2 SBLS { enum 1_STOP_BIT 0; enum 2_STOP_BITS 1; } | ||
| 1261 | fld 1 0 WLS { enum 5BITS 0; enum 6BITS 1; enum 7BITS 2; enum 8BITS 3; } | ||
| 1262 | } | ||
| 1263 | |||
| 1264 | reg UMCR 0x10 { | ||
| 1265 | bit 7 MDCE | ||
| 1266 | bit 6 FCM | ||
| 1267 | bit 4 LOOP | ||
| 1268 | bit 1 RTS | ||
| 1269 | } | ||
| 1270 | |||
| 1271 | reg ULSR 0x14 { | ||
| 1272 | bit 7 FIFOE | ||
| 1273 | bit 6 TEMP | ||
| 1274 | bit 5 TDRQ | ||
| 1275 | bit 4 BI | ||
| 1276 | bit 3 FMER | ||
| 1277 | bit 2 PARER | ||
| 1278 | bit 1 OVER | ||
| 1279 | bit 0 DRY | ||
| 1280 | } | ||
| 1281 | |||
| 1282 | reg UMSR 0x18 { | ||
| 1283 | bit 4 CTS | ||
| 1284 | bit 0 CCTS | ||
| 1285 | } | ||
| 1286 | |||
| 1287 | reg USPR 0x1c | ||
| 1288 | |||
| 1289 | reg ISR 0x20 { | ||
| 1290 | bit 4 RDPL | ||
| 1291 | bit 3 TDPL | ||
| 1292 | bit 2 XMODE | ||
| 1293 | bit 1 RCVEIR | ||
| 1294 | bit 0 XMITIR | ||
| 1295 | } | ||
| 1296 | |||
| 1297 | reg UMR 0x24 | ||
| 1298 | reg UACR 0x28 | ||
| 1299 | reg URCR 0x40 | ||
| 1300 | reg UTCR 0x44 | ||
| 1301 | } | ||
| 1302 | |||
| 1006 | node MSC { | 1303 | node MSC { |
| 1007 | title "MMC/SD/CE-ATA controller" | 1304 | title "MMC/SD/CE-ATA controller" |
| 1008 | instance 0xb3450000 0x10000 2 | 1305 | instance 0xb3450000 0x10000 2 |