From f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Sat, 29 May 2021 16:34:32 +0100 Subject: x1000: Complete the register definitions I think this covers everything now, although some fields are missing enum values. Those can be added in if and when they are needed. Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f --- firmware/target/mips/ingenic_x1000/x1000/aic.h | 258 +++++++++++++++ firmware/target/mips/ingenic_x1000/x1000/efuse.h | 173 ++++++++++ firmware/target/mips/ingenic_x1000/x1000/pcm.h | 251 +++++++++++++++ firmware/target/mips/ingenic_x1000/x1000/ssi.h | 323 +++++++++++++++++++ firmware/target/mips/ingenic_x1000/x1000/uart.h | 390 +++++++++++++++++++++++ utils/reggen-ng/x1000.reggen | 297 +++++++++++++++++ 6 files changed, 1692 insertions(+) create mode 100644 firmware/target/mips/ingenic_x1000/x1000/efuse.h create mode 100644 firmware/target/mips/ingenic_x1000/x1000/pcm.h create mode 100644 firmware/target/mips/ingenic_x1000/x1000/ssi.h create mode 100644 firmware/target/mips/ingenic_x1000/x1000/uart.h diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h index e9c68511d7..d212ddc4e1 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/aic.h +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h @@ -356,4 +356,262 @@ #define JN_AIC_DR AIC_DR #define JI_AIC_DR +#define REG_AIC_SPENA jz_reg(AIC_SPENA) +#define JA_AIC_SPENA (0xb0020000 + 0x80) +#define JT_AIC_SPENA JIO_32_RW +#define JN_AIC_SPENA AIC_SPENA +#define JI_AIC_SPENA + +#define REG_AIC_SPCTRL jz_reg(AIC_SPCTRL) +#define JA_AIC_SPCTRL (0xb0020000 + 0x84) +#define JT_AIC_SPCTRL JIO_32_RW +#define JN_AIC_SPCTRL AIC_SPCTRL +#define JI_AIC_SPCTRL +#define BP_AIC_SPCTRL_DMA_EN 15 +#define BM_AIC_SPCTRL_DMA_EN 0x8000 +#define BF_AIC_SPCTRL_DMA_EN(v) (((v) & 0x1) << 15) +#define BFM_AIC_SPCTRL_DMA_EN(v) BM_AIC_SPCTRL_DMA_EN +#define BF_AIC_SPCTRL_DMA_EN_V(e) BF_AIC_SPCTRL_DMA_EN(BV_AIC_SPCTRL_DMA_EN__##e) +#define BFM_AIC_SPCTRL_DMA_EN_V(v) BM_AIC_SPCTRL_DMA_EN +#define BP_AIC_SPCTRL_D_TYPE 14 +#define BM_AIC_SPCTRL_D_TYPE 0x4000 +#define BF_AIC_SPCTRL_D_TYPE(v) (((v) & 0x1) << 14) +#define BFM_AIC_SPCTRL_D_TYPE(v) BM_AIC_SPCTRL_D_TYPE +#define BF_AIC_SPCTRL_D_TYPE_V(e) BF_AIC_SPCTRL_D_TYPE(BV_AIC_SPCTRL_D_TYPE__##e) +#define BFM_AIC_SPCTRL_D_TYPE_V(v) BM_AIC_SPCTRL_D_TYPE +#define BP_AIC_SPCTRL_SIGN_N 13 +#define BM_AIC_SPCTRL_SIGN_N 0x2000 +#define BF_AIC_SPCTRL_SIGN_N(v) (((v) & 0x1) << 13) +#define BFM_AIC_SPCTRL_SIGN_N(v) BM_AIC_SPCTRL_SIGN_N +#define BF_AIC_SPCTRL_SIGN_N_V(e) BF_AIC_SPCTRL_SIGN_N(BV_AIC_SPCTRL_SIGN_N__##e) +#define BFM_AIC_SPCTRL_SIGN_N_V(v) BM_AIC_SPCTRL_SIGN_N +#define BP_AIC_SPCTRL_INVALID 12 +#define BM_AIC_SPCTRL_INVALID 0x1000 +#define BF_AIC_SPCTRL_INVALID(v) (((v) & 0x1) << 12) +#define BFM_AIC_SPCTRL_INVALID(v) BM_AIC_SPCTRL_INVALID +#define BF_AIC_SPCTRL_INVALID_V(e) BF_AIC_SPCTRL_INVALID(BV_AIC_SPCTRL_INVALID__##e) +#define BFM_AIC_SPCTRL_INVALID_V(v) BM_AIC_SPCTRL_INVALID +#define BP_AIC_SPCTRL_SFT_RST 11 +#define BM_AIC_SPCTRL_SFT_RST 0x800 +#define BF_AIC_SPCTRL_SFT_RST(v) (((v) & 0x1) << 11) +#define BFM_AIC_SPCTRL_SFT_RST(v) BM_AIC_SPCTRL_SFT_RST +#define BF_AIC_SPCTRL_SFT_RST_V(e) BF_AIC_SPCTRL_SFT_RST(BV_AIC_SPCTRL_SFT_RST__##e) +#define BFM_AIC_SPCTRL_SFT_RST_V(v) BM_AIC_SPCTRL_SFT_RST +#define BP_AIC_SPCTRL_SPDIF_I2S 10 +#define BM_AIC_SPCTRL_SPDIF_I2S 0x400 +#define BF_AIC_SPCTRL_SPDIF_I2S(v) (((v) & 0x1) << 10) +#define BFM_AIC_SPCTRL_SPDIF_I2S(v) BM_AIC_SPCTRL_SPDIF_I2S +#define BF_AIC_SPCTRL_SPDIF_I2S_V(e) BF_AIC_SPCTRL_SPDIF_I2S(BV_AIC_SPCTRL_SPDIF_I2S__##e) +#define BFM_AIC_SPCTRL_SPDIF_I2S_V(v) BM_AIC_SPCTRL_SPDIF_I2S +#define BP_AIC_SPCTRL_M_TRIG 1 +#define BM_AIC_SPCTRL_M_TRIG 0x2 +#define BF_AIC_SPCTRL_M_TRIG(v) (((v) & 0x1) << 1) +#define BFM_AIC_SPCTRL_M_TRIG(v) BM_AIC_SPCTRL_M_TRIG +#define BF_AIC_SPCTRL_M_TRIG_V(e) BF_AIC_SPCTRL_M_TRIG(BV_AIC_SPCTRL_M_TRIG__##e) +#define BFM_AIC_SPCTRL_M_TRIG_V(v) BM_AIC_SPCTRL_M_TRIG +#define BP_AIC_SPCTRL_M_FFUR 0 +#define BM_AIC_SPCTRL_M_FFUR 0x1 +#define BF_AIC_SPCTRL_M_FFUR(v) (((v) & 0x1) << 0) +#define BFM_AIC_SPCTRL_M_FFUR(v) BM_AIC_SPCTRL_M_FFUR +#define BF_AIC_SPCTRL_M_FFUR_V(e) BF_AIC_SPCTRL_M_FFUR(BV_AIC_SPCTRL_M_FFUR__##e) +#define BFM_AIC_SPCTRL_M_FFUR_V(v) BM_AIC_SPCTRL_M_FFUR + +#define REG_AIC_SPSTATE jz_reg(AIC_SPSTATE) +#define JA_AIC_SPSTATE (0xb0020000 + 0x88) +#define JT_AIC_SPSTATE JIO_32_RW +#define JN_AIC_SPSTATE AIC_SPSTATE +#define JI_AIC_SPSTATE +#define BP_AIC_SPSTATE_FIFO_LEVEL 8 +#define BM_AIC_SPSTATE_FIFO_LEVEL 0x7f00 +#define BF_AIC_SPSTATE_FIFO_LEVEL(v) (((v) & 0x7f) << 8) +#define BFM_AIC_SPSTATE_FIFO_LEVEL(v) BM_AIC_SPSTATE_FIFO_LEVEL +#define BF_AIC_SPSTATE_FIFO_LEVEL_V(e) BF_AIC_SPSTATE_FIFO_LEVEL(BV_AIC_SPSTATE_FIFO_LEVEL__##e) +#define BFM_AIC_SPSTATE_FIFO_LEVEL_V(v) BM_AIC_SPSTATE_FIFO_LEVEL +#define BP_AIC_SPSTATE_BUSY 7 +#define BM_AIC_SPSTATE_BUSY 0x80 +#define BF_AIC_SPSTATE_BUSY(v) (((v) & 0x1) << 7) +#define BFM_AIC_SPSTATE_BUSY(v) BM_AIC_SPSTATE_BUSY +#define BF_AIC_SPSTATE_BUSY_V(e) BF_AIC_SPSTATE_BUSY(BV_AIC_SPSTATE_BUSY__##e) +#define BFM_AIC_SPSTATE_BUSY_V(v) BM_AIC_SPSTATE_BUSY +#define BP_AIC_SPSTATE_F_TRIG 1 +#define BM_AIC_SPSTATE_F_TRIG 0x2 +#define BF_AIC_SPSTATE_F_TRIG(v) (((v) & 0x1) << 1) +#define BFM_AIC_SPSTATE_F_TRIG(v) BM_AIC_SPSTATE_F_TRIG +#define BF_AIC_SPSTATE_F_TRIG_V(e) BF_AIC_SPSTATE_F_TRIG(BV_AIC_SPSTATE_F_TRIG__##e) +#define BFM_AIC_SPSTATE_F_TRIG_V(v) BM_AIC_SPSTATE_F_TRIG +#define BP_AIC_SPSTATE_F_FFUR 0 +#define BM_AIC_SPSTATE_F_FFUR 0x1 +#define BF_AIC_SPSTATE_F_FFUR(v) (((v) & 0x1) << 0) +#define BFM_AIC_SPSTATE_F_FFUR(v) BM_AIC_SPSTATE_F_FFUR +#define BF_AIC_SPSTATE_F_FFUR_V(e) BF_AIC_SPSTATE_F_FFUR(BV_AIC_SPSTATE_F_FFUR__##e) +#define BFM_AIC_SPSTATE_F_FFUR_V(v) BM_AIC_SPSTATE_F_FFUR + +#define REG_AIC_SPCFG1 jz_reg(AIC_SPCFG1) +#define JA_AIC_SPCFG1 (0xb0020000 + 0x8c) +#define JT_AIC_SPCFG1 JIO_32_RW +#define JN_AIC_SPCFG1 AIC_SPCFG1 +#define JI_AIC_SPCFG1 +#define BP_AIC_SPCFG1_TRIG 12 +#define BM_AIC_SPCFG1_TRIG 0x3000 +#define BF_AIC_SPCFG1_TRIG(v) (((v) & 0x3) << 12) +#define BFM_AIC_SPCFG1_TRIG(v) BM_AIC_SPCFG1_TRIG +#define BF_AIC_SPCFG1_TRIG_V(e) BF_AIC_SPCFG1_TRIG(BV_AIC_SPCFG1_TRIG__##e) +#define BFM_AIC_SPCFG1_TRIG_V(v) BM_AIC_SPCFG1_TRIG +#define BP_AIC_SPCFG1_SRC_NUM 8 +#define BM_AIC_SPCFG1_SRC_NUM 0xf00 +#define BF_AIC_SPCFG1_SRC_NUM(v) (((v) & 0xf) << 8) +#define BFM_AIC_SPCFG1_SRC_NUM(v) BM_AIC_SPCFG1_SRC_NUM +#define BF_AIC_SPCFG1_SRC_NUM_V(e) BF_AIC_SPCFG1_SRC_NUM(BV_AIC_SPCFG1_SRC_NUM__##e) +#define BFM_AIC_SPCFG1_SRC_NUM_V(v) BM_AIC_SPCFG1_SRC_NUM +#define BP_AIC_SPCFG1_CH1_NUM 4 +#define BM_AIC_SPCFG1_CH1_NUM 0xf0 +#define BF_AIC_SPCFG1_CH1_NUM(v) (((v) & 0xf) << 4) +#define BFM_AIC_SPCFG1_CH1_NUM(v) BM_AIC_SPCFG1_CH1_NUM +#define BF_AIC_SPCFG1_CH1_NUM_V(e) BF_AIC_SPCFG1_CH1_NUM(BV_AIC_SPCFG1_CH1_NUM__##e) +#define BFM_AIC_SPCFG1_CH1_NUM_V(v) BM_AIC_SPCFG1_CH1_NUM +#define BP_AIC_SPCFG1_CH2_NUM 0 +#define BM_AIC_SPCFG1_CH2_NUM 0xf +#define BF_AIC_SPCFG1_CH2_NUM(v) (((v) & 0xf) << 0) +#define BFM_AIC_SPCFG1_CH2_NUM(v) BM_AIC_SPCFG1_CH2_NUM +#define BF_AIC_SPCFG1_CH2_NUM_V(e) BF_AIC_SPCFG1_CH2_NUM(BV_AIC_SPCFG1_CH2_NUM__##e) +#define BFM_AIC_SPCFG1_CH2_NUM_V(v) BM_AIC_SPCFG1_CH2_NUM +#define BP_AIC_SPCFG1_INIT_LEVEL 17 +#define BM_AIC_SPCFG1_INIT_LEVEL 0x20000 +#define BF_AIC_SPCFG1_INIT_LEVEL(v) (((v) & 0x1) << 17) +#define BFM_AIC_SPCFG1_INIT_LEVEL(v) BM_AIC_SPCFG1_INIT_LEVEL +#define BF_AIC_SPCFG1_INIT_LEVEL_V(e) BF_AIC_SPCFG1_INIT_LEVEL(BV_AIC_SPCFG1_INIT_LEVEL__##e) +#define BFM_AIC_SPCFG1_INIT_LEVEL_V(v) BM_AIC_SPCFG1_INIT_LEVEL +#define BP_AIC_SPCFG1_ZERO_VALID 16 +#define BM_AIC_SPCFG1_ZERO_VALID 0x10000 +#define BF_AIC_SPCFG1_ZERO_VALID(v) (((v) & 0x1) << 16) +#define BFM_AIC_SPCFG1_ZERO_VALID(v) BM_AIC_SPCFG1_ZERO_VALID +#define BF_AIC_SPCFG1_ZERO_VALID_V(e) BF_AIC_SPCFG1_ZERO_VALID(BV_AIC_SPCFG1_ZERO_VALID__##e) +#define BFM_AIC_SPCFG1_ZERO_VALID_V(v) BM_AIC_SPCFG1_ZERO_VALID + +#define REG_AIC_SPCFG2 jz_reg(AIC_SPCFG2) +#define JA_AIC_SPCFG2 (0xb0020000 + 0x90) +#define JT_AIC_SPCFG2 JIO_32_RW +#define JN_AIC_SPCFG2 AIC_SPCFG2 +#define JI_AIC_SPCFG2 +#define BP_AIC_SPCFG2_FS 26 +#define BM_AIC_SPCFG2_FS 0x3c000000 +#define BF_AIC_SPCFG2_FS(v) (((v) & 0xf) << 26) +#define BFM_AIC_SPCFG2_FS(v) BM_AIC_SPCFG2_FS +#define BF_AIC_SPCFG2_FS_V(e) BF_AIC_SPCFG2_FS(BV_AIC_SPCFG2_FS__##e) +#define BFM_AIC_SPCFG2_FS_V(v) BM_AIC_SPCFG2_FS +#define BP_AIC_SPCFG2_ORG_FRQ 22 +#define BM_AIC_SPCFG2_ORG_FRQ 0x3c00000 +#define BF_AIC_SPCFG2_ORG_FRQ(v) (((v) & 0xf) << 22) +#define BFM_AIC_SPCFG2_ORG_FRQ(v) BM_AIC_SPCFG2_ORG_FRQ +#define BF_AIC_SPCFG2_ORG_FRQ_V(e) BF_AIC_SPCFG2_ORG_FRQ(BV_AIC_SPCFG2_ORG_FRQ__##e) +#define BFM_AIC_SPCFG2_ORG_FRQ_V(v) BM_AIC_SPCFG2_ORG_FRQ +#define BP_AIC_SPCFG2_SAMPL_WL 19 +#define BM_AIC_SPCFG2_SAMPL_WL 0x380000 +#define BF_AIC_SPCFG2_SAMPL_WL(v) (((v) & 0x7) << 19) +#define BFM_AIC_SPCFG2_SAMPL_WL(v) BM_AIC_SPCFG2_SAMPL_WL +#define BF_AIC_SPCFG2_SAMPL_WL_V(e) BF_AIC_SPCFG2_SAMPL_WL(BV_AIC_SPCFG2_SAMPL_WL__##e) +#define BFM_AIC_SPCFG2_SAMPL_WL_V(v) BM_AIC_SPCFG2_SAMPL_WL +#define BP_AIC_SPCFG2_CLK_ACU 16 +#define BM_AIC_SPCFG2_CLK_ACU 0x30000 +#define BF_AIC_SPCFG2_CLK_ACU(v) (((v) & 0x3) << 16) +#define BFM_AIC_SPCFG2_CLK_ACU(v) BM_AIC_SPCFG2_CLK_ACU +#define BF_AIC_SPCFG2_CLK_ACU_V(e) BF_AIC_SPCFG2_CLK_ACU(BV_AIC_SPCFG2_CLK_ACU__##e) +#define BFM_AIC_SPCFG2_CLK_ACU_V(v) BM_AIC_SPCFG2_CLK_ACU +#define BP_AIC_SPCFG2_CAT_CODE 8 +#define BM_AIC_SPCFG2_CAT_CODE 0xff00 +#define BF_AIC_SPCFG2_CAT_CODE(v) (((v) & 0xff) << 8) +#define BFM_AIC_SPCFG2_CAT_CODE(v) BM_AIC_SPCFG2_CAT_CODE +#define BF_AIC_SPCFG2_CAT_CODE_V(e) BF_AIC_SPCFG2_CAT_CODE(BV_AIC_SPCFG2_CAT_CODE__##e) +#define BFM_AIC_SPCFG2_CAT_CODE_V(v) BM_AIC_SPCFG2_CAT_CODE +#define BP_AIC_SPCFG2_CH_MD 6 +#define BM_AIC_SPCFG2_CH_MD 0xc0 +#define BF_AIC_SPCFG2_CH_MD(v) (((v) & 0x3) << 6) +#define BFM_AIC_SPCFG2_CH_MD(v) BM_AIC_SPCFG2_CH_MD +#define BF_AIC_SPCFG2_CH_MD_V(e) BF_AIC_SPCFG2_CH_MD(BV_AIC_SPCFG2_CH_MD__##e) +#define BFM_AIC_SPCFG2_CH_MD_V(v) BM_AIC_SPCFG2_CH_MD +#define BP_AIC_SPCFG2_MAX_WL 18 +#define BM_AIC_SPCFG2_MAX_WL 0x40000 +#define BF_AIC_SPCFG2_MAX_WL(v) (((v) & 0x1) << 18) +#define BFM_AIC_SPCFG2_MAX_WL(v) BM_AIC_SPCFG2_MAX_WL +#define BF_AIC_SPCFG2_MAX_WL_V(e) BF_AIC_SPCFG2_MAX_WL(BV_AIC_SPCFG2_MAX_WL__##e) +#define BFM_AIC_SPCFG2_MAX_WL_V(v) BM_AIC_SPCFG2_MAX_WL +#define BP_AIC_SPCFG2_PRE 3 +#define BM_AIC_SPCFG2_PRE 0x8 +#define BF_AIC_SPCFG2_PRE(v) (((v) & 0x1) << 3) +#define BFM_AIC_SPCFG2_PRE(v) BM_AIC_SPCFG2_PRE +#define BF_AIC_SPCFG2_PRE_V(e) BF_AIC_SPCFG2_PRE(BV_AIC_SPCFG2_PRE__##e) +#define BFM_AIC_SPCFG2_PRE_V(v) BM_AIC_SPCFG2_PRE +#define BP_AIC_SPCFG2_COPY_N 2 +#define BM_AIC_SPCFG2_COPY_N 0x4 +#define BF_AIC_SPCFG2_COPY_N(v) (((v) & 0x1) << 2) +#define BFM_AIC_SPCFG2_COPY_N(v) BM_AIC_SPCFG2_COPY_N +#define BF_AIC_SPCFG2_COPY_N_V(e) BF_AIC_SPCFG2_COPY_N(BV_AIC_SPCFG2_COPY_N__##e) +#define BFM_AIC_SPCFG2_COPY_N_V(v) BM_AIC_SPCFG2_COPY_N +#define BP_AIC_SPCFG2_AUDIO_N 1 +#define BM_AIC_SPCFG2_AUDIO_N 0x2 +#define BF_AIC_SPCFG2_AUDIO_N(v) (((v) & 0x1) << 1) +#define BFM_AIC_SPCFG2_AUDIO_N(v) BM_AIC_SPCFG2_AUDIO_N +#define BF_AIC_SPCFG2_AUDIO_N_V(e) BF_AIC_SPCFG2_AUDIO_N(BV_AIC_SPCFG2_AUDIO_N__##e) +#define BFM_AIC_SPCFG2_AUDIO_N_V(v) BM_AIC_SPCFG2_AUDIO_N +#define BP_AIC_SPCFG2_CON_PRO 0 +#define BM_AIC_SPCFG2_CON_PRO 0x1 +#define BF_AIC_SPCFG2_CON_PRO(v) (((v) & 0x1) << 0) +#define BFM_AIC_SPCFG2_CON_PRO(v) BM_AIC_SPCFG2_CON_PRO +#define BF_AIC_SPCFG2_CON_PRO_V(e) BF_AIC_SPCFG2_CON_PRO(BV_AIC_SPCFG2_CON_PRO__##e) +#define BFM_AIC_SPCFG2_CON_PRO_V(v) BM_AIC_SPCFG2_CON_PRO + +#define REG_AIC_SPFIFO jz_reg(AIC_SPFIFO) +#define JA_AIC_SPFIFO (0xb0020000 + 0x94) +#define JT_AIC_SPFIFO JIO_32_RW +#define JN_AIC_SPFIFO AIC_SPFIFO +#define JI_AIC_SPFIFO + +#define REG_AIC_RGADW jz_reg(AIC_RGADW) +#define JA_AIC_RGADW (0xb0020000 + 0xa4) +#define JT_AIC_RGADW JIO_32_RW +#define JN_AIC_RGADW AIC_RGADW +#define JI_AIC_RGADW +#define BP_AIC_RGADW_ADDR 8 +#define BM_AIC_RGADW_ADDR 0x7f00 +#define BF_AIC_RGADW_ADDR(v) (((v) & 0x7f) << 8) +#define BFM_AIC_RGADW_ADDR(v) BM_AIC_RGADW_ADDR +#define BF_AIC_RGADW_ADDR_V(e) BF_AIC_RGADW_ADDR(BV_AIC_RGADW_ADDR__##e) +#define BFM_AIC_RGADW_ADDR_V(v) BM_AIC_RGADW_ADDR +#define BP_AIC_RGADW_DATA 0 +#define BM_AIC_RGADW_DATA 0xff +#define BF_AIC_RGADW_DATA(v) (((v) & 0xff) << 0) +#define BFM_AIC_RGADW_DATA(v) BM_AIC_RGADW_DATA +#define BF_AIC_RGADW_DATA_V(e) BF_AIC_RGADW_DATA(BV_AIC_RGADW_DATA__##e) +#define BFM_AIC_RGADW_DATA_V(v) BM_AIC_RGADW_DATA +#define BP_AIC_RGADW_ICRST 31 +#define BM_AIC_RGADW_ICRST 0x80000000 +#define BF_AIC_RGADW_ICRST(v) (((v) & 0x1) << 31) +#define BFM_AIC_RGADW_ICRST(v) BM_AIC_RGADW_ICRST +#define BF_AIC_RGADW_ICRST_V(e) BF_AIC_RGADW_ICRST(BV_AIC_RGADW_ICRST__##e) +#define BFM_AIC_RGADW_ICRST_V(v) BM_AIC_RGADW_ICRST +#define BP_AIC_RGADW_RGWR 16 +#define BM_AIC_RGADW_RGWR 0x10000 +#define BF_AIC_RGADW_RGWR(v) (((v) & 0x1) << 16) +#define BFM_AIC_RGADW_RGWR(v) BM_AIC_RGADW_RGWR +#define BF_AIC_RGADW_RGWR_V(e) BF_AIC_RGADW_RGWR(BV_AIC_RGADW_RGWR__##e) +#define BFM_AIC_RGADW_RGWR_V(v) BM_AIC_RGADW_RGWR + +#define REG_AIC_RGDATA jz_reg(AIC_RGDATA) +#define JA_AIC_RGDATA (0xb0020000 + 0xa8) +#define JT_AIC_RGDATA JIO_32_RW +#define JN_AIC_RGDATA AIC_RGDATA +#define JI_AIC_RGDATA +#define BP_AIC_RGDATA_DATA 0 +#define BM_AIC_RGDATA_DATA 0xff +#define BF_AIC_RGDATA_DATA(v) (((v) & 0xff) << 0) +#define BFM_AIC_RGDATA_DATA(v) BM_AIC_RGDATA_DATA +#define BF_AIC_RGDATA_DATA_V(e) BF_AIC_RGDATA_DATA(BV_AIC_RGDATA_DATA__##e) +#define BFM_AIC_RGDATA_DATA_V(v) BM_AIC_RGDATA_DATA +#define BP_AIC_RGDATA_IRQ 8 +#define BM_AIC_RGDATA_IRQ 0x100 +#define BF_AIC_RGDATA_IRQ(v) (((v) & 0x1) << 8) +#define BFM_AIC_RGDATA_IRQ(v) BM_AIC_RGDATA_IRQ +#define BF_AIC_RGDATA_IRQ_V(e) BF_AIC_RGDATA_IRQ(BV_AIC_RGDATA_IRQ__##e) +#define BFM_AIC_RGDATA_IRQ_V(v) BM_AIC_RGDATA_IRQ + #endif /* __HEADERGEN_AIC_H__*/ diff --git a/firmware/target/mips/ingenic_x1000/x1000/efuse.h b/firmware/target/mips/ingenic_x1000/x1000/efuse.h new file mode 100644 index 0000000000..8628cfd08b --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/efuse.h @@ -0,0 +1,173 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_EFUSE_H__ +#define __HEADERGEN_EFUSE_H__ + +#include "macro.h" + +#define REG_EFUSE_CTRL jz_reg(EFUSE_CTRL) +#define JA_EFUSE_CTRL (0xb3540000 + 0x0) +#define JT_EFUSE_CTRL JIO_32_RW +#define JN_EFUSE_CTRL EFUSE_CTRL +#define JI_EFUSE_CTRL +#define BP_EFUSE_CTRL_ADDR 21 +#define BM_EFUSE_CTRL_ADDR 0xfe00000 +#define BF_EFUSE_CTRL_ADDR(v) (((v) & 0x7f) << 21) +#define BFM_EFUSE_CTRL_ADDR(v) BM_EFUSE_CTRL_ADDR +#define BF_EFUSE_CTRL_ADDR_V(e) BF_EFUSE_CTRL_ADDR(BV_EFUSE_CTRL_ADDR__##e) +#define BFM_EFUSE_CTRL_ADDR_V(v) BM_EFUSE_CTRL_ADDR +#define BP_EFUSE_CTRL_LENGTH 16 +#define BM_EFUSE_CTRL_LENGTH 0x1f0000 +#define BF_EFUSE_CTRL_LENGTH(v) (((v) & 0x1f) << 16) +#define BFM_EFUSE_CTRL_LENGTH(v) BM_EFUSE_CTRL_LENGTH +#define BF_EFUSE_CTRL_LENGTH_V(e) BF_EFUSE_CTRL_LENGTH(BV_EFUSE_CTRL_LENGTH__##e) +#define BFM_EFUSE_CTRL_LENGTH_V(v) BM_EFUSE_CTRL_LENGTH +#define BP_EFUSE_CTRL_PG_EN 15 +#define BM_EFUSE_CTRL_PG_EN 0x8000 +#define BF_EFUSE_CTRL_PG_EN(v) (((v) & 0x1) << 15) +#define BFM_EFUSE_CTRL_PG_EN(v) BM_EFUSE_CTRL_PG_EN +#define BF_EFUSE_CTRL_PG_EN_V(e) BF_EFUSE_CTRL_PG_EN(BV_EFUSE_CTRL_PG_EN__##e) +#define BFM_EFUSE_CTRL_PG_EN_V(v) BM_EFUSE_CTRL_PG_EN +#define BP_EFUSE_CTRL_WR_EN 1 +#define BM_EFUSE_CTRL_WR_EN 0x2 +#define BF_EFUSE_CTRL_WR_EN(v) (((v) & 0x1) << 1) +#define BFM_EFUSE_CTRL_WR_EN(v) BM_EFUSE_CTRL_WR_EN +#define BF_EFUSE_CTRL_WR_EN_V(e) BF_EFUSE_CTRL_WR_EN(BV_EFUSE_CTRL_WR_EN__##e) +#define BFM_EFUSE_CTRL_WR_EN_V(v) BM_EFUSE_CTRL_WR_EN +#define BP_EFUSE_CTRL_RD_EN 0 +#define BM_EFUSE_CTRL_RD_EN 0x1 +#define BF_EFUSE_CTRL_RD_EN(v) (((v) & 0x1) << 0) +#define BFM_EFUSE_CTRL_RD_EN(v) BM_EFUSE_CTRL_RD_EN +#define BF_EFUSE_CTRL_RD_EN_V(e) BF_EFUSE_CTRL_RD_EN(BV_EFUSE_CTRL_RD_EN__##e) +#define BFM_EFUSE_CTRL_RD_EN_V(v) BM_EFUSE_CTRL_RD_EN + +#define REG_EFUSE_CFG jz_reg(EFUSE_CFG) +#define JA_EFUSE_CFG (0xb3540000 + 0x4) +#define JT_EFUSE_CFG JIO_32_RW +#define JN_EFUSE_CFG EFUSE_CFG +#define JI_EFUSE_CFG +#define BP_EFUSE_CFG_RD_AJD 20 +#define BM_EFUSE_CFG_RD_AJD 0x300000 +#define BF_EFUSE_CFG_RD_AJD(v) (((v) & 0x3) << 20) +#define BFM_EFUSE_CFG_RD_AJD(v) BM_EFUSE_CFG_RD_AJD +#define BF_EFUSE_CFG_RD_AJD_V(e) BF_EFUSE_CFG_RD_AJD(BV_EFUSE_CFG_RD_AJD__##e) +#define BFM_EFUSE_CFG_RD_AJD_V(v) BM_EFUSE_CFG_RD_AJD +#define BP_EFUSE_CFG_RD_STROBE 16 +#define BM_EFUSE_CFG_RD_STROBE 0x70000 +#define BF_EFUSE_CFG_RD_STROBE(v) (((v) & 0x7) << 16) +#define BFM_EFUSE_CFG_RD_STROBE(v) BM_EFUSE_CFG_RD_STROBE +#define BF_EFUSE_CFG_RD_STROBE_V(e) BF_EFUSE_CFG_RD_STROBE(BV_EFUSE_CFG_RD_STROBE__##e) +#define BFM_EFUSE_CFG_RD_STROBE_V(v) BM_EFUSE_CFG_RD_STROBE +#define BP_EFUSE_CFG_WR_ADJ 12 +#define BM_EFUSE_CFG_WR_ADJ 0x3000 +#define BF_EFUSE_CFG_WR_ADJ(v) (((v) & 0x3) << 12) +#define BFM_EFUSE_CFG_WR_ADJ(v) BM_EFUSE_CFG_WR_ADJ +#define BF_EFUSE_CFG_WR_ADJ_V(e) BF_EFUSE_CFG_WR_ADJ(BV_EFUSE_CFG_WR_ADJ__##e) +#define BFM_EFUSE_CFG_WR_ADJ_V(v) BM_EFUSE_CFG_WR_ADJ +#define BP_EFUSE_CFG_WR_STROBE 0 +#define BM_EFUSE_CFG_WR_STROBE 0x1ff +#define BF_EFUSE_CFG_WR_STROBE(v) (((v) & 0x1ff) << 0) +#define BFM_EFUSE_CFG_WR_STROBE(v) BM_EFUSE_CFG_WR_STROBE +#define BF_EFUSE_CFG_WR_STROBE_V(e) BF_EFUSE_CFG_WR_STROBE(BV_EFUSE_CFG_WR_STROBE__##e) +#define BFM_EFUSE_CFG_WR_STROBE_V(v) BM_EFUSE_CFG_WR_STROBE +#define BP_EFUSE_CFG_INT_EN 31 +#define BM_EFUSE_CFG_INT_EN 0x80000000 +#define BF_EFUSE_CFG_INT_EN(v) (((v) & 0x1) << 31) +#define BFM_EFUSE_CFG_INT_EN(v) BM_EFUSE_CFG_INT_EN +#define BF_EFUSE_CFG_INT_EN_V(e) BF_EFUSE_CFG_INT_EN(BV_EFUSE_CFG_INT_EN__##e) +#define BFM_EFUSE_CFG_INT_EN_V(v) BM_EFUSE_CFG_INT_EN + +#define REG_EFUSE_STATE jz_reg(EFUSE_STATE) +#define JA_EFUSE_STATE (0xb3540000 + 0x8) +#define JT_EFUSE_STATE JIO_32_RW +#define JN_EFUSE_STATE EFUSE_STATE +#define JI_EFUSE_STATE +#define BP_EFUSE_STATE_UK_PRT 23 +#define BM_EFUSE_STATE_UK_PRT 0x800000 +#define BF_EFUSE_STATE_UK_PRT(v) (((v) & 0x1) << 23) +#define BFM_EFUSE_STATE_UK_PRT(v) BM_EFUSE_STATE_UK_PRT +#define BF_EFUSE_STATE_UK_PRT_V(e) BF_EFUSE_STATE_UK_PRT(BV_EFUSE_STATE_UK_PRT__##e) +#define BFM_EFUSE_STATE_UK_PRT_V(v) BM_EFUSE_STATE_UK_PRT +#define BP_EFUSE_STATE_NKU_PRT 22 +#define BM_EFUSE_STATE_NKU_PRT 0x400000 +#define BF_EFUSE_STATE_NKU_PRT(v) (((v) & 0x1) << 22) +#define BFM_EFUSE_STATE_NKU_PRT(v) BM_EFUSE_STATE_NKU_PRT +#define BF_EFUSE_STATE_NKU_PRT_V(e) BF_EFUSE_STATE_NKU_PRT(BV_EFUSE_STATE_NKU_PRT__##e) +#define BFM_EFUSE_STATE_NKU_PRT_V(v) BM_EFUSE_STATE_NKU_PRT +#define BP_EFUSE_STATE_EXKEY_EN 21 +#define BM_EFUSE_STATE_EXKEY_EN 0x200000 +#define BF_EFUSE_STATE_EXKEY_EN(v) (((v) & 0x1) << 21) +#define BFM_EFUSE_STATE_EXKEY_EN(v) BM_EFUSE_STATE_EXKEY_EN +#define BF_EFUSE_STATE_EXKEY_EN_V(e) BF_EFUSE_STATE_EXKEY_EN(BV_EFUSE_STATE_EXKEY_EN__##e) +#define BFM_EFUSE_STATE_EXKEY_EN_V(v) BM_EFUSE_STATE_EXKEY_EN +#define BP_EFUSE_STATE_CUSTID_PRT 15 +#define BM_EFUSE_STATE_CUSTID_PRT 0x8000 +#define BF_EFUSE_STATE_CUSTID_PRT(v) (((v) & 0x1) << 15) +#define BFM_EFUSE_STATE_CUSTID_PRT(v) BM_EFUSE_STATE_CUSTID_PRT +#define BF_EFUSE_STATE_CUSTID_PRT_V(e) BF_EFUSE_STATE_CUSTID_PRT(BV_EFUSE_STATE_CUSTID_PRT__##e) +#define BFM_EFUSE_STATE_CUSTID_PRT_V(v) BM_EFUSE_STATE_CUSTID_PRT +#define BP_EFUSE_STATE_CHIPID_PRT 14 +#define BM_EFUSE_STATE_CHIPID_PRT 0x4000 +#define BF_EFUSE_STATE_CHIPID_PRT(v) (((v) & 0x1) << 14) +#define BFM_EFUSE_STATE_CHIPID_PRT(v) BM_EFUSE_STATE_CHIPID_PRT +#define BF_EFUSE_STATE_CHIPID_PRT_V(e) BF_EFUSE_STATE_CHIPID_PRT(BV_EFUSE_STATE_CHIPID_PRT__##e) +#define BFM_EFUSE_STATE_CHIPID_PRT_V(v) BM_EFUSE_STATE_CHIPID_PRT +#define BP_EFUSE_STATE_SECBOOT_PRT 12 +#define BM_EFUSE_STATE_SECBOOT_PRT 0x1000 +#define BF_EFUSE_STATE_SECBOOT_PRT(v) (((v) & 0x1) << 12) +#define BFM_EFUSE_STATE_SECBOOT_PRT(v) BM_EFUSE_STATE_SECBOOT_PRT +#define BF_EFUSE_STATE_SECBOOT_PRT_V(e) BF_EFUSE_STATE_SECBOOT_PRT(BV_EFUSE_STATE_SECBOOT_PRT__##e) +#define BFM_EFUSE_STATE_SECBOOT_PRT_V(v) BM_EFUSE_STATE_SECBOOT_PRT +#define BP_EFUSE_STATE_DIS_JTAG 11 +#define BM_EFUSE_STATE_DIS_JTAG 0x800 +#define BF_EFUSE_STATE_DIS_JTAG(v) (((v) & 0x1) << 11) +#define BFM_EFUSE_STATE_DIS_JTAG(v) BM_EFUSE_STATE_DIS_JTAG +#define BF_EFUSE_STATE_DIS_JTAG_V(e) BF_EFUSE_STATE_DIS_JTAG(BV_EFUSE_STATE_DIS_JTAG__##e) +#define BFM_EFUSE_STATE_DIS_JTAG_V(v) BM_EFUSE_STATE_DIS_JTAG +#define BP_EFUSE_STATE_SECBOOT_EN 8 +#define BM_EFUSE_STATE_SECBOOT_EN 0x100 +#define BF_EFUSE_STATE_SECBOOT_EN(v) (((v) & 0x1) << 8) +#define BFM_EFUSE_STATE_SECBOOT_EN(v) BM_EFUSE_STATE_SECBOOT_EN +#define BF_EFUSE_STATE_SECBOOT_EN_V(e) BF_EFUSE_STATE_SECBOOT_EN(BV_EFUSE_STATE_SECBOOT_EN__##e) +#define BFM_EFUSE_STATE_SECBOOT_EN_V(v) BM_EFUSE_STATE_SECBOOT_EN +#define BP_EFUSE_STATE_WR_DONE 1 +#define BM_EFUSE_STATE_WR_DONE 0x2 +#define BF_EFUSE_STATE_WR_DONE(v) (((v) & 0x1) << 1) +#define BFM_EFUSE_STATE_WR_DONE(v) BM_EFUSE_STATE_WR_DONE +#define BF_EFUSE_STATE_WR_DONE_V(e) BF_EFUSE_STATE_WR_DONE(BV_EFUSE_STATE_WR_DONE__##e) +#define BFM_EFUSE_STATE_WR_DONE_V(v) BM_EFUSE_STATE_WR_DONE +#define BP_EFUSE_STATE_RD_DONE 0 +#define BM_EFUSE_STATE_RD_DONE 0x1 +#define BF_EFUSE_STATE_RD_DONE(v) (((v) & 0x1) << 0) +#define BFM_EFUSE_STATE_RD_DONE(v) BM_EFUSE_STATE_RD_DONE +#define BF_EFUSE_STATE_RD_DONE_V(e) BF_EFUSE_STATE_RD_DONE(BV_EFUSE_STATE_RD_DONE__##e) +#define BFM_EFUSE_STATE_RD_DONE_V(v) BM_EFUSE_STATE_RD_DONE + +#define REG_EFUSE_DATA(_n1) jz_reg(EFUSE_DATA(_n1)) +#define JA_EFUSE_DATA(_n1) (0xb3540000 + 0xc + (_n1) * 0x4) +#define JT_EFUSE_DATA(_n1) JIO_32_RW +#define JN_EFUSE_DATA(_n1) EFUSE_DATA +#define JI_EFUSE_DATA(_n1) (_n1) + +#endif /* __HEADERGEN_EFUSE_H__*/ diff --git a/firmware/target/mips/ingenic_x1000/x1000/pcm.h b/firmware/target/mips/ingenic_x1000/x1000/pcm.h new file mode 100644 index 0000000000..e47a2e5c13 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/pcm.h @@ -0,0 +1,251 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_PCM_H__ +#define __HEADERGEN_PCM_H__ + +#include "macro.h" + +#define REG_PCM_CTL jz_reg(PCM_CTL) +#define JA_PCM_CTL (0xb0071000 + 0x0) +#define JT_PCM_CTL JIO_32_RW +#define JN_PCM_CTL PCM_CTL +#define JI_PCM_CTL +#define BP_PCM_CTL_ERDMA 9 +#define BM_PCM_CTL_ERDMA 0x200 +#define BF_PCM_CTL_ERDMA(v) (((v) & 0x1) << 9) +#define BFM_PCM_CTL_ERDMA(v) BM_PCM_CTL_ERDMA +#define BF_PCM_CTL_ERDMA_V(e) BF_PCM_CTL_ERDMA(BV_PCM_CTL_ERDMA__##e) +#define BFM_PCM_CTL_ERDMA_V(v) BM_PCM_CTL_ERDMA +#define BP_PCM_CTL_ETDMA 8 +#define BM_PCM_CTL_ETDMA 0x100 +#define BF_PCM_CTL_ETDMA(v) (((v) & 0x1) << 8) +#define BFM_PCM_CTL_ETDMA(v) BM_PCM_CTL_ETDMA +#define BF_PCM_CTL_ETDMA_V(e) BF_PCM_CTL_ETDMA(BV_PCM_CTL_ETDMA__##e) +#define BFM_PCM_CTL_ETDMA_V(v) BM_PCM_CTL_ETDMA +#define BP_PCM_CTL_LSMP 7 +#define BM_PCM_CTL_LSMP 0x80 +#define BF_PCM_CTL_LSMP(v) (((v) & 0x1) << 7) +#define BFM_PCM_CTL_LSMP(v) BM_PCM_CTL_LSMP +#define BF_PCM_CTL_LSMP_V(e) BF_PCM_CTL_LSMP(BV_PCM_CTL_LSMP__##e) +#define BFM_PCM_CTL_LSMP_V(v) BM_PCM_CTL_LSMP +#define BP_PCM_CTL_ERPL 6 +#define BM_PCM_CTL_ERPL 0x40 +#define BF_PCM_CTL_ERPL(v) (((v) & 0x1) << 6) +#define BFM_PCM_CTL_ERPL(v) BM_PCM_CTL_ERPL +#define BF_PCM_CTL_ERPL_V(e) BF_PCM_CTL_ERPL(BV_PCM_CTL_ERPL__##e) +#define BFM_PCM_CTL_ERPL_V(v) BM_PCM_CTL_ERPL +#define BP_PCM_CTL_EREC 5 +#define BM_PCM_CTL_EREC 0x20 +#define BF_PCM_CTL_EREC(v) (((v) & 0x1) << 5) +#define BFM_PCM_CTL_EREC(v) BM_PCM_CTL_EREC +#define BF_PCM_CTL_EREC_V(e) BF_PCM_CTL_EREC(BV_PCM_CTL_EREC__##e) +#define BFM_PCM_CTL_EREC_V(v) BM_PCM_CTL_EREC +#define BP_PCM_CTL_FLUSH 4 +#define BM_PCM_CTL_FLUSH 0x10 +#define BF_PCM_CTL_FLUSH(v) (((v) & 0x1) << 4) +#define BFM_PCM_CTL_FLUSH(v) BM_PCM_CTL_FLUSH +#define BF_PCM_CTL_FLUSH_V(e) BF_PCM_CTL_FLUSH(BV_PCM_CTL_FLUSH__##e) +#define BFM_PCM_CTL_FLUSH_V(v) BM_PCM_CTL_FLUSH +#define BP_PCM_CTL_RST 3 +#define BM_PCM_CTL_RST 0x8 +#define BF_PCM_CTL_RST(v) (((v) & 0x1) << 3) +#define BFM_PCM_CTL_RST(v) BM_PCM_CTL_RST +#define BF_PCM_CTL_RST_V(e) BF_PCM_CTL_RST(BV_PCM_CTL_RST__##e) +#define BFM_PCM_CTL_RST_V(v) BM_PCM_CTL_RST +#define BP_PCM_CTL_CLKEN 1 +#define BM_PCM_CTL_CLKEN 0x2 +#define BF_PCM_CTL_CLKEN(v) (((v) & 0x1) << 1) +#define BFM_PCM_CTL_CLKEN(v) BM_PCM_CTL_CLKEN +#define BF_PCM_CTL_CLKEN_V(e) BF_PCM_CTL_CLKEN(BV_PCM_CTL_CLKEN__##e) +#define BFM_PCM_CTL_CLKEN_V(v) BM_PCM_CTL_CLKEN +#define BP_PCM_CTL_PCMEN 0 +#define BM_PCM_CTL_PCMEN 0x1 +#define BF_PCM_CTL_PCMEN(v) (((v) & 0x1) << 0) +#define BFM_PCM_CTL_PCMEN(v) BM_PCM_CTL_PCMEN +#define BF_PCM_CTL_PCMEN_V(e) BF_PCM_CTL_PCMEN(BV_PCM_CTL_PCMEN__##e) +#define BFM_PCM_CTL_PCMEN_V(v) BM_PCM_CTL_PCMEN + +#define REG_PCM_CFG jz_reg(PCM_CFG) +#define JA_PCM_CFG (0xb0071000 + 0x4) +#define JT_PCM_CFG JIO_32_RW +#define JN_PCM_CFG PCM_CFG +#define JI_PCM_CFG +#define BP_PCM_CFG_SLOT 13 +#define BM_PCM_CFG_SLOT 0x6000 +#define BF_PCM_CFG_SLOT(v) (((v) & 0x3) << 13) +#define BFM_PCM_CFG_SLOT(v) BM_PCM_CFG_SLOT +#define BF_PCM_CFG_SLOT_V(e) BF_PCM_CFG_SLOT(BV_PCM_CFG_SLOT__##e) +#define BFM_PCM_CFG_SLOT_V(v) BM_PCM_CFG_SLOT +#define BP_PCM_CFG_RFTH 5 +#define BM_PCM_CFG_RFTH 0x1e0 +#define BF_PCM_CFG_RFTH(v) (((v) & 0xf) << 5) +#define BFM_PCM_CFG_RFTH(v) BM_PCM_CFG_RFTH +#define BF_PCM_CFG_RFTH_V(e) BF_PCM_CFG_RFTH(BV_PCM_CFG_RFTH__##e) +#define BFM_PCM_CFG_RFTH_V(v) BM_PCM_CFG_RFTH +#define BP_PCM_CFG_TFTH 1 +#define BM_PCM_CFG_TFTH 0x1e +#define BF_PCM_CFG_TFTH(v) (((v) & 0xf) << 1) +#define BFM_PCM_CFG_TFTH(v) BM_PCM_CFG_TFTH +#define BF_PCM_CFG_TFTH_V(e) BF_PCM_CFG_TFTH(BV_PCM_CFG_TFTH__##e) +#define BFM_PCM_CFG_TFTH_V(v) BM_PCM_CFG_TFTH +#define BP_PCM_CFG_ISS 12 +#define BM_PCM_CFG_ISS 0x1000 +#define BF_PCM_CFG_ISS(v) (((v) & 0x1) << 12) +#define BFM_PCM_CFG_ISS(v) BM_PCM_CFG_ISS +#define BF_PCM_CFG_ISS_V(e) BF_PCM_CFG_ISS(BV_PCM_CFG_ISS__##e) +#define BFM_PCM_CFG_ISS_V(v) BM_PCM_CFG_ISS +#define BP_PCM_CFG_OSS 11 +#define BM_PCM_CFG_OSS 0x800 +#define BF_PCM_CFG_OSS(v) (((v) & 0x1) << 11) +#define BFM_PCM_CFG_OSS(v) BM_PCM_CFG_OSS +#define BF_PCM_CFG_OSS_V(e) BF_PCM_CFG_OSS(BV_PCM_CFG_OSS__##e) +#define BFM_PCM_CFG_OSS_V(v) BM_PCM_CFG_OSS +#define BP_PCM_CFG_IMSBPOS 10 +#define BM_PCM_CFG_IMSBPOS 0x400 +#define BF_PCM_CFG_IMSBPOS(v) (((v) & 0x1) << 10) +#define BFM_PCM_CFG_IMSBPOS(v) BM_PCM_CFG_IMSBPOS +#define BF_PCM_CFG_IMSBPOS_V(e) BF_PCM_CFG_IMSBPOS(BV_PCM_CFG_IMSBPOS__##e) +#define BFM_PCM_CFG_IMSBPOS_V(v) BM_PCM_CFG_IMSBPOS +#define BP_PCM_CFG_OMSBPOS 9 +#define BM_PCM_CFG_OMSBPOS 0x200 +#define BF_PCM_CFG_OMSBPOS(v) (((v) & 0x1) << 9) +#define BFM_PCM_CFG_OMSBPOS(v) BM_PCM_CFG_OMSBPOS +#define BF_PCM_CFG_OMSBPOS_V(e) BF_PCM_CFG_OMSBPOS(BV_PCM_CFG_OMSBPOS__##e) +#define BFM_PCM_CFG_OMSBPOS_V(v) BM_PCM_CFG_OMSBPOS +#define BP_PCM_CFG_PCMMOD 0 +#define BM_PCM_CFG_PCMMOD 0x1 +#define BF_PCM_CFG_PCMMOD(v) (((v) & 0x1) << 0) +#define BFM_PCM_CFG_PCMMOD(v) BM_PCM_CFG_PCMMOD +#define BF_PCM_CFG_PCMMOD_V(e) BF_PCM_CFG_PCMMOD(BV_PCM_CFG_PCMMOD__##e) +#define BFM_PCM_CFG_PCMMOD_V(v) BM_PCM_CFG_PCMMOD + +#define REG_PCM_DP jz_reg(PCM_DP) +#define JA_PCM_DP (0xb0071000 + 0x8) +#define JT_PCM_DP JIO_32_RW +#define JN_PCM_DP PCM_DP +#define JI_PCM_DP + +#define REG_PCM_INTC jz_reg(PCM_INTC) +#define JA_PCM_INTC (0xb0071000 + 0xc) +#define JT_PCM_INTC JIO_32_RW +#define JN_PCM_INTC PCM_INTC +#define JI_PCM_INTC +#define BP_PCM_INTC_ETFS 3 +#define BM_PCM_INTC_ETFS 0x8 +#define BF_PCM_INTC_ETFS(v) (((v) & 0x1) << 3) +#define BFM_PCM_INTC_ETFS(v) BM_PCM_INTC_ETFS +#define BF_PCM_INTC_ETFS_V(e) BF_PCM_INTC_ETFS(BV_PCM_INTC_ETFS__##e) +#define BFM_PCM_INTC_ETFS_V(v) BM_PCM_INTC_ETFS +#define BP_PCM_INTC_ETUR 2 +#define BM_PCM_INTC_ETUR 0x4 +#define BF_PCM_INTC_ETUR(v) (((v) & 0x1) << 2) +#define BFM_PCM_INTC_ETUR(v) BM_PCM_INTC_ETUR +#define BF_PCM_INTC_ETUR_V(e) BF_PCM_INTC_ETUR(BV_PCM_INTC_ETUR__##e) +#define BFM_PCM_INTC_ETUR_V(v) BM_PCM_INTC_ETUR +#define BP_PCM_INTC_ERFS 1 +#define BM_PCM_INTC_ERFS 0x2 +#define BF_PCM_INTC_ERFS(v) (((v) & 0x1) << 1) +#define BFM_PCM_INTC_ERFS(v) BM_PCM_INTC_ERFS +#define BF_PCM_INTC_ERFS_V(e) BF_PCM_INTC_ERFS(BV_PCM_INTC_ERFS__##e) +#define BFM_PCM_INTC_ERFS_V(v) BM_PCM_INTC_ERFS +#define BP_PCM_INTC_EROR 0 +#define BM_PCM_INTC_EROR 0x1 +#define BF_PCM_INTC_EROR(v) (((v) & 0x1) << 0) +#define BFM_PCM_INTC_EROR(v) BM_PCM_INTC_EROR +#define BF_PCM_INTC_EROR_V(e) BF_PCM_INTC_EROR(BV_PCM_INTC_EROR__##e) +#define BFM_PCM_INTC_EROR_V(v) BM_PCM_INTC_EROR + +#define REG_PCM_INTS jz_reg(PCM_INTS) +#define JA_PCM_INTS (0xb0071000 + 0x10) +#define JT_PCM_INTS JIO_32_RW +#define JN_PCM_INTS PCM_INTS +#define JI_PCM_INTS +#define BP_PCM_INTS_TFL 9 +#define BM_PCM_INTS_TFL 0x3e00 +#define BF_PCM_INTS_TFL(v) (((v) & 0x1f) << 9) +#define BFM_PCM_INTS_TFL(v) BM_PCM_INTS_TFL +#define BF_PCM_INTS_TFL_V(e) BF_PCM_INTS_TFL(BV_PCM_INTS_TFL__##e) +#define BFM_PCM_INTS_TFL_V(v) BM_PCM_INTS_TFL +#define BP_PCM_INTS_RSTS 14 +#define BM_PCM_INTS_RSTS 0x4000 +#define BF_PCM_INTS_RSTS(v) (((v) & 0x1) << 14) +#define BFM_PCM_INTS_RSTS(v) BM_PCM_INTS_RSTS +#define BF_PCM_INTS_RSTS_V(e) BF_PCM_INTS_RSTS(BV_PCM_INTS_RSTS__##e) +#define BFM_PCM_INTS_RSTS_V(v) BM_PCM_INTS_RSTS +#define BP_PCM_INTS_TFS 8 +#define BM_PCM_INTS_TFS 0x100 +#define BF_PCM_INTS_TFS(v) (((v) & 0x1) << 8) +#define BFM_PCM_INTS_TFS(v) BM_PCM_INTS_TFS +#define BF_PCM_INTS_TFS_V(e) BF_PCM_INTS_TFS(BV_PCM_INTS_TFS__##e) +#define BFM_PCM_INTS_TFS_V(v) BM_PCM_INTS_TFS +#define BP_PCM_INTS_TUR 7 +#define BM_PCM_INTS_TUR 0x80 +#define BF_PCM_INTS_TUR(v) (((v) & 0x1) << 7) +#define BFM_PCM_INTS_TUR(v) BM_PCM_INTS_TUR +#define BF_PCM_INTS_TUR_V(e) BF_PCM_INTS_TUR(BV_PCM_INTS_TUR__##e) +#define BFM_PCM_INTS_TUR_V(v) BM_PCM_INTS_TUR +#define BP_PCM_INTS_RFL 2 +#define BM_PCM_INTS_RFL 0x7c +#define BF_PCM_INTS_RFL(v) (((v) & 0x1f) << 2) +#define BFM_PCM_INTS_RFL(v) BM_PCM_INTS_RFL +#define BF_PCM_INTS_RFL_V(e) BF_PCM_INTS_RFL(BV_PCM_INTS_RFL__##e) +#define BFM_PCM_INTS_RFL_V(v) BM_PCM_INTS_RFL +#define BP_PCM_INTS_RFS 1 +#define BM_PCM_INTS_RFS 0x2 +#define BF_PCM_INTS_RFS(v) (((v) & 0x1) << 1) +#define BFM_PCM_INTS_RFS(v) BM_PCM_INTS_RFS +#define BF_PCM_INTS_RFS_V(e) BF_PCM_INTS_RFS(BV_PCM_INTS_RFS__##e) +#define BFM_PCM_INTS_RFS_V(v) BM_PCM_INTS_RFS +#define BP_PCM_INTS_ROR 0 +#define BM_PCM_INTS_ROR 0x1 +#define BF_PCM_INTS_ROR(v) (((v) & 0x1) << 0) +#define BFM_PCM_INTS_ROR(v) BM_PCM_INTS_ROR +#define BF_PCM_INTS_ROR_V(e) BF_PCM_INTS_ROR(BV_PCM_INTS_ROR__##e) +#define BFM_PCM_INTS_ROR_V(v) BM_PCM_INTS_ROR + +#define REG_PCM_DIV jz_reg(PCM_DIV) +#define JA_PCM_DIV (0xb0071000 + 0x14) +#define JT_PCM_DIV JIO_32_RW +#define JN_PCM_DIV PCM_DIV +#define JI_PCM_DIV +#define BP_PCM_DIV_SYNL 11 +#define BM_PCM_DIV_SYNL 0x1f800 +#define BF_PCM_DIV_SYNL(v) (((v) & 0x3f) << 11) +#define BFM_PCM_DIV_SYNL(v) BM_PCM_DIV_SYNL +#define BF_PCM_DIV_SYNL_V(e) BF_PCM_DIV_SYNL(BV_PCM_DIV_SYNL__##e) +#define BFM_PCM_DIV_SYNL_V(v) BM_PCM_DIV_SYNL +#define BP_PCM_DIV_SYNDIV 6 +#define BM_PCM_DIV_SYNDIV 0x7c0 +#define BF_PCM_DIV_SYNDIV(v) (((v) & 0x1f) << 6) +#define BFM_PCM_DIV_SYNDIV(v) BM_PCM_DIV_SYNDIV +#define BF_PCM_DIV_SYNDIV_V(e) BF_PCM_DIV_SYNDIV(BV_PCM_DIV_SYNDIV__##e) +#define BFM_PCM_DIV_SYNDIV_V(v) BM_PCM_DIV_SYNDIV +#define BP_PCM_DIV_CLKDIV 0 +#define BM_PCM_DIV_CLKDIV 0x3f +#define BF_PCM_DIV_CLKDIV(v) (((v) & 0x3f) << 0) +#define BFM_PCM_DIV_CLKDIV(v) BM_PCM_DIV_CLKDIV +#define BF_PCM_DIV_CLKDIV_V(e) BF_PCM_DIV_CLKDIV(BV_PCM_DIV_CLKDIV__##e) +#define BFM_PCM_DIV_CLKDIV_V(v) BM_PCM_DIV_CLKDIV + +#endif /* __HEADERGEN_PCM_H__*/ diff --git a/firmware/target/mips/ingenic_x1000/x1000/ssi.h b/firmware/target/mips/ingenic_x1000/x1000/ssi.h new file mode 100644 index 0000000000..731e73c3a6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ssi.h @@ -0,0 +1,323 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_SSI_H__ +#define __HEADERGEN_SSI_H__ + +#include "macro.h" + +#define REG_SSI_DR jz_reg(SSI_DR) +#define JA_SSI_DR (0xb0043000 + 0x0) +#define JT_SSI_DR JIO_32_RW +#define JN_SSI_DR SSI_DR +#define JI_SSI_DR + +#define REG_SSI_CR0 jz_reg(SSI_CR0) +#define JA_SSI_CR0 (0xb0043000 + 0x4) +#define JT_SSI_CR0 JIO_32_RW +#define JN_SSI_CR0 SSI_CR0 +#define JI_SSI_CR0 +#define BP_SSI_CR0_TENDIAN 18 +#define BM_SSI_CR0_TENDIAN 0xc0000 +#define BF_SSI_CR0_TENDIAN(v) (((v) & 0x3) << 18) +#define BFM_SSI_CR0_TENDIAN(v) BM_SSI_CR0_TENDIAN +#define BF_SSI_CR0_TENDIAN_V(e) BF_SSI_CR0_TENDIAN(BV_SSI_CR0_TENDIAN__##e) +#define BFM_SSI_CR0_TENDIAN_V(v) BM_SSI_CR0_TENDIAN +#define BP_SSI_CR0_RENDIAN 16 +#define BM_SSI_CR0_RENDIAN 0x30000 +#define BF_SSI_CR0_RENDIAN(v) (((v) & 0x3) << 16) +#define BFM_SSI_CR0_RENDIAN(v) BM_SSI_CR0_RENDIAN +#define BF_SSI_CR0_RENDIAN_V(e) BF_SSI_CR0_RENDIAN(BV_SSI_CR0_RENDIAN__##e) +#define BFM_SSI_CR0_RENDIAN_V(v) BM_SSI_CR0_RENDIAN +#define BP_SSI_CR0_SSIE 15 +#define BM_SSI_CR0_SSIE 0x8000 +#define BF_SSI_CR0_SSIE(v) (((v) & 0x1) << 15) +#define BFM_SSI_CR0_SSIE(v) BM_SSI_CR0_SSIE +#define BF_SSI_CR0_SSIE_V(e) BF_SSI_CR0_SSIE(BV_SSI_CR0_SSIE__##e) +#define BFM_SSI_CR0_SSIE_V(v) BM_SSI_CR0_SSIE +#define BP_SSI_CR0_TIE 14 +#define BM_SSI_CR0_TIE 0x4000 +#define BF_SSI_CR0_TIE(v) (((v) & 0x1) << 14) +#define BFM_SSI_CR0_TIE(v) BM_SSI_CR0_TIE +#define BF_SSI_CR0_TIE_V(e) BF_SSI_CR0_TIE(BV_SSI_CR0_TIE__##e) +#define BFM_SSI_CR0_TIE_V(v) BM_SSI_CR0_TIE +#define BP_SSI_CR0_RIE 13 +#define BM_SSI_CR0_RIE 0x2000 +#define BF_SSI_CR0_RIE(v) (((v) & 0x1) << 13) +#define BFM_SSI_CR0_RIE(v) BM_SSI_CR0_RIE +#define BF_SSI_CR0_RIE_V(e) BF_SSI_CR0_RIE(BV_SSI_CR0_RIE__##e) +#define BFM_SSI_CR0_RIE_V(v) BM_SSI_CR0_RIE +#define BP_SSI_CR0_TEIE 12 +#define BM_SSI_CR0_TEIE 0x1000 +#define BF_SSI_CR0_TEIE(v) (((v) & 0x1) << 12) +#define BFM_SSI_CR0_TEIE(v) BM_SSI_CR0_TEIE +#define BF_SSI_CR0_TEIE_V(e) BF_SSI_CR0_TEIE(BV_SSI_CR0_TEIE__##e) +#define BFM_SSI_CR0_TEIE_V(v) BM_SSI_CR0_TEIE +#define BP_SSI_CR0_REIE 11 +#define BM_SSI_CR0_REIE 0x800 +#define BF_SSI_CR0_REIE(v) (((v) & 0x1) << 11) +#define BFM_SSI_CR0_REIE(v) BM_SSI_CR0_REIE +#define BF_SSI_CR0_REIE_V(e) BF_SSI_CR0_REIE(BV_SSI_CR0_REIE__##e) +#define BFM_SSI_CR0_REIE_V(v) BM_SSI_CR0_REIE +#define BP_SSI_CR0_LOOP 10 +#define BM_SSI_CR0_LOOP 0x400 +#define BF_SSI_CR0_LOOP(v) (((v) & 0x1) << 10) +#define BFM_SSI_CR0_LOOP(v) BM_SSI_CR0_LOOP +#define BF_SSI_CR0_LOOP_V(e) BF_SSI_CR0_LOOP(BV_SSI_CR0_LOOP__##e) +#define BFM_SSI_CR0_LOOP_V(v) BM_SSI_CR0_LOOP +#define BP_SSI_CR0_RFINE 9 +#define BM_SSI_CR0_RFINE 0x200 +#define BF_SSI_CR0_RFINE(v) (((v) & 0x1) << 9) +#define BFM_SSI_CR0_RFINE(v) BM_SSI_CR0_RFINE +#define BF_SSI_CR0_RFINE_V(e) BF_SSI_CR0_RFINE(BV_SSI_CR0_RFINE__##e) +#define BFM_SSI_CR0_RFINE_V(v) BM_SSI_CR0_RFINE +#define BP_SSI_CR0_RFINC 8 +#define BM_SSI_CR0_RFINC 0x100 +#define BF_SSI_CR0_RFINC(v) (((v) & 0x1) << 8) +#define BFM_SSI_CR0_RFINC(v) BM_SSI_CR0_RFINC +#define BF_SSI_CR0_RFINC_V(e) BF_SSI_CR0_RFINC(BV_SSI_CR0_RFINC__##e) +#define BFM_SSI_CR0_RFINC_V(v) BM_SSI_CR0_RFINC +#define BP_SSI_CR0_EACLRUN 7 +#define BM_SSI_CR0_EACLRUN 0x80 +#define BF_SSI_CR0_EACLRUN(v) (((v) & 0x1) << 7) +#define BFM_SSI_CR0_EACLRUN(v) BM_SSI_CR0_EACLRUN +#define BF_SSI_CR0_EACLRUN_V(e) BF_SSI_CR0_EACLRUN(BV_SSI_CR0_EACLRUN__##e) +#define BFM_SSI_CR0_EACLRUN_V(v) BM_SSI_CR0_EACLRUN +#define BP_SSI_CR0_FSEL 6 +#define BM_SSI_CR0_FSEL 0x40 +#define BF_SSI_CR0_FSEL(v) (((v) & 0x1) << 6) +#define BFM_SSI_CR0_FSEL(v) BM_SSI_CR0_FSEL +#define BF_SSI_CR0_FSEL_V(e) BF_SSI_CR0_FSEL(BV_SSI_CR0_FSEL__##e) +#define BFM_SSI_CR0_FSEL_V(v) BM_SSI_CR0_FSEL +#define BP_SSI_CR0_VRCNT 4 +#define BM_SSI_CR0_VRCNT 0x10 +#define BF_SSI_CR0_VRCNT(v) (((v) & 0x1) << 4) +#define BFM_SSI_CR0_VRCNT(v) BM_SSI_CR0_VRCNT +#define BF_SSI_CR0_VRCNT_V(e) BF_SSI_CR0_VRCNT(BV_SSI_CR0_VRCNT__##e) +#define BFM_SSI_CR0_VRCNT_V(v) BM_SSI_CR0_VRCNT +#define BP_SSI_CR0_TFMODE 3 +#define BM_SSI_CR0_TFMODE 0x8 +#define BF_SSI_CR0_TFMODE(v) (((v) & 0x1) << 3) +#define BFM_SSI_CR0_TFMODE(v) BM_SSI_CR0_TFMODE +#define BF_SSI_CR0_TFMODE_V(e) BF_SSI_CR0_TFMODE(BV_SSI_CR0_TFMODE__##e) +#define BFM_SSI_CR0_TFMODE_V(v) BM_SSI_CR0_TFMODE +#define BP_SSI_CR0_TFLUSH 2 +#define BM_SSI_CR0_TFLUSH 0x4 +#define BF_SSI_CR0_TFLUSH(v) (((v) & 0x1) << 2) +#define BFM_SSI_CR0_TFLUSH(v) BM_SSI_CR0_TFLUSH +#define BF_SSI_CR0_TFLUSH_V(e) BF_SSI_CR0_TFLUSH(BV_SSI_CR0_TFLUSH__##e) +#define BFM_SSI_CR0_TFLUSH_V(v) BM_SSI_CR0_TFLUSH +#define BP_SSI_CR0_RFLUSH 1 +#define BM_SSI_CR0_RFLUSH 0x2 +#define BF_SSI_CR0_RFLUSH(v) (((v) & 0x1) << 1) +#define BFM_SSI_CR0_RFLUSH(v) BM_SSI_CR0_RFLUSH +#define BF_SSI_CR0_RFLUSH_V(e) BF_SSI_CR0_RFLUSH(BV_SSI_CR0_RFLUSH__##e) +#define BFM_SSI_CR0_RFLUSH_V(v) BM_SSI_CR0_RFLUSH +#define BP_SSI_CR0_DISREV 0 +#define BM_SSI_CR0_DISREV 0x1 +#define BF_SSI_CR0_DISREV(v) (((v) & 0x1) << 0) +#define BFM_SSI_CR0_DISREV(v) BM_SSI_CR0_DISREV +#define BF_SSI_CR0_DISREV_V(e) BF_SSI_CR0_DISREV(BV_SSI_CR0_DISREV__##e) +#define BFM_SSI_CR0_DISREV_V(v) BM_SSI_CR0_DISREV + +#define REG_SSI_CR1 jz_reg(SSI_CR1) +#define JA_SSI_CR1 (0xb0043000 + 0x8) +#define JT_SSI_CR1 JIO_32_RW +#define JN_SSI_CR1 SSI_CR1 +#define JI_SSI_CR1 +#define BP_SSI_CR1_FRMHL 30 +#define BM_SSI_CR1_FRMHL 0xc0000000 +#define BF_SSI_CR1_FRMHL(v) (((v) & 0x3) << 30) +#define BFM_SSI_CR1_FRMHL(v) BM_SSI_CR1_FRMHL +#define BF_SSI_CR1_FRMHL_V(e) BF_SSI_CR1_FRMHL(BV_SSI_CR1_FRMHL__##e) +#define BFM_SSI_CR1_FRMHL_V(v) BM_SSI_CR1_FRMHL +#define BP_SSI_CR1_TFVCK 28 +#define BM_SSI_CR1_TFVCK 0x30000000 +#define BF_SSI_CR1_TFVCK(v) (((v) & 0x3) << 28) +#define BFM_SSI_CR1_TFVCK(v) BM_SSI_CR1_TFVCK +#define BF_SSI_CR1_TFVCK_V(e) BF_SSI_CR1_TFVCK(BV_SSI_CR1_TFVCK__##e) +#define BFM_SSI_CR1_TFVCK_V(v) BM_SSI_CR1_TFVCK +#define BP_SSI_CR1_TCKFI 26 +#define BM_SSI_CR1_TCKFI 0xc000000 +#define BF_SSI_CR1_TCKFI(v) (((v) & 0x3) << 26) +#define BFM_SSI_CR1_TCKFI(v) BM_SSI_CR1_TCKFI +#define BF_SSI_CR1_TCKFI_V(e) BF_SSI_CR1_TCKFI(BV_SSI_CR1_TCKFI__##e) +#define BFM_SSI_CR1_TCKFI_V(v) BM_SSI_CR1_TCKFI +#define BP_SSI_CR1_FMAT 20 +#define BM_SSI_CR1_FMAT 0x300000 +#define BF_SSI_CR1_FMAT(v) (((v) & 0x3) << 20) +#define BFM_SSI_CR1_FMAT(v) BM_SSI_CR1_FMAT +#define BF_SSI_CR1_FMAT_V(e) BF_SSI_CR1_FMAT(BV_SSI_CR1_FMAT__##e) +#define BFM_SSI_CR1_FMAT_V(v) BM_SSI_CR1_FMAT +#define BP_SSI_CR1_TTRG 16 +#define BM_SSI_CR1_TTRG 0xf0000 +#define BF_SSI_CR1_TTRG(v) (((v) & 0xf) << 16) +#define BFM_SSI_CR1_TTRG(v) BM_SSI_CR1_TTRG +#define BF_SSI_CR1_TTRG_V(e) BF_SSI_CR1_TTRG(BV_SSI_CR1_TTRG__##e) +#define BFM_SSI_CR1_TTRG_V(v) BM_SSI_CR1_TTRG +#define BP_SSI_CR1_MCOM 12 +#define BM_SSI_CR1_MCOM 0xf000 +#define BF_SSI_CR1_MCOM(v) (((v) & 0xf) << 12) +#define BFM_SSI_CR1_MCOM(v) BM_SSI_CR1_MCOM +#define BF_SSI_CR1_MCOM_V(e) BF_SSI_CR1_MCOM(BV_SSI_CR1_MCOM__##e) +#define BFM_SSI_CR1_MCOM_V(v) BM_SSI_CR1_MCOM +#define BP_SSI_CR1_RTRG 8 +#define BM_SSI_CR1_RTRG 0xf00 +#define BF_SSI_CR1_RTRG(v) (((v) & 0xf) << 8) +#define BFM_SSI_CR1_RTRG(v) BM_SSI_CR1_RTRG +#define BF_SSI_CR1_RTRG_V(e) BF_SSI_CR1_RTRG(BV_SSI_CR1_RTRG__##e) +#define BFM_SSI_CR1_RTRG_V(v) BM_SSI_CR1_RTRG +#define BP_SSI_CR1_FLEN 3 +#define BM_SSI_CR1_FLEN 0xf8 +#define BF_SSI_CR1_FLEN(v) (((v) & 0x1f) << 3) +#define BFM_SSI_CR1_FLEN(v) BM_SSI_CR1_FLEN +#define BF_SSI_CR1_FLEN_V(e) BF_SSI_CR1_FLEN(BV_SSI_CR1_FLEN__##e) +#define BFM_SSI_CR1_FLEN_V(v) BM_SSI_CR1_FLEN +#define BP_SSI_CR1_ITFRM 24 +#define BM_SSI_CR1_ITFRM 0x1000000 +#define BF_SSI_CR1_ITFRM(v) (((v) & 0x1) << 24) +#define BFM_SSI_CR1_ITFRM(v) BM_SSI_CR1_ITFRM +#define BF_SSI_CR1_ITFRM_V(e) BF_SSI_CR1_ITFRM(BV_SSI_CR1_ITFRM__##e) +#define BFM_SSI_CR1_ITFRM_V(v) BM_SSI_CR1_ITFRM +#define BP_SSI_CR1_UNFIN 23 +#define BM_SSI_CR1_UNFIN 0x800000 +#define BF_SSI_CR1_UNFIN(v) (((v) & 0x1) << 23) +#define BFM_SSI_CR1_UNFIN(v) BM_SSI_CR1_UNFIN +#define BF_SSI_CR1_UNFIN_V(e) BF_SSI_CR1_UNFIN(BV_SSI_CR1_UNFIN__##e) +#define BFM_SSI_CR1_UNFIN_V(v) BM_SSI_CR1_UNFIN +#define BP_SSI_CR1_PHA 1 +#define BM_SSI_CR1_PHA 0x2 +#define BF_SSI_CR1_PHA(v) (((v) & 0x1) << 1) +#define BFM_SSI_CR1_PHA(v) BM_SSI_CR1_PHA +#define BF_SSI_CR1_PHA_V(e) BF_SSI_CR1_PHA(BV_SSI_CR1_PHA__##e) +#define BFM_SSI_CR1_PHA_V(v) BM_SSI_CR1_PHA +#define BP_SSI_CR1_POL 0 +#define BM_SSI_CR1_POL 0x1 +#define BF_SSI_CR1_POL(v) (((v) & 0x1) << 0) +#define BFM_SSI_CR1_POL(v) BM_SSI_CR1_POL +#define BF_SSI_CR1_POL_V(e) BF_SSI_CR1_POL(BV_SSI_CR1_POL__##e) +#define BFM_SSI_CR1_POL_V(v) BM_SSI_CR1_POL + +#define REG_SSI_SR jz_reg(SSI_SR) +#define JA_SSI_SR (0xb0043000 + 0xc) +#define JT_SSI_SR JIO_32_RW +#define JN_SSI_SR SSI_SR +#define JI_SSI_SR +#define BP_SSI_SR_TFIFO_NUM 16 +#define BM_SSI_SR_TFIFO_NUM 0x1ff0000 +#define BF_SSI_SR_TFIFO_NUM(v) (((v) & 0x1ff) << 16) +#define BFM_SSI_SR_TFIFO_NUM(v) BM_SSI_SR_TFIFO_NUM +#define BF_SSI_SR_TFIFO_NUM_V(e) BF_SSI_SR_TFIFO_NUM(BV_SSI_SR_TFIFO_NUM__##e) +#define BFM_SSI_SR_TFIFO_NUM_V(v) BM_SSI_SR_TFIFO_NUM +#define BP_SSI_SR_RFIFO_NUM 8 +#define BM_SSI_SR_RFIFO_NUM 0xff00 +#define BF_SSI_SR_RFIFO_NUM(v) (((v) & 0xff) << 8) +#define BFM_SSI_SR_RFIFO_NUM(v) BM_SSI_SR_RFIFO_NUM +#define BF_SSI_SR_RFIFO_NUM_V(e) BF_SSI_SR_RFIFO_NUM(BV_SSI_SR_RFIFO_NUM__##e) +#define BFM_SSI_SR_RFIFO_NUM_V(v) BM_SSI_SR_RFIFO_NUM +#define BP_SSI_SR_END 7 +#define BM_SSI_SR_END 0x80 +#define BF_SSI_SR_END(v) (((v) & 0x1) << 7) +#define BFM_SSI_SR_END(v) BM_SSI_SR_END +#define BF_SSI_SR_END_V(e) BF_SSI_SR_END(BV_SSI_SR_END__##e) +#define BFM_SSI_SR_END_V(v) BM_SSI_SR_END +#define BP_SSI_SR_BUSY 6 +#define BM_SSI_SR_BUSY 0x40 +#define BF_SSI_SR_BUSY(v) (((v) & 0x1) << 6) +#define BFM_SSI_SR_BUSY(v) BM_SSI_SR_BUSY +#define BF_SSI_SR_BUSY_V(e) BF_SSI_SR_BUSY(BV_SSI_SR_BUSY__##e) +#define BFM_SSI_SR_BUSY_V(v) BM_SSI_SR_BUSY +#define BP_SSI_SR_TFF 5 +#define BM_SSI_SR_TFF 0x20 +#define BF_SSI_SR_TFF(v) (((v) & 0x1) << 5) +#define BFM_SSI_SR_TFF(v) BM_SSI_SR_TFF +#define BF_SSI_SR_TFF_V(e) BF_SSI_SR_TFF(BV_SSI_SR_TFF__##e) +#define BFM_SSI_SR_TFF_V(v) BM_SSI_SR_TFF +#define BP_SSI_SR_RFE 4 +#define BM_SSI_SR_RFE 0x10 +#define BF_SSI_SR_RFE(v) (((v) & 0x1) << 4) +#define BFM_SSI_SR_RFE(v) BM_SSI_SR_RFE +#define BF_SSI_SR_RFE_V(e) BF_SSI_SR_RFE(BV_SSI_SR_RFE__##e) +#define BFM_SSI_SR_RFE_V(v) BM_SSI_SR_RFE +#define BP_SSI_SR_TFHE 3 +#define BM_SSI_SR_TFHE 0x8 +#define BF_SSI_SR_TFHE(v) (((v) & 0x1) << 3) +#define BFM_SSI_SR_TFHE(v) BM_SSI_SR_TFHE +#define BF_SSI_SR_TFHE_V(e) BF_SSI_SR_TFHE(BV_SSI_SR_TFHE__##e) +#define BFM_SSI_SR_TFHE_V(v) BM_SSI_SR_TFHE +#define BP_SSI_SR_RFHF 2 +#define BM_SSI_SR_RFHF 0x4 +#define BF_SSI_SR_RFHF(v) (((v) & 0x1) << 2) +#define BFM_SSI_SR_RFHF(v) BM_SSI_SR_RFHF +#define BF_SSI_SR_RFHF_V(e) BF_SSI_SR_RFHF(BV_SSI_SR_RFHF__##e) +#define BFM_SSI_SR_RFHF_V(v) BM_SSI_SR_RFHF +#define BP_SSI_SR_UNDR 1 +#define BM_SSI_SR_UNDR 0x2 +#define BF_SSI_SR_UNDR(v) (((v) & 0x1) << 1) +#define BFM_SSI_SR_UNDR(v) BM_SSI_SR_UNDR +#define BF_SSI_SR_UNDR_V(e) BF_SSI_SR_UNDR(BV_SSI_SR_UNDR__##e) +#define BFM_SSI_SR_UNDR_V(v) BM_SSI_SR_UNDR +#define BP_SSI_SR_OVER 0 +#define BM_SSI_SR_OVER 0x1 +#define BF_SSI_SR_OVER(v) (((v) & 0x1) << 0) +#define BFM_SSI_SR_OVER(v) BM_SSI_SR_OVER +#define BF_SSI_SR_OVER_V(e) BF_SSI_SR_OVER(BV_SSI_SR_OVER__##e) +#define BFM_SSI_SR_OVER_V(v) BM_SSI_SR_OVER + +#define REG_SSI_ITR jz_reg(SSI_ITR) +#define JA_SSI_ITR (0xb0043000 + 0x10) +#define JT_SSI_ITR JIO_32_RW +#define JN_SSI_ITR SSI_ITR +#define JI_SSI_ITR +#define BP_SSI_ITR_IVLTM 0 +#define BM_SSI_ITR_IVLTM 0x7fff +#define BF_SSI_ITR_IVLTM(v) (((v) & 0x7fff) << 0) +#define BFM_SSI_ITR_IVLTM(v) BM_SSI_ITR_IVLTM +#define BF_SSI_ITR_IVLTM_V(e) BF_SSI_ITR_IVLTM(BV_SSI_ITR_IVLTM__##e) +#define BFM_SSI_ITR_IVLTM_V(v) BM_SSI_ITR_IVLTM +#define BP_SSI_ITR_CNTCLK 15 +#define BM_SSI_ITR_CNTCLK 0x8000 +#define BF_SSI_ITR_CNTCLK(v) (((v) & 0x1) << 15) +#define BFM_SSI_ITR_CNTCLK(v) BM_SSI_ITR_CNTCLK +#define BF_SSI_ITR_CNTCLK_V(e) BF_SSI_ITR_CNTCLK(BV_SSI_ITR_CNTCLK__##e) +#define BFM_SSI_ITR_CNTCLK_V(v) BM_SSI_ITR_CNTCLK + +#define REG_SSI_ICR jz_reg(SSI_ICR) +#define JA_SSI_ICR (0xb0043000 + 0x14) +#define JT_SSI_ICR JIO_32_RW +#define JN_SSI_ICR SSI_ICR +#define JI_SSI_ICR + +#define REG_SSI_GR jz_reg(SSI_GR) +#define JA_SSI_GR (0xb0043000 + 0x18) +#define JT_SSI_GR JIO_32_RW +#define JN_SSI_GR SSI_GR +#define JI_SSI_GR + +#define REG_SSI_RCNT jz_reg(SSI_RCNT) +#define JA_SSI_RCNT (0xb0043000 + 0x1c) +#define JT_SSI_RCNT JIO_32_RW +#define JN_SSI_RCNT SSI_RCNT +#define JI_SSI_RCNT + +#endif /* __HEADERGEN_SSI_H__*/ diff --git a/firmware/target/mips/ingenic_x1000/x1000/uart.h b/firmware/target/mips/ingenic_x1000/x1000/uart.h new file mode 100644 index 0000000000..6b42740bb7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/uart.h @@ -0,0 +1,390 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_UART_H__ +#define __HEADERGEN_UART_H__ + +#include "macro.h" + +#define REG_UART_URBR(_n1) jz_reg(UART_URBR(_n1)) +#define JA_UART_URBR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) +#define JT_UART_URBR(_n1) JIO_32_RW +#define JN_UART_URBR(_n1) UART_URBR +#define JI_UART_URBR(_n1) (_n1) + +#define REG_UART_UTHR(_n1) jz_reg(UART_UTHR(_n1)) +#define JA_UART_UTHR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) +#define JT_UART_UTHR(_n1) JIO_32_RW +#define JN_UART_UTHR(_n1) UART_UTHR +#define JI_UART_UTHR(_n1) (_n1) + +#define REG_UART_UDLLR(_n1) jz_reg(UART_UDLLR(_n1)) +#define JA_UART_UDLLR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x0) +#define JT_UART_UDLLR(_n1) JIO_32_RW +#define JN_UART_UDLLR(_n1) UART_UDLLR +#define JI_UART_UDLLR(_n1) (_n1) + +#define REG_UART_UDLHR(_n1) jz_reg(UART_UDLHR(_n1)) +#define JA_UART_UDLHR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x4) +#define JT_UART_UDLHR(_n1) JIO_32_RW +#define JN_UART_UDLHR(_n1) UART_UDLHR +#define JI_UART_UDLHR(_n1) (_n1) + +#define REG_UART_UIER(_n1) jz_reg(UART_UIER(_n1)) +#define JA_UART_UIER(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x4) +#define JT_UART_UIER(_n1) JIO_32_RW +#define JN_UART_UIER(_n1) UART_UIER +#define JI_UART_UIER(_n1) (_n1) +#define BP_UART_UIER_RTOIE 4 +#define BM_UART_UIER_RTOIE 0x10 +#define BF_UART_UIER_RTOIE(v) (((v) & 0x1) << 4) +#define BFM_UART_UIER_RTOIE(v) BM_UART_UIER_RTOIE +#define BF_UART_UIER_RTOIE_V(e) BF_UART_UIER_RTOIE(BV_UART_UIER_RTOIE__##e) +#define BFM_UART_UIER_RTOIE_V(v) BM_UART_UIER_RTOIE +#define BP_UART_UIER_MSIE 3 +#define BM_UART_UIER_MSIE 0x8 +#define BF_UART_UIER_MSIE(v) (((v) & 0x1) << 3) +#define BFM_UART_UIER_MSIE(v) BM_UART_UIER_MSIE +#define BF_UART_UIER_MSIE_V(e) BF_UART_UIER_MSIE(BV_UART_UIER_MSIE__##e) +#define BFM_UART_UIER_MSIE_V(v) BM_UART_UIER_MSIE +#define BP_UART_UIER_RLSIE 2 +#define BM_UART_UIER_RLSIE 0x4 +#define BF_UART_UIER_RLSIE(v) (((v) & 0x1) << 2) +#define BFM_UART_UIER_RLSIE(v) BM_UART_UIER_RLSIE +#define BF_UART_UIER_RLSIE_V(e) BF_UART_UIER_RLSIE(BV_UART_UIER_RLSIE__##e) +#define BFM_UART_UIER_RLSIE_V(v) BM_UART_UIER_RLSIE +#define BP_UART_UIER_TDRIE 1 +#define BM_UART_UIER_TDRIE 0x2 +#define BF_UART_UIER_TDRIE(v) (((v) & 0x1) << 1) +#define BFM_UART_UIER_TDRIE(v) BM_UART_UIER_TDRIE +#define BF_UART_UIER_TDRIE_V(e) BF_UART_UIER_TDRIE(BV_UART_UIER_TDRIE__##e) +#define BFM_UART_UIER_TDRIE_V(v) BM_UART_UIER_TDRIE +#define BP_UART_UIER_RDRIE 0 +#define BM_UART_UIER_RDRIE 0x1 +#define BF_UART_UIER_RDRIE(v) (((v) & 0x1) << 0) +#define BFM_UART_UIER_RDRIE(v) BM_UART_UIER_RDRIE +#define BF_UART_UIER_RDRIE_V(e) BF_UART_UIER_RDRIE(BV_UART_UIER_RDRIE__##e) +#define BFM_UART_UIER_RDRIE_V(v) BM_UART_UIER_RDRIE + +#define REG_UART_UIIR(_n1) jz_reg(UART_UIIR(_n1)) +#define JA_UART_UIIR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x8) +#define JT_UART_UIIR(_n1) JIO_32_RW +#define JN_UART_UIIR(_n1) UART_UIIR +#define JI_UART_UIIR(_n1) (_n1) +#define BP_UART_UIIR_FFMSEL 6 +#define BM_UART_UIIR_FFMSEL 0xc0 +#define BV_UART_UIIR_FFMSEL__NON_FIFO_MODE 0x0 +#define BV_UART_UIIR_FFMSEL__FIFO_MODE 0x1 +#define BF_UART_UIIR_FFMSEL(v) (((v) & 0x3) << 6) +#define BFM_UART_UIIR_FFMSEL(v) BM_UART_UIIR_FFMSEL +#define BF_UART_UIIR_FFMSEL_V(e) BF_UART_UIIR_FFMSEL(BV_UART_UIIR_FFMSEL__##e) +#define BFM_UART_UIIR_FFMSEL_V(v) BM_UART_UIIR_FFMSEL +#define BP_UART_UIIR_INID 1 +#define BM_UART_UIIR_INID 0xe +#define BV_UART_UIIR_INID__MODEM_STATUS 0x0 +#define BV_UART_UIIR_INID__TRANSMIT_DATA_REQ 0x1 +#define BV_UART_UIIR_INID__RECEIVE_DATA_READY 0x2 +#define BV_UART_UIIR_INID__RECEIVE_LINE_STATUS 0x3 +#define BV_UART_UIIR_INID__RECEIVE_TIME_OUT 0x6 +#define BF_UART_UIIR_INID(v) (((v) & 0x7) << 1) +#define BFM_UART_UIIR_INID(v) BM_UART_UIIR_INID +#define BF_UART_UIIR_INID_V(e) BF_UART_UIIR_INID(BV_UART_UIIR_INID__##e) +#define BFM_UART_UIIR_INID_V(v) BM_UART_UIIR_INID +#define BP_UART_UIIR_INPEND 0 +#define BM_UART_UIIR_INPEND 0x1 +#define BF_UART_UIIR_INPEND(v) (((v) & 0x1) << 0) +#define BFM_UART_UIIR_INPEND(v) BM_UART_UIIR_INPEND +#define BF_UART_UIIR_INPEND_V(e) BF_UART_UIIR_INPEND(BV_UART_UIIR_INPEND__##e) +#define BFM_UART_UIIR_INPEND_V(v) BM_UART_UIIR_INPEND + +#define REG_UART_UFCR(_n1) jz_reg(UART_UFCR(_n1)) +#define JA_UART_UFCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x8) +#define JT_UART_UFCR(_n1) JIO_32_RW +#define JN_UART_UFCR(_n1) UART_UFCR +#define JI_UART_UFCR(_n1) (_n1) +#define BP_UART_UFCR_RDTR 6 +#define BM_UART_UFCR_RDTR 0xc0 +#define BV_UART_UFCR_RDTR__1BYTE 0x0 +#define BV_UART_UFCR_RDTR__16BYTE 0x1 +#define BV_UART_UFCR_RDTR__32BYTE 0x2 +#define BV_UART_UFCR_RDTR__60BYTE 0x3 +#define BF_UART_UFCR_RDTR(v) (((v) & 0x3) << 6) +#define BFM_UART_UFCR_RDTR(v) BM_UART_UFCR_RDTR +#define BF_UART_UFCR_RDTR_V(e) BF_UART_UFCR_RDTR(BV_UART_UFCR_RDTR__##e) +#define BFM_UART_UFCR_RDTR_V(v) BM_UART_UFCR_RDTR +#define BP_UART_UFCR_UME 4 +#define BM_UART_UFCR_UME 0x10 +#define BF_UART_UFCR_UME(v) (((v) & 0x1) << 4) +#define BFM_UART_UFCR_UME(v) BM_UART_UFCR_UME +#define BF_UART_UFCR_UME_V(e) BF_UART_UFCR_UME(BV_UART_UFCR_UME__##e) +#define BFM_UART_UFCR_UME_V(v) BM_UART_UFCR_UME +#define BP_UART_UFCR_DME 3 +#define BM_UART_UFCR_DME 0x8 +#define BF_UART_UFCR_DME(v) (((v) & 0x1) << 3) +#define BFM_UART_UFCR_DME(v) BM_UART_UFCR_DME +#define BF_UART_UFCR_DME_V(e) BF_UART_UFCR_DME(BV_UART_UFCR_DME__##e) +#define BFM_UART_UFCR_DME_V(v) BM_UART_UFCR_DME +#define BP_UART_UFCR_TFRT 2 +#define BM_UART_UFCR_TFRT 0x4 +#define BF_UART_UFCR_TFRT(v) (((v) & 0x1) << 2) +#define BFM_UART_UFCR_TFRT(v) BM_UART_UFCR_TFRT +#define BF_UART_UFCR_TFRT_V(e) BF_UART_UFCR_TFRT(BV_UART_UFCR_TFRT__##e) +#define BFM_UART_UFCR_TFRT_V(v) BM_UART_UFCR_TFRT +#define BP_UART_UFCR_RFRT 1 +#define BM_UART_UFCR_RFRT 0x2 +#define BF_UART_UFCR_RFRT(v) (((v) & 0x1) << 1) +#define BFM_UART_UFCR_RFRT(v) BM_UART_UFCR_RFRT +#define BF_UART_UFCR_RFRT_V(e) BF_UART_UFCR_RFRT(BV_UART_UFCR_RFRT__##e) +#define BFM_UART_UFCR_RFRT_V(v) BM_UART_UFCR_RFRT +#define BP_UART_UFCR_FME 0 +#define BM_UART_UFCR_FME 0x1 +#define BF_UART_UFCR_FME(v) (((v) & 0x1) << 0) +#define BFM_UART_UFCR_FME(v) BM_UART_UFCR_FME +#define BF_UART_UFCR_FME_V(e) BF_UART_UFCR_FME(BV_UART_UFCR_FME__##e) +#define BFM_UART_UFCR_FME_V(v) BM_UART_UFCR_FME + +#define REG_UART_ULCR(_n1) jz_reg(UART_ULCR(_n1)) +#define JA_UART_ULCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0xc) +#define JT_UART_ULCR(_n1) JIO_32_RW +#define JN_UART_ULCR(_n1) UART_ULCR +#define JI_UART_ULCR(_n1) (_n1) +#define BP_UART_ULCR_WLS 0 +#define BM_UART_ULCR_WLS 0x3 +#define BV_UART_ULCR_WLS__5BITS 0x0 +#define BV_UART_ULCR_WLS__6BITS 0x1 +#define BV_UART_ULCR_WLS__7BITS 0x2 +#define BV_UART_ULCR_WLS__8BITS 0x3 +#define BF_UART_ULCR_WLS(v) (((v) & 0x3) << 0) +#define BFM_UART_ULCR_WLS(v) BM_UART_ULCR_WLS +#define BF_UART_ULCR_WLS_V(e) BF_UART_ULCR_WLS(BV_UART_ULCR_WLS__##e) +#define BFM_UART_ULCR_WLS_V(v) BM_UART_ULCR_WLS +#define BP_UART_ULCR_DLAB 7 +#define BM_UART_ULCR_DLAB 0x80 +#define BF_UART_ULCR_DLAB(v) (((v) & 0x1) << 7) +#define BFM_UART_ULCR_DLAB(v) BM_UART_ULCR_DLAB +#define BF_UART_ULCR_DLAB_V(e) BF_UART_ULCR_DLAB(BV_UART_ULCR_DLAB__##e) +#define BFM_UART_ULCR_DLAB_V(v) BM_UART_ULCR_DLAB +#define BP_UART_ULCR_SBK 6 +#define BM_UART_ULCR_SBK 0x40 +#define BF_UART_ULCR_SBK(v) (((v) & 0x1) << 6) +#define BFM_UART_ULCR_SBK(v) BM_UART_ULCR_SBK +#define BF_UART_ULCR_SBK_V(e) BF_UART_ULCR_SBK(BV_UART_ULCR_SBK__##e) +#define BFM_UART_ULCR_SBK_V(v) BM_UART_ULCR_SBK +#define BP_UART_ULCR_STPAR 5 +#define BM_UART_ULCR_STPAR 0x20 +#define BF_UART_ULCR_STPAR(v) (((v) & 0x1) << 5) +#define BFM_UART_ULCR_STPAR(v) BM_UART_ULCR_STPAR +#define BF_UART_ULCR_STPAR_V(e) BF_UART_ULCR_STPAR(BV_UART_ULCR_STPAR__##e) +#define BFM_UART_ULCR_STPAR_V(v) BM_UART_ULCR_STPAR +#define BP_UART_ULCR_PARM 4 +#define BM_UART_ULCR_PARM 0x10 +#define BV_UART_ULCR_PARM__ODD 0x0 +#define BV_UART_ULCR_PARM__EVEN 0x1 +#define BF_UART_ULCR_PARM(v) (((v) & 0x1) << 4) +#define BFM_UART_ULCR_PARM(v) BM_UART_ULCR_PARM +#define BF_UART_ULCR_PARM_V(e) BF_UART_ULCR_PARM(BV_UART_ULCR_PARM__##e) +#define BFM_UART_ULCR_PARM_V(v) BM_UART_ULCR_PARM +#define BP_UART_ULCR_PARE 3 +#define BM_UART_ULCR_PARE 0x8 +#define BF_UART_ULCR_PARE(v) (((v) & 0x1) << 3) +#define BFM_UART_ULCR_PARE(v) BM_UART_ULCR_PARE +#define BF_UART_ULCR_PARE_V(e) BF_UART_ULCR_PARE(BV_UART_ULCR_PARE__##e) +#define BFM_UART_ULCR_PARE_V(v) BM_UART_ULCR_PARE +#define BP_UART_ULCR_SBLS 2 +#define BM_UART_ULCR_SBLS 0x4 +#define BV_UART_ULCR_SBLS__1_STOP_BIT 0x0 +#define BV_UART_ULCR_SBLS__2_STOP_BITS 0x1 +#define BF_UART_ULCR_SBLS(v) (((v) & 0x1) << 2) +#define BFM_UART_ULCR_SBLS(v) BM_UART_ULCR_SBLS +#define BF_UART_ULCR_SBLS_V(e) BF_UART_ULCR_SBLS(BV_UART_ULCR_SBLS__##e) +#define BFM_UART_ULCR_SBLS_V(v) BM_UART_ULCR_SBLS + +#define REG_UART_UMCR(_n1) jz_reg(UART_UMCR(_n1)) +#define JA_UART_UMCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x10) +#define JT_UART_UMCR(_n1) JIO_32_RW +#define JN_UART_UMCR(_n1) UART_UMCR +#define JI_UART_UMCR(_n1) (_n1) +#define BP_UART_UMCR_MDCE 7 +#define BM_UART_UMCR_MDCE 0x80 +#define BF_UART_UMCR_MDCE(v) (((v) & 0x1) << 7) +#define BFM_UART_UMCR_MDCE(v) BM_UART_UMCR_MDCE +#define BF_UART_UMCR_MDCE_V(e) BF_UART_UMCR_MDCE(BV_UART_UMCR_MDCE__##e) +#define BFM_UART_UMCR_MDCE_V(v) BM_UART_UMCR_MDCE +#define BP_UART_UMCR_FCM 6 +#define BM_UART_UMCR_FCM 0x40 +#define BF_UART_UMCR_FCM(v) (((v) & 0x1) << 6) +#define BFM_UART_UMCR_FCM(v) BM_UART_UMCR_FCM +#define BF_UART_UMCR_FCM_V(e) BF_UART_UMCR_FCM(BV_UART_UMCR_FCM__##e) +#define BFM_UART_UMCR_FCM_V(v) BM_UART_UMCR_FCM +#define BP_UART_UMCR_LOOP 4 +#define BM_UART_UMCR_LOOP 0x10 +#define BF_UART_UMCR_LOOP(v) (((v) & 0x1) << 4) +#define BFM_UART_UMCR_LOOP(v) BM_UART_UMCR_LOOP +#define BF_UART_UMCR_LOOP_V(e) BF_UART_UMCR_LOOP(BV_UART_UMCR_LOOP__##e) +#define BFM_UART_UMCR_LOOP_V(v) BM_UART_UMCR_LOOP +#define BP_UART_UMCR_RTS 1 +#define BM_UART_UMCR_RTS 0x2 +#define BF_UART_UMCR_RTS(v) (((v) & 0x1) << 1) +#define BFM_UART_UMCR_RTS(v) BM_UART_UMCR_RTS +#define BF_UART_UMCR_RTS_V(e) BF_UART_UMCR_RTS(BV_UART_UMCR_RTS__##e) +#define BFM_UART_UMCR_RTS_V(v) BM_UART_UMCR_RTS + +#define REG_UART_ULSR(_n1) jz_reg(UART_ULSR(_n1)) +#define JA_UART_ULSR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x14) +#define JT_UART_ULSR(_n1) JIO_32_RW +#define JN_UART_ULSR(_n1) UART_ULSR +#define JI_UART_ULSR(_n1) (_n1) +#define BP_UART_ULSR_FIFOE 7 +#define BM_UART_ULSR_FIFOE 0x80 +#define BF_UART_ULSR_FIFOE(v) (((v) & 0x1) << 7) +#define BFM_UART_ULSR_FIFOE(v) BM_UART_ULSR_FIFOE +#define BF_UART_ULSR_FIFOE_V(e) BF_UART_ULSR_FIFOE(BV_UART_ULSR_FIFOE__##e) +#define BFM_UART_ULSR_FIFOE_V(v) BM_UART_ULSR_FIFOE +#define BP_UART_ULSR_TEMP 6 +#define BM_UART_ULSR_TEMP 0x40 +#define BF_UART_ULSR_TEMP(v) (((v) & 0x1) << 6) +#define BFM_UART_ULSR_TEMP(v) BM_UART_ULSR_TEMP +#define BF_UART_ULSR_TEMP_V(e) BF_UART_ULSR_TEMP(BV_UART_ULSR_TEMP__##e) +#define BFM_UART_ULSR_TEMP_V(v) BM_UART_ULSR_TEMP +#define BP_UART_ULSR_TDRQ 5 +#define BM_UART_ULSR_TDRQ 0x20 +#define BF_UART_ULSR_TDRQ(v) (((v) & 0x1) << 5) +#define BFM_UART_ULSR_TDRQ(v) BM_UART_ULSR_TDRQ +#define BF_UART_ULSR_TDRQ_V(e) BF_UART_ULSR_TDRQ(BV_UART_ULSR_TDRQ__##e) +#define BFM_UART_ULSR_TDRQ_V(v) BM_UART_ULSR_TDRQ +#define BP_UART_ULSR_BI 4 +#define BM_UART_ULSR_BI 0x10 +#define BF_UART_ULSR_BI(v) (((v) & 0x1) << 4) +#define BFM_UART_ULSR_BI(v) BM_UART_ULSR_BI +#define BF_UART_ULSR_BI_V(e) BF_UART_ULSR_BI(BV_UART_ULSR_BI__##e) +#define BFM_UART_ULSR_BI_V(v) BM_UART_ULSR_BI +#define BP_UART_ULSR_FMER 3 +#define BM_UART_ULSR_FMER 0x8 +#define BF_UART_ULSR_FMER(v) (((v) & 0x1) << 3) +#define BFM_UART_ULSR_FMER(v) BM_UART_ULSR_FMER +#define BF_UART_ULSR_FMER_V(e) BF_UART_ULSR_FMER(BV_UART_ULSR_FMER__##e) +#define BFM_UART_ULSR_FMER_V(v) BM_UART_ULSR_FMER +#define BP_UART_ULSR_PARER 2 +#define BM_UART_ULSR_PARER 0x4 +#define BF_UART_ULSR_PARER(v) (((v) & 0x1) << 2) +#define BFM_UART_ULSR_PARER(v) BM_UART_ULSR_PARER +#define BF_UART_ULSR_PARER_V(e) BF_UART_ULSR_PARER(BV_UART_ULSR_PARER__##e) +#define BFM_UART_ULSR_PARER_V(v) BM_UART_ULSR_PARER +#define BP_UART_ULSR_OVER 1 +#define BM_UART_ULSR_OVER 0x2 +#define BF_UART_ULSR_OVER(v) (((v) & 0x1) << 1) +#define BFM_UART_ULSR_OVER(v) BM_UART_ULSR_OVER +#define BF_UART_ULSR_OVER_V(e) BF_UART_ULSR_OVER(BV_UART_ULSR_OVER__##e) +#define BFM_UART_ULSR_OVER_V(v) BM_UART_ULSR_OVER +#define BP_UART_ULSR_DRY 0 +#define BM_UART_ULSR_DRY 0x1 +#define BF_UART_ULSR_DRY(v) (((v) & 0x1) << 0) +#define BFM_UART_ULSR_DRY(v) BM_UART_ULSR_DRY +#define BF_UART_ULSR_DRY_V(e) BF_UART_ULSR_DRY(BV_UART_ULSR_DRY__##e) +#define BFM_UART_ULSR_DRY_V(v) BM_UART_ULSR_DRY + +#define REG_UART_UMSR(_n1) jz_reg(UART_UMSR(_n1)) +#define JA_UART_UMSR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x18) +#define JT_UART_UMSR(_n1) JIO_32_RW +#define JN_UART_UMSR(_n1) UART_UMSR +#define JI_UART_UMSR(_n1) (_n1) +#define BP_UART_UMSR_CTS 4 +#define BM_UART_UMSR_CTS 0x10 +#define BF_UART_UMSR_CTS(v) (((v) & 0x1) << 4) +#define BFM_UART_UMSR_CTS(v) BM_UART_UMSR_CTS +#define BF_UART_UMSR_CTS_V(e) BF_UART_UMSR_CTS(BV_UART_UMSR_CTS__##e) +#define BFM_UART_UMSR_CTS_V(v) BM_UART_UMSR_CTS +#define BP_UART_UMSR_CCTS 0 +#define BM_UART_UMSR_CCTS 0x1 +#define BF_UART_UMSR_CCTS(v) (((v) & 0x1) << 0) +#define BFM_UART_UMSR_CCTS(v) BM_UART_UMSR_CCTS +#define BF_UART_UMSR_CCTS_V(e) BF_UART_UMSR_CCTS(BV_UART_UMSR_CCTS__##e) +#define BFM_UART_UMSR_CCTS_V(v) BM_UART_UMSR_CCTS + +#define REG_UART_USPR(_n1) jz_reg(UART_USPR(_n1)) +#define JA_UART_USPR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x1c) +#define JT_UART_USPR(_n1) JIO_32_RW +#define JN_UART_USPR(_n1) UART_USPR +#define JI_UART_USPR(_n1) (_n1) + +#define REG_UART_ISR(_n1) jz_reg(UART_ISR(_n1)) +#define JA_UART_ISR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x20) +#define JT_UART_ISR(_n1) JIO_32_RW +#define JN_UART_ISR(_n1) UART_ISR +#define JI_UART_ISR(_n1) (_n1) +#define BP_UART_ISR_RDPL 4 +#define BM_UART_ISR_RDPL 0x10 +#define BF_UART_ISR_RDPL(v) (((v) & 0x1) << 4) +#define BFM_UART_ISR_RDPL(v) BM_UART_ISR_RDPL +#define BF_UART_ISR_RDPL_V(e) BF_UART_ISR_RDPL(BV_UART_ISR_RDPL__##e) +#define BFM_UART_ISR_RDPL_V(v) BM_UART_ISR_RDPL +#define BP_UART_ISR_TDPL 3 +#define BM_UART_ISR_TDPL 0x8 +#define BF_UART_ISR_TDPL(v) (((v) & 0x1) << 3) +#define BFM_UART_ISR_TDPL(v) BM_UART_ISR_TDPL +#define BF_UART_ISR_TDPL_V(e) BF_UART_ISR_TDPL(BV_UART_ISR_TDPL__##e) +#define BFM_UART_ISR_TDPL_V(v) BM_UART_ISR_TDPL +#define BP_UART_ISR_XMODE 2 +#define BM_UART_ISR_XMODE 0x4 +#define BF_UART_ISR_XMODE(v) (((v) & 0x1) << 2) +#define BFM_UART_ISR_XMODE(v) BM_UART_ISR_XMODE +#define BF_UART_ISR_XMODE_V(e) BF_UART_ISR_XMODE(BV_UART_ISR_XMODE__##e) +#define BFM_UART_ISR_XMODE_V(v) BM_UART_ISR_XMODE +#define BP_UART_ISR_RCVEIR 1 +#define BM_UART_ISR_RCVEIR 0x2 +#define BF_UART_ISR_RCVEIR(v) (((v) & 0x1) << 1) +#define BFM_UART_ISR_RCVEIR(v) BM_UART_ISR_RCVEIR +#define BF_UART_ISR_RCVEIR_V(e) BF_UART_ISR_RCVEIR(BV_UART_ISR_RCVEIR__##e) +#define BFM_UART_ISR_RCVEIR_V(v) BM_UART_ISR_RCVEIR +#define BP_UART_ISR_XMITIR 0 +#define BM_UART_ISR_XMITIR 0x1 +#define BF_UART_ISR_XMITIR(v) (((v) & 0x1) << 0) +#define BFM_UART_ISR_XMITIR(v) BM_UART_ISR_XMITIR +#define BF_UART_ISR_XMITIR_V(e) BF_UART_ISR_XMITIR(BV_UART_ISR_XMITIR__##e) +#define BFM_UART_ISR_XMITIR_V(v) BM_UART_ISR_XMITIR + +#define REG_UART_UMR(_n1) jz_reg(UART_UMR(_n1)) +#define JA_UART_UMR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x24) +#define JT_UART_UMR(_n1) JIO_32_RW +#define JN_UART_UMR(_n1) UART_UMR +#define JI_UART_UMR(_n1) (_n1) + +#define REG_UART_UACR(_n1) jz_reg(UART_UACR(_n1)) +#define JA_UART_UACR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x28) +#define JT_UART_UACR(_n1) JIO_32_RW +#define JN_UART_UACR(_n1) UART_UACR +#define JI_UART_UACR(_n1) (_n1) + +#define REG_UART_URCR(_n1) jz_reg(UART_URCR(_n1)) +#define JA_UART_URCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x40) +#define JT_UART_URCR(_n1) JIO_32_RW +#define JN_UART_URCR(_n1) UART_URCR +#define JI_UART_URCR(_n1) (_n1) + +#define REG_UART_UTCR(_n1) jz_reg(UART_UTCR(_n1)) +#define JA_UART_UTCR(_n1) (0xb0030000 + (_n1) * 0x1000 + 0x44) +#define JT_UART_UTCR(_n1) JIO_32_RW +#define JN_UART_UTCR(_n1) UART_UTCR +#define JI_UART_UTCR(_n1) (_n1) + +#endif /* __HEADERGEN_UART_H__*/ diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index 0d971c59f8..4620378c19 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen @@ -190,6 +190,115 @@ node AIC { reg I2SDIV 0x30 reg DR 0x34 + reg SPENA 0x80 + + reg SPCTRL 0x84 { + bit 15 DMA_EN + bit 14 D_TYPE + bit 13 SIGN_N + bit 12 INVALID + bit 11 SFT_RST + bit 10 SPDIF_I2S + bit 1 M_TRIG + bit 0 M_FFUR + } + + reg SPSTATE 0x88 { + fld 14 8 FIFO_LEVEL + bit 7 BUSY + bit 1 F_TRIG + bit 0 F_FFUR + } + + reg SPCFG1 0x8c { + bit 17 INIT_LEVEL + bit 16 ZERO_VALID + fld 13 12 TRIG + fld 11 8 SRC_NUM + fld 7 4 CH1_NUM + fld 3 0 CH2_NUM + } + + reg SPCFG2 0x90 { + fld 29 26 FS + fld 25 22 ORG_FRQ + fld 21 19 SAMPL_WL + bit 18 MAX_WL + fld 17 16 CLK_ACU + fld 15 8 CAT_CODE + fld 7 6 CH_MD + bit 3 PRE + bit 2 COPY_N + bit 1 AUDIO_N + bit 0 CON_PRO + } + + reg SPFIFO 0x94 + + reg RGADW 0xa4 { + bit 31 ICRST + bit 16 RGWR + fld 14 8 ADDR + fld 7 0 DATA + } + + reg RGDATA 0xa8 { + bit 8 IRQ + fld 7 0 DATA + } +} + +node PCM { + title "PCM interface controller" + addr 0xb0071000 + + reg CTL 0x00 { + bit 9 ERDMA + bit 8 ETDMA + bit 7 LSMP + bit 6 ERPL + bit 5 EREC + bit 4 FLUSH + bit 3 RST + bit 1 CLKEN + bit 0 PCMEN + } + + reg CFG 0x04 { + fld 14 13 SLOT + bit 12 ISS + bit 11 OSS + bit 10 IMSBPOS + bit 9 OMSBPOS + fld 8 5 RFTH + fld 4 1 TFTH + bit 0 PCMMOD + } + + reg DP 0x08 + + reg INTC 0x0c { + bit 3 ETFS + bit 2 ETUR + bit 1 ERFS + bit 0 EROR + } + + reg INTS 0x10 { + bit 14 RSTS + fld 13 9 TFL + bit 8 TFS + bit 7 TUR + bit 6 2 RFL + bit 1 RFS + bit 0 ROR + } + + reg DIV 0x14 { + fld 16 11 SYNL + fld 10 6 SYNDIV + fld 5 0 CLKDIV + } } node DDRC { @@ -851,6 +960,44 @@ node RTC { reg WKUPPINCR 0x48 } +node EFUSE { + title "EFUSE interface" + instance 0xb3540000 + + reg CTRL 0x00 { + fld 27 21 ADDR + fld 20 16 LENGTH + bit 15 PG_EN + bit 1 WR_EN + bit 0 RD_EN + } + + reg CFG 0x04 { + bit 31 INT_EN + fld 21 20 RD_AJD + fld 18 16 RD_STROBE + fld 13 12 WR_ADJ + fld 8 0 WR_STROBE + } + + reg STATE 0x08 { + bit 23 UK_PRT + bit 22 NKU_PRT + bit 21 EXKEY_EN + bit 15 CUSTID_PRT + bit 14 CHIPID_PRT + bit 12 SECBOOT_PRT + bit 11 DIS_JTAG + bit 8 SECBOOT_EN + bit 1 WR_DONE + bit 0 RD_DONE + } + + reg DATA { + instance 0x0c 0x04 8 + } +} + node GPIO { title "General purpose I/O" addr 0xb0010000 @@ -1003,6 +1150,156 @@ node I2C { reg CGC 0x68 } +node SSI { + title "Synchronous serial interface" + instance 0xb0043000 + + reg DR 0x00 + + reg CR0 0x04 { + fld 19 18 TENDIAN + fld 17 16 RENDIAN + bit 15 SSIE + bit 14 TIE + bit 13 RIE + bit 12 TEIE + bit 11 REIE + bit 10 LOOP + bit 9 RFINE + bit 8 RFINC + bit 7 EACLRUN + bit 6 FSEL + bit 4 VRCNT + bit 3 TFMODE + bit 2 TFLUSH + bit 1 RFLUSH + bit 0 DISREV + } + + reg CR1 0x08 { + fld 31 30 FRMHL + fld 29 28 TFVCK + fld 27 26 TCKFI + bit 24 ITFRM + bit 23 UNFIN + fld 21 20 FMAT + fld 19 16 TTRG + fld 15 12 MCOM + fld 11 8 RTRG + fld 7 3 FLEN + bit 1 PHA + bit 0 POL + } + + reg SR 0x0c { + fld 24 16 TFIFO_NUM + fld 15 8 RFIFO_NUM + bit 7 END + bit 6 BUSY + bit 5 TFF + bit 4 RFE + bit 3 TFHE + bit 2 RFHF + bit 1 UNDR + bit 0 OVER + } + + reg ITR 0x10 { + bit 15 CNTCLK + fld 14 0 IVLTM + } + + reg ICR 0x14 + reg GR 0x18 + reg RCNT 0x1c +} + +node UART { + title "UART controller" + instance 0xb0030000 0x1000 3 + + # Note there is some hardware multiplexing controlled by the + # ULCR register going on here which is why some registers share + # the same address. + + reg URBR 0x00 + reg UTHR 0x00 + reg UDLLR 0x00 + reg UDLHR 0x04 + + reg UIER 0x04 { + bit 4 RTOIE + bit 3 MSIE + bit 2 RLSIE + bit 1 TDRIE + bit 0 RDRIE + } + + reg UIIR 0x08 { + fld 7 6 FFMSEL { enum NON_FIFO_MODE 0; enum FIFO_MODE 1; } + fld 3 1 INID { enum MODEM_STATUS 0; enum TRANSMIT_DATA_REQ 1; enum RECEIVE_DATA_READY 2 + enum RECEIVE_LINE_STATUS 3; enum RECEIVE_TIME_OUT 6 } + bit 0 INPEND + } + + reg UFCR 0x08 { + fld 7 6 RDTR { enum 1BYTE 0; enum 16BYTE 1; enum 32BYTE 2; enum 60BYTE 3; } + bit 4 UME + bit 3 DME + bit 2 TFRT + bit 1 RFRT + bit 0 FME + } + + reg ULCR 0x0c { + bit 7 DLAB + bit 6 SBK + bit 5 STPAR + bit 4 PARM { enum ODD 0; enum EVEN 1; } + bit 3 PARE + bit 2 SBLS { enum 1_STOP_BIT 0; enum 2_STOP_BITS 1; } + fld 1 0 WLS { enum 5BITS 0; enum 6BITS 1; enum 7BITS 2; enum 8BITS 3; } + } + + reg UMCR 0x10 { + bit 7 MDCE + bit 6 FCM + bit 4 LOOP + bit 1 RTS + } + + reg ULSR 0x14 { + bit 7 FIFOE + bit 6 TEMP + bit 5 TDRQ + bit 4 BI + bit 3 FMER + bit 2 PARER + bit 1 OVER + bit 0 DRY + } + + reg UMSR 0x18 { + bit 4 CTS + bit 0 CCTS + } + + reg USPR 0x1c + + reg ISR 0x20 { + bit 4 RDPL + bit 3 TDPL + bit 2 XMODE + bit 1 RCVEIR + bit 0 XMITIR + } + + reg UMR 0x24 + reg UACR 0x28 + reg URCR 0x40 + reg UTCR 0x44 +} + node MSC { title "MMC/SD/CE-ATA controller" instance 0xb3450000 0x10000 2 -- cgit v1.2.3