diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/pcm.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/pcm.h | 251 |
1 files changed, 251 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/pcm.h b/firmware/target/mips/ingenic_x1000/x1000/pcm.h new file mode 100644 index 0000000000..e47a2e5c13 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/pcm.h | |||
@@ -0,0 +1,251 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_PCM_H__ | ||
25 | #define __HEADERGEN_PCM_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_PCM_CTL jz_reg(PCM_CTL) | ||
30 | #define JA_PCM_CTL (0xb0071000 + 0x0) | ||
31 | #define JT_PCM_CTL JIO_32_RW | ||
32 | #define JN_PCM_CTL PCM_CTL | ||
33 | #define JI_PCM_CTL | ||
34 | #define BP_PCM_CTL_ERDMA 9 | ||
35 | #define BM_PCM_CTL_ERDMA 0x200 | ||
36 | #define BF_PCM_CTL_ERDMA(v) (((v) & 0x1) << 9) | ||
37 | #define BFM_PCM_CTL_ERDMA(v) BM_PCM_CTL_ERDMA | ||
38 | #define BF_PCM_CTL_ERDMA_V(e) BF_PCM_CTL_ERDMA(BV_PCM_CTL_ERDMA__##e) | ||
39 | #define BFM_PCM_CTL_ERDMA_V(v) BM_PCM_CTL_ERDMA | ||
40 | #define BP_PCM_CTL_ETDMA 8 | ||
41 | #define BM_PCM_CTL_ETDMA 0x100 | ||
42 | #define BF_PCM_CTL_ETDMA(v) (((v) & 0x1) << 8) | ||
43 | #define BFM_PCM_CTL_ETDMA(v) BM_PCM_CTL_ETDMA | ||
44 | #define BF_PCM_CTL_ETDMA_V(e) BF_PCM_CTL_ETDMA(BV_PCM_CTL_ETDMA__##e) | ||
45 | #define BFM_PCM_CTL_ETDMA_V(v) BM_PCM_CTL_ETDMA | ||
46 | #define BP_PCM_CTL_LSMP 7 | ||
47 | #define BM_PCM_CTL_LSMP 0x80 | ||
48 | #define BF_PCM_CTL_LSMP(v) (((v) & 0x1) << 7) | ||
49 | #define BFM_PCM_CTL_LSMP(v) BM_PCM_CTL_LSMP | ||
50 | #define BF_PCM_CTL_LSMP_V(e) BF_PCM_CTL_LSMP(BV_PCM_CTL_LSMP__##e) | ||
51 | #define BFM_PCM_CTL_LSMP_V(v) BM_PCM_CTL_LSMP | ||
52 | #define BP_PCM_CTL_ERPL 6 | ||
53 | #define BM_PCM_CTL_ERPL 0x40 | ||
54 | #define BF_PCM_CTL_ERPL(v) (((v) & 0x1) << 6) | ||
55 | #define BFM_PCM_CTL_ERPL(v) BM_PCM_CTL_ERPL | ||
56 | #define BF_PCM_CTL_ERPL_V(e) BF_PCM_CTL_ERPL(BV_PCM_CTL_ERPL__##e) | ||
57 | #define BFM_PCM_CTL_ERPL_V(v) BM_PCM_CTL_ERPL | ||
58 | #define BP_PCM_CTL_EREC 5 | ||
59 | #define BM_PCM_CTL_EREC 0x20 | ||
60 | #define BF_PCM_CTL_EREC(v) (((v) & 0x1) << 5) | ||
61 | #define BFM_PCM_CTL_EREC(v) BM_PCM_CTL_EREC | ||
62 | #define BF_PCM_CTL_EREC_V(e) BF_PCM_CTL_EREC(BV_PCM_CTL_EREC__##e) | ||
63 | #define BFM_PCM_CTL_EREC_V(v) BM_PCM_CTL_EREC | ||
64 | #define BP_PCM_CTL_FLUSH 4 | ||
65 | #define BM_PCM_CTL_FLUSH 0x10 | ||
66 | #define BF_PCM_CTL_FLUSH(v) (((v) & 0x1) << 4) | ||
67 | #define BFM_PCM_CTL_FLUSH(v) BM_PCM_CTL_FLUSH | ||
68 | #define BF_PCM_CTL_FLUSH_V(e) BF_PCM_CTL_FLUSH(BV_PCM_CTL_FLUSH__##e) | ||
69 | #define BFM_PCM_CTL_FLUSH_V(v) BM_PCM_CTL_FLUSH | ||
70 | #define BP_PCM_CTL_RST 3 | ||
71 | #define BM_PCM_CTL_RST 0x8 | ||
72 | #define BF_PCM_CTL_RST(v) (((v) & 0x1) << 3) | ||
73 | #define BFM_PCM_CTL_RST(v) BM_PCM_CTL_RST | ||
74 | #define BF_PCM_CTL_RST_V(e) BF_PCM_CTL_RST(BV_PCM_CTL_RST__##e) | ||
75 | #define BFM_PCM_CTL_RST_V(v) BM_PCM_CTL_RST | ||
76 | #define BP_PCM_CTL_CLKEN 1 | ||
77 | #define BM_PCM_CTL_CLKEN 0x2 | ||
78 | #define BF_PCM_CTL_CLKEN(v) (((v) & 0x1) << 1) | ||
79 | #define BFM_PCM_CTL_CLKEN(v) BM_PCM_CTL_CLKEN | ||
80 | #define BF_PCM_CTL_CLKEN_V(e) BF_PCM_CTL_CLKEN(BV_PCM_CTL_CLKEN__##e) | ||
81 | #define BFM_PCM_CTL_CLKEN_V(v) BM_PCM_CTL_CLKEN | ||
82 | #define BP_PCM_CTL_PCMEN 0 | ||
83 | #define BM_PCM_CTL_PCMEN 0x1 | ||
84 | #define BF_PCM_CTL_PCMEN(v) (((v) & 0x1) << 0) | ||
85 | #define BFM_PCM_CTL_PCMEN(v) BM_PCM_CTL_PCMEN | ||
86 | #define BF_PCM_CTL_PCMEN_V(e) BF_PCM_CTL_PCMEN(BV_PCM_CTL_PCMEN__##e) | ||
87 | #define BFM_PCM_CTL_PCMEN_V(v) BM_PCM_CTL_PCMEN | ||
88 | |||
89 | #define REG_PCM_CFG jz_reg(PCM_CFG) | ||
90 | #define JA_PCM_CFG (0xb0071000 + 0x4) | ||
91 | #define JT_PCM_CFG JIO_32_RW | ||
92 | #define JN_PCM_CFG PCM_CFG | ||
93 | #define JI_PCM_CFG | ||
94 | #define BP_PCM_CFG_SLOT 13 | ||
95 | #define BM_PCM_CFG_SLOT 0x6000 | ||
96 | #define BF_PCM_CFG_SLOT(v) (((v) & 0x3) << 13) | ||
97 | #define BFM_PCM_CFG_SLOT(v) BM_PCM_CFG_SLOT | ||
98 | #define BF_PCM_CFG_SLOT_V(e) BF_PCM_CFG_SLOT(BV_PCM_CFG_SLOT__##e) | ||
99 | #define BFM_PCM_CFG_SLOT_V(v) BM_PCM_CFG_SLOT | ||
100 | #define BP_PCM_CFG_RFTH 5 | ||
101 | #define BM_PCM_CFG_RFTH 0x1e0 | ||
102 | #define BF_PCM_CFG_RFTH(v) (((v) & 0xf) << 5) | ||
103 | #define BFM_PCM_CFG_RFTH(v) BM_PCM_CFG_RFTH | ||
104 | #define BF_PCM_CFG_RFTH_V(e) BF_PCM_CFG_RFTH(BV_PCM_CFG_RFTH__##e) | ||
105 | #define BFM_PCM_CFG_RFTH_V(v) BM_PCM_CFG_RFTH | ||
106 | #define BP_PCM_CFG_TFTH 1 | ||
107 | #define BM_PCM_CFG_TFTH 0x1e | ||
108 | #define BF_PCM_CFG_TFTH(v) (((v) & 0xf) << 1) | ||
109 | #define BFM_PCM_CFG_TFTH(v) BM_PCM_CFG_TFTH | ||
110 | #define BF_PCM_CFG_TFTH_V(e) BF_PCM_CFG_TFTH(BV_PCM_CFG_TFTH__##e) | ||
111 | #define BFM_PCM_CFG_TFTH_V(v) BM_PCM_CFG_TFTH | ||
112 | #define BP_PCM_CFG_ISS 12 | ||
113 | #define BM_PCM_CFG_ISS 0x1000 | ||
114 | #define BF_PCM_CFG_ISS(v) (((v) & 0x1) << 12) | ||
115 | #define BFM_PCM_CFG_ISS(v) BM_PCM_CFG_ISS | ||
116 | #define BF_PCM_CFG_ISS_V(e) BF_PCM_CFG_ISS(BV_PCM_CFG_ISS__##e) | ||
117 | #define BFM_PCM_CFG_ISS_V(v) BM_PCM_CFG_ISS | ||
118 | #define BP_PCM_CFG_OSS 11 | ||
119 | #define BM_PCM_CFG_OSS 0x800 | ||
120 | #define BF_PCM_CFG_OSS(v) (((v) & 0x1) << 11) | ||
121 | #define BFM_PCM_CFG_OSS(v) BM_PCM_CFG_OSS | ||
122 | #define BF_PCM_CFG_OSS_V(e) BF_PCM_CFG_OSS(BV_PCM_CFG_OSS__##e) | ||
123 | #define BFM_PCM_CFG_OSS_V(v) BM_PCM_CFG_OSS | ||
124 | #define BP_PCM_CFG_IMSBPOS 10 | ||
125 | #define BM_PCM_CFG_IMSBPOS 0x400 | ||
126 | #define BF_PCM_CFG_IMSBPOS(v) (((v) & 0x1) << 10) | ||
127 | #define BFM_PCM_CFG_IMSBPOS(v) BM_PCM_CFG_IMSBPOS | ||
128 | #define BF_PCM_CFG_IMSBPOS_V(e) BF_PCM_CFG_IMSBPOS(BV_PCM_CFG_IMSBPOS__##e) | ||
129 | #define BFM_PCM_CFG_IMSBPOS_V(v) BM_PCM_CFG_IMSBPOS | ||
130 | #define BP_PCM_CFG_OMSBPOS 9 | ||
131 | #define BM_PCM_CFG_OMSBPOS 0x200 | ||
132 | #define BF_PCM_CFG_OMSBPOS(v) (((v) & 0x1) << 9) | ||
133 | #define BFM_PCM_CFG_OMSBPOS(v) BM_PCM_CFG_OMSBPOS | ||
134 | #define BF_PCM_CFG_OMSBPOS_V(e) BF_PCM_CFG_OMSBPOS(BV_PCM_CFG_OMSBPOS__##e) | ||
135 | #define BFM_PCM_CFG_OMSBPOS_V(v) BM_PCM_CFG_OMSBPOS | ||
136 | #define BP_PCM_CFG_PCMMOD 0 | ||
137 | #define BM_PCM_CFG_PCMMOD 0x1 | ||
138 | #define BF_PCM_CFG_PCMMOD(v) (((v) & 0x1) << 0) | ||
139 | #define BFM_PCM_CFG_PCMMOD(v) BM_PCM_CFG_PCMMOD | ||
140 | #define BF_PCM_CFG_PCMMOD_V(e) BF_PCM_CFG_PCMMOD(BV_PCM_CFG_PCMMOD__##e) | ||
141 | #define BFM_PCM_CFG_PCMMOD_V(v) BM_PCM_CFG_PCMMOD | ||
142 | |||
143 | #define REG_PCM_DP jz_reg(PCM_DP) | ||
144 | #define JA_PCM_DP (0xb0071000 + 0x8) | ||
145 | #define JT_PCM_DP JIO_32_RW | ||
146 | #define JN_PCM_DP PCM_DP | ||
147 | #define JI_PCM_DP | ||
148 | |||
149 | #define REG_PCM_INTC jz_reg(PCM_INTC) | ||
150 | #define JA_PCM_INTC (0xb0071000 + 0xc) | ||
151 | #define JT_PCM_INTC JIO_32_RW | ||
152 | #define JN_PCM_INTC PCM_INTC | ||
153 | #define JI_PCM_INTC | ||
154 | #define BP_PCM_INTC_ETFS 3 | ||
155 | #define BM_PCM_INTC_ETFS 0x8 | ||
156 | #define BF_PCM_INTC_ETFS(v) (((v) & 0x1) << 3) | ||
157 | #define BFM_PCM_INTC_ETFS(v) BM_PCM_INTC_ETFS | ||
158 | #define BF_PCM_INTC_ETFS_V(e) BF_PCM_INTC_ETFS(BV_PCM_INTC_ETFS__##e) | ||
159 | #define BFM_PCM_INTC_ETFS_V(v) BM_PCM_INTC_ETFS | ||
160 | #define BP_PCM_INTC_ETUR 2 | ||
161 | #define BM_PCM_INTC_ETUR 0x4 | ||
162 | #define BF_PCM_INTC_ETUR(v) (((v) & 0x1) << 2) | ||
163 | #define BFM_PCM_INTC_ETUR(v) BM_PCM_INTC_ETUR | ||
164 | #define BF_PCM_INTC_ETUR_V(e) BF_PCM_INTC_ETUR(BV_PCM_INTC_ETUR__##e) | ||
165 | #define BFM_PCM_INTC_ETUR_V(v) BM_PCM_INTC_ETUR | ||
166 | #define BP_PCM_INTC_ERFS 1 | ||
167 | #define BM_PCM_INTC_ERFS 0x2 | ||
168 | #define BF_PCM_INTC_ERFS(v) (((v) & 0x1) << 1) | ||
169 | #define BFM_PCM_INTC_ERFS(v) BM_PCM_INTC_ERFS | ||
170 | #define BF_PCM_INTC_ERFS_V(e) BF_PCM_INTC_ERFS(BV_PCM_INTC_ERFS__##e) | ||
171 | #define BFM_PCM_INTC_ERFS_V(v) BM_PCM_INTC_ERFS | ||
172 | #define BP_PCM_INTC_EROR 0 | ||
173 | #define BM_PCM_INTC_EROR 0x1 | ||
174 | #define BF_PCM_INTC_EROR(v) (((v) & 0x1) << 0) | ||
175 | #define BFM_PCM_INTC_EROR(v) BM_PCM_INTC_EROR | ||
176 | #define BF_PCM_INTC_EROR_V(e) BF_PCM_INTC_EROR(BV_PCM_INTC_EROR__##e) | ||
177 | #define BFM_PCM_INTC_EROR_V(v) BM_PCM_INTC_EROR | ||
178 | |||
179 | #define REG_PCM_INTS jz_reg(PCM_INTS) | ||
180 | #define JA_PCM_INTS (0xb0071000 + 0x10) | ||
181 | #define JT_PCM_INTS JIO_32_RW | ||
182 | #define JN_PCM_INTS PCM_INTS | ||
183 | #define JI_PCM_INTS | ||
184 | #define BP_PCM_INTS_TFL 9 | ||
185 | #define BM_PCM_INTS_TFL 0x3e00 | ||
186 | #define BF_PCM_INTS_TFL(v) (((v) & 0x1f) << 9) | ||
187 | #define BFM_PCM_INTS_TFL(v) BM_PCM_INTS_TFL | ||
188 | #define BF_PCM_INTS_TFL_V(e) BF_PCM_INTS_TFL(BV_PCM_INTS_TFL__##e) | ||
189 | #define BFM_PCM_INTS_TFL_V(v) BM_PCM_INTS_TFL | ||
190 | #define BP_PCM_INTS_RSTS 14 | ||
191 | #define BM_PCM_INTS_RSTS 0x4000 | ||
192 | #define BF_PCM_INTS_RSTS(v) (((v) & 0x1) << 14) | ||
193 | #define BFM_PCM_INTS_RSTS(v) BM_PCM_INTS_RSTS | ||
194 | #define BF_PCM_INTS_RSTS_V(e) BF_PCM_INTS_RSTS(BV_PCM_INTS_RSTS__##e) | ||
195 | #define BFM_PCM_INTS_RSTS_V(v) BM_PCM_INTS_RSTS | ||
196 | #define BP_PCM_INTS_TFS 8 | ||
197 | #define BM_PCM_INTS_TFS 0x100 | ||
198 | #define BF_PCM_INTS_TFS(v) (((v) & 0x1) << 8) | ||
199 | #define BFM_PCM_INTS_TFS(v) BM_PCM_INTS_TFS | ||
200 | #define BF_PCM_INTS_TFS_V(e) BF_PCM_INTS_TFS(BV_PCM_INTS_TFS__##e) | ||
201 | #define BFM_PCM_INTS_TFS_V(v) BM_PCM_INTS_TFS | ||
202 | #define BP_PCM_INTS_TUR 7 | ||
203 | #define BM_PCM_INTS_TUR 0x80 | ||
204 | #define BF_PCM_INTS_TUR(v) (((v) & 0x1) << 7) | ||
205 | #define BFM_PCM_INTS_TUR(v) BM_PCM_INTS_TUR | ||
206 | #define BF_PCM_INTS_TUR_V(e) BF_PCM_INTS_TUR(BV_PCM_INTS_TUR__##e) | ||
207 | #define BFM_PCM_INTS_TUR_V(v) BM_PCM_INTS_TUR | ||
208 | #define BP_PCM_INTS_RFL 2 | ||
209 | #define BM_PCM_INTS_RFL 0x7c | ||
210 | #define BF_PCM_INTS_RFL(v) (((v) & 0x1f) << 2) | ||
211 | #define BFM_PCM_INTS_RFL(v) BM_PCM_INTS_RFL | ||
212 | #define BF_PCM_INTS_RFL_V(e) BF_PCM_INTS_RFL(BV_PCM_INTS_RFL__##e) | ||
213 | #define BFM_PCM_INTS_RFL_V(v) BM_PCM_INTS_RFL | ||
214 | #define BP_PCM_INTS_RFS 1 | ||
215 | #define BM_PCM_INTS_RFS 0x2 | ||
216 | #define BF_PCM_INTS_RFS(v) (((v) & 0x1) << 1) | ||
217 | #define BFM_PCM_INTS_RFS(v) BM_PCM_INTS_RFS | ||
218 | #define BF_PCM_INTS_RFS_V(e) BF_PCM_INTS_RFS(BV_PCM_INTS_RFS__##e) | ||
219 | #define BFM_PCM_INTS_RFS_V(v) BM_PCM_INTS_RFS | ||
220 | #define BP_PCM_INTS_ROR 0 | ||
221 | #define BM_PCM_INTS_ROR 0x1 | ||
222 | #define BF_PCM_INTS_ROR(v) (((v) & 0x1) << 0) | ||
223 | #define BFM_PCM_INTS_ROR(v) BM_PCM_INTS_ROR | ||
224 | #define BF_PCM_INTS_ROR_V(e) BF_PCM_INTS_ROR(BV_PCM_INTS_ROR__##e) | ||
225 | #define BFM_PCM_INTS_ROR_V(v) BM_PCM_INTS_ROR | ||
226 | |||
227 | #define REG_PCM_DIV jz_reg(PCM_DIV) | ||
228 | #define JA_PCM_DIV (0xb0071000 + 0x14) | ||
229 | #define JT_PCM_DIV JIO_32_RW | ||
230 | #define JN_PCM_DIV PCM_DIV | ||
231 | #define JI_PCM_DIV | ||
232 | #define BP_PCM_DIV_SYNL 11 | ||
233 | #define BM_PCM_DIV_SYNL 0x1f800 | ||
234 | #define BF_PCM_DIV_SYNL(v) (((v) & 0x3f) << 11) | ||
235 | #define BFM_PCM_DIV_SYNL(v) BM_PCM_DIV_SYNL | ||
236 | #define BF_PCM_DIV_SYNL_V(e) BF_PCM_DIV_SYNL(BV_PCM_DIV_SYNL__##e) | ||
237 | #define BFM_PCM_DIV_SYNL_V(v) BM_PCM_DIV_SYNL | ||
238 | #define BP_PCM_DIV_SYNDIV 6 | ||
239 | #define BM_PCM_DIV_SYNDIV 0x7c0 | ||
240 | #define BF_PCM_DIV_SYNDIV(v) (((v) & 0x1f) << 6) | ||
241 | #define BFM_PCM_DIV_SYNDIV(v) BM_PCM_DIV_SYNDIV | ||
242 | #define BF_PCM_DIV_SYNDIV_V(e) BF_PCM_DIV_SYNDIV(BV_PCM_DIV_SYNDIV__##e) | ||
243 | #define BFM_PCM_DIV_SYNDIV_V(v) BM_PCM_DIV_SYNDIV | ||
244 | #define BP_PCM_DIV_CLKDIV 0 | ||
245 | #define BM_PCM_DIV_CLKDIV 0x3f | ||
246 | #define BF_PCM_DIV_CLKDIV(v) (((v) & 0x3f) << 0) | ||
247 | #define BFM_PCM_DIV_CLKDIV(v) BM_PCM_DIV_CLKDIV | ||
248 | #define BF_PCM_DIV_CLKDIV_V(e) BF_PCM_DIV_CLKDIV(BV_PCM_DIV_CLKDIV__##e) | ||
249 | #define BFM_PCM_DIV_CLKDIV_V(v) BM_PCM_DIV_CLKDIV | ||
250 | |||
251 | #endif /* __HEADERGEN_PCM_H__*/ | ||