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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 20:08:49 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-17 00:29:24 +0200 |
commit | f5ac658d160d11880c2affa9c5b669404c4fe207 (patch) | |
tree | 120f5e132430ea032d12d765fc6f407c020a908e | |
parent | 84fc327aeb7be91e611520bb058a6c8d318401c3 (diff) | |
download | rockbox-f5ac658d160d11880c2affa9c5b669404c4fe207.tar.gz rockbox-f5ac658d160d11880c2affa9c5b669404c4fe207.zip |
imx233: normalise clkctrl
The clkctrl functions were becoming a mess. Normalise the names,
get rid of the xtal derived as special case and use the same
interface.
Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
-rw-r--r-- | firmware/target/arm/imx233/audioout-imx233.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 151 | ||||
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.h | 76 | ||||
-rw-r--r-- | firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/imx233/debug-imx233.c | 66 | ||||
-rw-r--r-- | firmware/target/arm/imx233/pwm-imx233.c | 5 | ||||
-rw-r--r-- | firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/imx233/ssp-imx233.c | 19 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 48 | ||||
-rw-r--r-- | firmware/target/arm/imx233/timrot-imx233.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/imx233/usb-imx233.c | 4 |
12 files changed, 154 insertions, 245 deletions
diff --git a/firmware/target/arm/imx233/audioout-imx233.c b/firmware/target/arm/imx233/audioout-imx233.c index 8f71655699..8903879b8a 100644 --- a/firmware/target/arm/imx233/audioout-imx233.c +++ b/firmware/target/arm/imx233/audioout-imx233.c | |||
@@ -40,7 +40,7 @@ void imx233_audioout_preinit(void) | |||
40 | /* Enable AUDIOOUT block */ | 40 | /* Enable AUDIOOUT block */ |
41 | imx233_reset_block(&HW_AUDIOOUT_CTRL); | 41 | imx233_reset_block(&HW_AUDIOOUT_CTRL); |
42 | /* Enable digital filter clock */ | 42 | /* Enable digital filter clock */ |
43 | imx233_clkctrl_enable_xtal(XTAL_FILT, true); | 43 | imx233_clkctrl_enable(CLK_FILT, true); |
44 | /* Enable DAC */ | 44 | /* Enable DAC */ |
45 | BF_CLR(AUDIOOUT_ANACLKCTRL, CLKGATE); | 45 | BF_CLR(AUDIOOUT_ANACLKCTRL, CLKGATE); |
46 | /* Set capless mode */ | 46 | /* Set capless mode */ |
@@ -97,7 +97,7 @@ void imx233_audioout_close(void) | |||
97 | /* Gate off DAC */ | 97 | /* Gate off DAC */ |
98 | BF_SET(AUDIOOUT_ANACLKCTRL, CLKGATE); | 98 | BF_SET(AUDIOOUT_ANACLKCTRL, CLKGATE); |
99 | /* Disable digital filter clock */ | 99 | /* Disable digital filter clock */ |
100 | imx233_clkctrl_enable_xtal(XTAL_FILT, false); | 100 | imx233_clkctrl_enable(CLK_FILT, false); |
101 | /* will also gate off the module */ | 101 | /* will also gate off the module */ |
102 | BF_CLR(AUDIOOUT_CTRL, RUN); | 102 | BF_CLR(AUDIOOUT_CTRL, RUN); |
103 | } | 103 | } |
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 1553889543..102ef4e432 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
@@ -20,29 +20,19 @@ | |||
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include "clkctrl-imx233.h" | 21 | #include "clkctrl-imx233.h" |
22 | 22 | ||
23 | #define __CLK_CLKGATE (1 << 31) | 23 | void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable) |
24 | #define __CLK_BUSY (1 << 29) | ||
25 | |||
26 | void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable) | ||
27 | { | ||
28 | if(enable) | ||
29 | HW_CLKCTRL_XTAL_CLR = xtal_clk; | ||
30 | else | ||
31 | HW_CLKCTRL_XTAL_SET = xtal_clk; | ||
32 | } | ||
33 | |||
34 | bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk) | ||
35 | { | ||
36 | return HW_CLKCTRL_XTAL & clk; | ||
37 | } | ||
38 | |||
39 | void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable) | ||
40 | { | 24 | { |
25 | /* NOTE some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */ | ||
41 | bool gate = !enable; | 26 | bool gate = !enable; |
42 | switch(clk) | 27 | switch(clk) |
43 | { | 28 | { |
44 | case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break; | 29 | case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break; |
45 | case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break; | 30 | case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break; |
31 | case CLK_DRI: BF_WR(CLKCTRL_XTAL, DRI_CLK24M_GATE, gate); break; | ||
32 | case CLK_PWM: BF_WR(CLKCTRL_XTAL, PWM_CLK24M_GATE, gate); break; | ||
33 | case CLK_UART: BF_WR(CLKCTRL_XTAL, UART_CLK_GATE, gate); break; | ||
34 | case CLK_FILT: BF_WR(CLKCTRL_XTAL, FILT_CLK24M_GATE, gate); break; | ||
35 | case CLK_TIMROT: BF_WR(CLKCTRL_XTAL, TIMROT_CLK32K_GATE, gate); break; | ||
46 | case CLK_PLL: | 36 | case CLK_PLL: |
47 | /* pll is a special case */ | 37 | /* pll is a special case */ |
48 | if(enable) | 38 | if(enable) |
@@ -58,18 +48,23 @@ void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable) | |||
58 | } | 48 | } |
59 | } | 49 | } |
60 | 50 | ||
61 | bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk) | 51 | bool imx233_clkctrl_is_enabled(enum imx233_clock_t clk) |
62 | { | 52 | { |
63 | switch(clk) | 53 | switch(clk) |
64 | { | 54 | { |
65 | case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER); | 55 | case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER); |
66 | case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE); | 56 | case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE); |
67 | case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE); | 57 | case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE); |
58 | case CLK_DRI: return !BF_RD(CLKCTRL_XTAL, DRI_CLK24M_GATE); | ||
59 | case CLK_PWM: return !BF_RD(CLKCTRL_XTAL, PWM_CLK24M_GATE); | ||
60 | case CLK_UART: return !BF_RD(CLKCTRL_XTAL, UART_CLK_GATE); | ||
61 | case CLK_FILT: return !BF_RD(CLKCTRL_XTAL, FILT_CLK24M_GATE); | ||
62 | case CLK_TIMROT: return !BF_RD(CLKCTRL_XTAL, TIMROT_CLK32K_GATE); | ||
68 | default: return true; | 63 | default: return true; |
69 | } | 64 | } |
70 | } | 65 | } |
71 | 66 | ||
72 | void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div) | 67 | void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div) |
73 | { | 68 | { |
74 | /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! | 69 | /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! |
75 | * assume that we always derive emi and cpu from ref_XX */ | 70 | * assume that we always derive emi and cpu from ref_XX */ |
@@ -85,7 +80,7 @@ void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
85 | } | 80 | } |
86 | } | 81 | } |
87 | 82 | ||
88 | int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk) | 83 | int imx233_clkctrl_get_div(enum imx233_clock_t clk) |
89 | { | 84 | { |
90 | switch(clk) | 85 | switch(clk) |
91 | { | 86 | { |
@@ -99,7 +94,7 @@ int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk) | |||
99 | } | 94 | } |
100 | } | 95 | } |
101 | 96 | ||
102 | void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | 97 | void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv) |
103 | { | 98 | { |
104 | #define handle_frac(dev) \ | 99 | #define handle_frac(dev) \ |
105 | case CLK_##dev: \ | 100 | case CLK_##dev: \ |
@@ -120,7 +115,7 @@ void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | |||
120 | #undef handle_frac | 115 | #undef handle_frac |
121 | } | 116 | } |
122 | 117 | ||
123 | int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk) | 118 | int imx233_clkctrl_get_frac_div(enum imx233_clock_t clk) |
124 | { | 119 | { |
125 | #define handle_frac(dev) \ | 120 | #define handle_frac(dev) \ |
126 | case CLK_##dev:\ | 121 | case CLK_##dev:\ |
@@ -139,7 +134,7 @@ int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk) | |||
139 | #undef handle_frac | 134 | #undef handle_frac |
140 | } | 135 | } |
141 | 136 | ||
142 | void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | 137 | void imx233_clkctrl_set_bypass(enum imx233_clock_t clk, bool bypass) |
143 | { | 138 | { |
144 | uint32_t msk; | 139 | uint32_t msk; |
145 | switch(clk) | 140 | switch(clk) |
@@ -157,7 +152,7 @@ void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | |||
157 | HW_CLKCTRL_CLKSEQ_CLR = msk; | 152 | HW_CLKCTRL_CLKSEQ_CLR = msk; |
158 | } | 153 | } |
159 | 154 | ||
160 | bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk) | 155 | bool imx233_clkctrl_get_bypass(enum imx233_clock_t clk) |
161 | { | 156 | { |
162 | switch(clk) | 157 | switch(clk) |
163 | { | 158 | { |
@@ -169,7 +164,7 @@ bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk) | |||
169 | } | 164 | } |
170 | } | 165 | } |
171 | 166 | ||
172 | void imx233_clkctrl_enable_usb_pll(bool enable) | 167 | void imx233_clkctrl_enable_usb(bool enable) |
173 | { | 168 | { |
174 | if(enable) | 169 | if(enable) |
175 | BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS); | 170 | BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS); |
@@ -177,12 +172,12 @@ void imx233_clkctrl_enable_usb_pll(bool enable) | |||
177 | BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS); | 172 | BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS); |
178 | } | 173 | } |
179 | 174 | ||
180 | bool imx233_clkctrl_is_usb_pll_enabled(void) | 175 | bool imx233_clkctrl_is_usb_enabled(void) |
181 | { | 176 | { |
182 | return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS); | 177 | return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS); |
183 | } | 178 | } |
184 | 179 | ||
185 | void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div) | 180 | void imx233_clkctrl_set_auto_slow_div(unsigned div) |
186 | { | 181 | { |
187 | /* the SLOW_DIV must only be set when auto-slow is disabled */ | 182 | /* the SLOW_DIV must only be set when auto-slow is disabled */ |
188 | bool old_status = imx233_clkctrl_is_auto_slow_enabled(); | 183 | bool old_status = imx233_clkctrl_is_auto_slow_enabled(); |
@@ -191,7 +186,7 @@ void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div) | |||
191 | imx233_clkctrl_enable_auto_slow(old_status); | 186 | imx233_clkctrl_enable_auto_slow(old_status); |
192 | } | 187 | } |
193 | 188 | ||
194 | enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void) | 189 | unsigned imx233_clkctrl_get_auto_slow_div(void) |
195 | { | 190 | { |
196 | return BF_RD(CLKCTRL_HBUS, SLOW_DIV); | 191 | return BF_RD(CLKCTRL_HBUS, SLOW_DIV); |
197 | } | 192 | } |
@@ -206,30 +201,12 @@ bool imx233_clkctrl_is_auto_slow_enabled(void) | |||
206 | return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE); | 201 | return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE); |
207 | } | 202 | } |
208 | 203 | ||
209 | void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable) | 204 | unsigned imx233_clkctrl_get_freq(enum imx233_clock_t clk) |
210 | { | ||
211 | if(enable) | ||
212 | HW_CLKCTRL_HBUS_SET = monitor; | ||
213 | else | ||
214 | HW_CLKCTRL_HBUS_CLR = monitor; | ||
215 | } | ||
216 | |||
217 | bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor) | ||
218 | { | ||
219 | return HW_CLKCTRL_HBUS & monitor; | ||
220 | } | ||
221 | |||
222 | bool imx233_clkctrl_is_emi_sync_enabled(void) | ||
223 | { | ||
224 | return BF_RD(CLKCTRL_EMI, SYNC_MODE_EN); | ||
225 | } | ||
226 | |||
227 | unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk) | ||
228 | { | 205 | { |
229 | switch(clk) | 206 | switch(clk) |
230 | { | 207 | { |
231 | case CLK_PLL: /* PLL: 480MHz when enable */ | 208 | case CLK_PLL: /* PLL: 480MHz when enable */ |
232 | return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0; | 209 | return imx233_clkctrl_is_enabled(CLK_PLL) ? 480000 : 0; |
233 | case CLK_XTAL: /* crystal: 24MHz */ | 210 | case CLK_XTAL: /* crystal: 24MHz */ |
234 | return 24000; | 211 | return 24000; |
235 | case CLK_CPU: | 212 | case CLK_CPU: |
@@ -238,78 +215,78 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk) | |||
238 | /* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider | 215 | /* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider |
239 | * otherwise, clk_p derived from clk_cpu via int div and clk_cpu | 216 | * otherwise, clk_p derived from clk_cpu via int div and clk_cpu |
240 | * derived from clk_pll fracdiv */ | 217 | * derived from clk_pll fracdiv */ |
241 | if(imx233_clkctrl_get_bypass_pll(CLK_CPU)) | 218 | if(imx233_clkctrl_get_bypass(CLK_CPU)) |
242 | { | 219 | { |
243 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); | 220 | ref = imx233_clkctrl_get_freq(CLK_XTAL); |
244 | /* Integer divide mode vs fractional divide mode */ | 221 | /* Integer divide mode vs fractional divide mode */ |
245 | if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN)) | 222 | if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN)) |
246 | 223 | ||
247 | return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32; | 224 | return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32; |
248 | else | 225 | else |
249 | return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); | 226 | return ref / imx233_clkctrl_get_div(CLK_CPU); |
250 | } | 227 | } |
251 | else | 228 | else |
252 | { | 229 | { |
253 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); | 230 | ref = imx233_clkctrl_get_freq(CLK_PLL); |
254 | /* fractional divider enable ? */ | 231 | /* fractional divider enable ? */ |
255 | if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0) | 232 | if(imx233_clkctrl_get_frac_div(CLK_CPU) != 0) |
256 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU); | 233 | ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_CPU); |
257 | return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); | 234 | return ref / imx233_clkctrl_get_div(CLK_CPU); |
258 | } | 235 | } |
259 | } | 236 | } |
260 | case CLK_HBUS: | 237 | case CLK_HBUS: |
261 | { | 238 | { |
262 | /* Derived from clk_p via integer/fractional div */ | 239 | /* Derived from clk_p via integer/fractional div */ |
263 | unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU); | 240 | unsigned ref = imx233_clkctrl_get_freq(CLK_CPU); |
264 | if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0) | 241 | if(imx233_clkctrl_get_frac_div(CLK_HBUS) != 0) |
265 | ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32; | 242 | ref = (ref * imx233_clkctrl_get_frac_div(CLK_HBUS)) / 32; |
266 | if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0) | 243 | if(imx233_clkctrl_get_div(CLK_HBUS) != 0) |
267 | ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS); | 244 | ref /= imx233_clkctrl_get_div(CLK_HBUS); |
268 | return ref; | 245 | return ref; |
269 | } | 246 | } |
270 | case CLK_IO: | 247 | case CLK_IO: |
271 | { | 248 | { |
272 | /* Derived from clk_pll via fracdiv */ | 249 | /* Derived from clk_pll via fracdiv */ |
273 | unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL); | 250 | unsigned ref = imx233_clkctrl_get_freq(CLK_PLL); |
274 | if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0) | 251 | if(imx233_clkctrl_get_frac_div(CLK_IO) != 0) |
275 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO); | 252 | ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_IO); |
276 | return ref; | 253 | return ref; |
277 | } | 254 | } |
278 | case CLK_PIX: | 255 | case CLK_PIX: |
279 | { | 256 | { |
280 | unsigned ref; | 257 | unsigned ref; |
281 | /* Derived from clk_pll or clk_xtal */ | 258 | /* Derived from clk_pll or clk_xtal */ |
282 | if(!imx233_clkctrl_is_clock_enabled(CLK_PIX)) | 259 | if(!imx233_clkctrl_is_enabled(CLK_PIX)) |
283 | ref = 0; | 260 | ref = 0; |
284 | else if(imx233_clkctrl_get_bypass_pll(CLK_PIX)) | 261 | else if(imx233_clkctrl_get_bypass(CLK_PIX)) |
285 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); | 262 | ref = imx233_clkctrl_get_freq(CLK_XTAL); |
286 | else | 263 | else |
287 | { | 264 | { |
288 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); | 265 | ref = imx233_clkctrl_get_freq(CLK_PLL); |
289 | if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0) | 266 | if(imx233_clkctrl_get_frac_div(CLK_PIX) != 0) |
290 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX); | 267 | ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_PIX); |
291 | } | 268 | } |
292 | return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX); | 269 | return ref / imx233_clkctrl_get_div(CLK_PIX); |
293 | } | 270 | } |
294 | case CLK_SSP: | 271 | case CLK_SSP: |
295 | { | 272 | { |
296 | unsigned ref; | 273 | unsigned ref; |
297 | /* Derived from clk_pll or clk_xtal */ | 274 | /* Derived from clk_pll or clk_xtal */ |
298 | if(!imx233_clkctrl_is_clock_enabled(CLK_SSP)) | 275 | if(!imx233_clkctrl_is_enabled(CLK_SSP)) |
299 | ref = 0; | 276 | ref = 0; |
300 | else if(imx233_clkctrl_get_bypass_pll(CLK_SSP)) | 277 | else if(imx233_clkctrl_get_bypass(CLK_SSP)) |
301 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); | 278 | ref = imx233_clkctrl_get_freq(CLK_XTAL); |
302 | else | 279 | else |
303 | ref = imx233_clkctrl_get_clock_freq(CLK_IO); | 280 | ref = imx233_clkctrl_get_freq(CLK_IO); |
304 | return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP); | 281 | return ref / imx233_clkctrl_get_div(CLK_SSP); |
305 | } | 282 | } |
306 | case CLK_EMI: | 283 | case CLK_EMI: |
307 | { | 284 | { |
308 | unsigned ref; | 285 | unsigned ref; |
309 | /* Derived from clk_pll or clk_xtal */ | 286 | /* Derived from clk_pll or clk_xtal */ |
310 | if(imx233_clkctrl_get_bypass_pll(CLK_EMI)) | 287 | if(imx233_clkctrl_get_bypass(CLK_EMI)) |
311 | { | 288 | { |
312 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); | 289 | ref = imx233_clkctrl_get_freq(CLK_XTAL); |
313 | if(BF_RD(CLKCTRL_EMI, CLKGATE)) | 290 | if(BF_RD(CLKCTRL_EMI, CLKGATE)) |
314 | return 0; | 291 | return 0; |
315 | else | 292 | else |
@@ -317,16 +294,24 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk) | |||
317 | } | 294 | } |
318 | else | 295 | else |
319 | { | 296 | { |
320 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); | 297 | ref = imx233_clkctrl_get_freq(CLK_PLL); |
321 | if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0) | 298 | if(imx233_clkctrl_get_frac_div(CLK_EMI) != 0) |
322 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI); | 299 | ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_EMI); |
323 | return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI); | 300 | return ref / imx233_clkctrl_get_div(CLK_EMI); |
324 | } | 301 | } |
325 | } | 302 | } |
326 | case CLK_XBUS: | 303 | case CLK_XBUS: |
327 | return imx233_clkctrl_get_clock_freq(CLK_XTAL) / | 304 | return imx233_clkctrl_get_freq(CLK_XTAL) / imx233_clkctrl_get_div(CLK_XBUS); |
328 | imx233_clkctrl_get_clock_divisor(CLK_XBUS); | ||
329 | default: | 305 | default: |
330 | return 0; | 306 | return 0; |
331 | } | 307 | } |
332 | } | 308 | } |
309 | |||
310 | void imx233_clkctrl_init(void) | ||
311 | { | ||
312 | /* set auto-slow monitor to all */ | ||
313 | HW_CLKCTRL_HBUS_SET = BF_OR8(CLKCTRL_HBUS, | ||
314 | APBHDMA_AS_ENABLE(1), TRAFFIC_JAM_AS_ENABLE(1), TRAFFIC_AS_ENABLE(1), | ||
315 | APBXDMA_AS_ENABLE(1), CPU_INSTR_AS_ENABLE(1), CPU_DATA_AS_ENABLE(1), | ||
316 | DCP_AS_ENABLE(1), PXP_AS_ENABLE(1)); | ||
317 | } | ||
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h index a15adb367e..ddd8bc9221 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.h +++ b/firmware/target/arm/imx233/clkctrl-imx233.h | |||
@@ -50,67 +50,33 @@ enum imx233_clock_t | |||
50 | CLK_XTAL, /* freq */ | 50 | CLK_XTAL, /* freq */ |
51 | CLK_EMI, /* freq, div, frac, bypass */ | 51 | CLK_EMI, /* freq, div, frac, bypass */ |
52 | CLK_XBUS, /* freq, div */ | 52 | CLK_XBUS, /* freq, div */ |
53 | CLK_FILT, /* enable */ | ||
54 | CLK_DRI, /* enable */ | ||
55 | CLK_PWM, /* enable */ | ||
56 | CLK_TIMROT, /* enable */ | ||
57 | CLK_UART, /* enable */ | ||
53 | }; | 58 | }; |
54 | 59 | ||
55 | enum imx233_xtal_clk_t | 60 | void imx233_clkctrl_init(void); |
56 | { | ||
57 | XTAL_FILT = 1 << 30, | ||
58 | XTAL_DRI = 1 << 28, | ||
59 | XTAL_TIMROT = 1 << 26, | ||
60 | XTAM_PWM = 1 << 29, | ||
61 | }; | ||
62 | |||
63 | /* Auto-Slow monitoring */ | ||
64 | enum imx233_as_monitor_t | ||
65 | { | ||
66 | AS_NONE = 0, /* Do not monitor any activity */ | ||
67 | AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */ | ||
68 | AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */ | ||
69 | AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */ | ||
70 | AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */ | ||
71 | AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */ | ||
72 | AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */ | ||
73 | AS_PXP = 1 << 27, /* Monitor PXP activity */ | ||
74 | AS_DCP = 1 << 28, /* Monitor DCP activity */ | ||
75 | AS_ALL = 0xff << 21, /* Monitor all activity */ | ||
76 | }; | ||
77 | |||
78 | enum imx233_as_div_t | ||
79 | { | ||
80 | AS_DIV_1 = 0, | ||
81 | AS_DIV_2 = 1, | ||
82 | AS_DIV_4 = 2, | ||
83 | AS_DIV_8 = 3, | ||
84 | AS_DIV_16 = 4, | ||
85 | AS_DIV_32 = 5 | ||
86 | }; | ||
87 | |||
88 | /* can use a mask of clocks */ | ||
89 | void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable); | ||
90 | void imx233_clkctrl_is_xtal_enabled(enum imx233_xtal_clk_t xtal_clk, bool enable); | ||
91 | /* only use it for non-fractional clocks (ie not for IO) */ | 61 | /* only use it for non-fractional clocks (ie not for IO) */ |
92 | void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable); | 62 | void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable); |
93 | bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t cl); | 63 | bool imx233_clkctrl_is_enabled(enum imx233_clock_t cl); |
94 | void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div); | 64 | void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div); |
95 | int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk); | 65 | int imx233_clkctrl_get_div(enum imx233_clock_t clk); |
96 | /* call with fracdiv=0 to disable it */ | 66 | /* call with fracdiv=0 to disable it */ |
97 | void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); | 67 | void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv); |
98 | /* 0 means fractional dividor disable */ | 68 | /* 0 means fractional dividor disable */ |
99 | int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk); | 69 | int imx233_clkctrl_get_frac_div(enum imx233_clock_t clk); |
100 | void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass); | 70 | void imx233_clkctrl_set_bypass(enum imx233_clock_t clk, bool bypass); |
101 | bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk); | 71 | bool imx233_clkctrl_get_bypass(enum imx233_clock_t clk); |
102 | void imx233_clkctrl_enable_usb_pll(bool enable); | 72 | void imx233_clkctrl_enable_usb(bool enable); |
103 | bool imx233_clkctrl_is_usb_pll_enabled(void); | 73 | bool imx233_clkctrl_is_usb_enabled(void); |
104 | unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk); | 74 | /* returns frequency in KHz */ |
105 | 75 | unsigned imx233_clkctrl_get_freq(enum imx233_clock_t clk); | |
106 | bool imx233_clkctrl_is_emi_sync_enabled(void); | 76 | /* auto-slow stuff */ |
107 | 77 | void imx233_clkctrl_set_auto_slow_div(unsigned div); | |
108 | void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div); | 78 | unsigned imx233_clkctrl_get_auto_slow_div(void); |
109 | enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void); | ||
110 | void imx233_clkctrl_enable_auto_slow(bool enable); | 79 | void imx233_clkctrl_enable_auto_slow(bool enable); |
111 | bool imx233_clkctrl_is_auto_slow_enabled(void); | 80 | bool imx233_clkctrl_is_auto_slow_enabled(void); |
112 | /* can use a mask of clocks */ | ||
113 | void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable); | ||
114 | bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor); | ||
115 | 81 | ||
116 | #endif /* CLKCTRL_IMX233_H */ | 82 | #endif /* CLKCTRL_IMX233_H */ |
diff --git a/firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c b/firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c index 0a16c995c1..1e60e60463 100644 --- a/firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c +++ b/firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c | |||
@@ -110,10 +110,10 @@ static inline uint32_t decode_18_to_16(uint32_t a) | |||
110 | static void setup_lcdif_clock(void) | 110 | static void setup_lcdif_clock(void) |
111 | { | 111 | { |
112 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ | 112 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ |
113 | imx233_clkctrl_enable_clock(CLK_PIX, false); | 113 | imx233_clkctrl_enable(CLK_PIX, false); |
114 | imx233_clkctrl_set_clock_divisor(CLK_PIX, 1); | 114 | imx233_clkctrl_set_div(CLK_PIX, 1); |
115 | imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */ | 115 | imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */ |
116 | imx233_clkctrl_enable_clock(CLK_PIX, true); | 116 | imx233_clkctrl_enable(CLK_PIX, true); |
117 | } | 117 | } |
118 | 118 | ||
119 | static void lcd_write_reg(uint32_t reg, uint32_t data) | 119 | static void lcd_write_reg(uint32_t reg, uint32_t data) |
diff --git a/firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c b/firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c index 253f37eef6..de9e2df393 100644 --- a/firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c +++ b/firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c | |||
@@ -97,10 +97,10 @@ static void setup_lcdif(void) | |||
97 | static void setup_lcdif_clock(void) | 97 | static void setup_lcdif_clock(void) |
98 | { | 98 | { |
99 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ | 99 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ |
100 | imx233_clkctrl_enable_clock(CLK_PIX, false); | 100 | imx233_clkctrl_enable(CLK_PIX, false); |
101 | imx233_clkctrl_set_clock_divisor(CLK_PIX, 1); | 101 | imx233_clkctrl_set_div(CLK_PIX, 1); |
102 | imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */ | 102 | imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */ |
103 | imx233_clkctrl_enable_clock(CLK_PIX, true); | 103 | imx233_clkctrl_enable(CLK_PIX, true); |
104 | } | 104 | } |
105 | 105 | ||
106 | static void lcd_write_reg(uint32_t reg, uint32_t data) | 106 | static void lcd_write_reg(uint32_t reg, uint32_t data) |
diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c index ff3313a59e..7cb217f40f 100644 --- a/firmware/target/arm/imx233/debug-imx233.c +++ b/firmware/target/arm/imx233/debug-imx233.c | |||
@@ -242,26 +242,10 @@ static struct | |||
242 | { CLK_XBUS, "xbus", false, false, true, false, true } | 242 | { CLK_XBUS, "xbus", false, false, true, false, true } |
243 | }; | 243 | }; |
244 | 244 | ||
245 | static struct | ||
246 | { | ||
247 | enum imx233_as_monitor_t monitor; | ||
248 | const char *name; | ||
249 | } dbg_as_monitor[] = | ||
250 | { | ||
251 | { AS_CPU_INSTR, "cpu inst" }, | ||
252 | { AS_CPU_DATA, "cpu data" }, | ||
253 | { AS_TRAFFIC, "traffic" }, | ||
254 | { AS_TRAFFIC_JAM, "traffic jam" }, | ||
255 | { AS_APBXDMA, "apbx" }, | ||
256 | { AS_APBHDMA, "apbh" }, | ||
257 | { AS_PXP, "pxp" }, | ||
258 | { AS_DCP, "dcp" } | ||
259 | }; | ||
260 | |||
261 | bool dbg_hw_info_clkctrl(void) | 245 | bool dbg_hw_info_clkctrl(void) |
262 | { | 246 | { |
263 | lcd_setfont(FONT_SYSFIXED); | 247 | lcd_setfont(FONT_SYSFIXED); |
264 | 248 | ||
265 | while(1) | 249 | while(1) |
266 | { | 250 | { |
267 | int button = get_action(CONTEXT_STD, HZ / 10); | 251 | int button = get_action(CONTEXT_STD, HZ / 10); |
@@ -277,7 +261,7 @@ bool dbg_hw_info_clkctrl(void) | |||
277 | lcd_setfont(FONT_UI); | 261 | lcd_setfont(FONT_UI); |
278 | return false; | 262 | return false; |
279 | } | 263 | } |
280 | 264 | ||
281 | lcd_clear_display(); | 265 | lcd_clear_display(); |
282 | 266 | ||
283 | /* 012345678901234567890123456789 */ | 267 | /* 012345678901234567890123456789 */ |
@@ -287,45 +271,23 @@ bool dbg_hw_info_clkctrl(void) | |||
287 | #define c dbg_clk[i] | 271 | #define c dbg_clk[i] |
288 | lcd_putsf(0, i + 1, "%4s", c.name); | 272 | lcd_putsf(0, i + 1, "%4s", c.name); |
289 | if(c.has_enable) | 273 | if(c.has_enable) |
290 | lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_clock_enabled(c.clk)); | 274 | lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_enabled(c.clk)); |
291 | if(c.has_bypass) | 275 | if(c.has_bypass) |
292 | lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass_pll(c.clk)); | 276 | lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass(c.clk)); |
293 | if(c.has_idiv && imx233_clkctrl_get_clock_divisor(c.clk) != 0) | 277 | if(c.has_idiv && imx233_clkctrl_get_div(c.clk) != 0) |
294 | lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_clock_divisor(c.clk)); | 278 | lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_div(c.clk)); |
295 | if(c.has_fdiv && imx233_clkctrl_get_fractional_divisor(c.clk) != 0) | 279 | if(c.has_fdiv && imx233_clkctrl_get_frac_div(c.clk) != 0) |
296 | lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_fractional_divisor(c.clk)); | 280 | lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_frac_div(c.clk)); |
297 | if(c.has_freq) | 281 | if(c.has_freq) |
298 | lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_clock_freq(c.clk)); | 282 | lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_freq(c.clk)); |
299 | #undef c | 283 | #undef c |
300 | } | 284 | } |
301 | int line = ARRAYLEN(dbg_clk) + 1; | 285 | int line = ARRAYLEN(dbg_clk) + 1; |
302 | lcd_putsf(0, line, "as: %d/%d emi sync: %d", imx233_clkctrl_is_auto_slow_enabled(), | 286 | if(!imx233_clkctrl_is_auto_slow_enabled()) |
303 | 1 << imx233_clkctrl_get_auto_slow_divisor(), imx233_clkctrl_is_emi_sync_enabled()); | 287 | lcd_putsf(0, line++, "auto-slow: disabled"); |
304 | line++; | 288 | else |
305 | lcd_putsf(0, line, "as monitor: "); | 289 | lcd_putsf(0, line++, "auto-slow: 1/%d", 1 << imx233_clkctrl_get_auto_slow_div()); |
306 | int x_off = 12; | 290 | |
307 | bool first = true; | ||
308 | unsigned line_w = lcd_getwidth() / font_get_width(font_get(lcd_getfont()), ' '); | ||
309 | for(unsigned i = 0; i < ARRAYLEN(dbg_as_monitor); i++) | ||
310 | { | ||
311 | if(!imx233_clkctrl_is_auto_slow_monitor_enabled(dbg_as_monitor[i].monitor)) | ||
312 | continue; | ||
313 | if(!first) | ||
314 | { | ||
315 | lcd_putsf(x_off, line, ", "); | ||
316 | x_off += 2; | ||
317 | } | ||
318 | first = false; | ||
319 | if((x_off + strlen(dbg_as_monitor[i].name)) > line_w) | ||
320 | { | ||
321 | x_off = 1; | ||
322 | line++; | ||
323 | } | ||
324 | lcd_putsf(x_off, line, "%s", dbg_as_monitor[i].name); | ||
325 | x_off += strlen(dbg_as_monitor[i].name); | ||
326 | } | ||
327 | line++; | ||
328 | |||
329 | lcd_update(); | 291 | lcd_update(); |
330 | yield(); | 292 | yield(); |
331 | } | 293 | } |
diff --git a/firmware/target/arm/imx233/pwm-imx233.c b/firmware/target/arm/imx233/pwm-imx233.c index 00aba9320e..c434338a07 100644 --- a/firmware/target/arm/imx233/pwm-imx233.c +++ b/firmware/target/arm/imx233/pwm-imx233.c | |||
@@ -25,7 +25,7 @@ | |||
25 | void imx233_pwm_init(void) | 25 | void imx233_pwm_init(void) |
26 | { | 26 | { |
27 | imx233_reset_block(&HW_PWM_CTRL); | 27 | imx233_reset_block(&HW_PWM_CTRL); |
28 | imx233_clkctrl_enable_xtal(XTAM_PWM, true); | 28 | imx233_clkctrl_enable(CLK_PWM, true); |
29 | } | 29 | } |
30 | 30 | ||
31 | bool imx233_pwm_is_channel_enable(int channel) | 31 | bool imx233_pwm_is_channel_enable(int channel) |
@@ -50,7 +50,8 @@ void imx233_pwm_setup_channel(int channel, int period, int cdiv, int active, | |||
50 | imx233_pwm_enable_channel(channel, false); | 50 | imx233_pwm_enable_channel(channel, false); |
51 | /* setup pin */ | 51 | /* setup pin */ |
52 | imx233_pinctrl_setup_vpin(VPIN_PWM(channel), "pwm", PINCTRL_DRIVE_4mA, false); | 52 | imx233_pinctrl_setup_vpin(VPIN_PWM(channel), "pwm", PINCTRL_DRIVE_4mA, false); |
53 | /* watch the order ! active THEN period */ | 53 | /* watch the order ! active THEN period |
54 | * NOTE: the register value is period-1 */ | ||
54 | HW_PWM_ACTIVEn(channel) = BF_OR2(PWM_ACTIVEn, ACTIVE(active), INACTIVE(inactive)); | 55 | HW_PWM_ACTIVEn(channel) = BF_OR2(PWM_ACTIVEn, ACTIVE(active), INACTIVE(inactive)); |
55 | HW_PWM_PERIODn(channel) = BF_OR4(PWM_PERIODn, PERIOD(period - 1), | 56 | HW_PWM_PERIODn(channel) = BF_OR4(PWM_PERIODn, PERIOD(period - 1), |
56 | ACTIVE_STATE(active_state), INACTIVE_STATE(inactive_state), CDIV(cdiv)); | 57 | ACTIVE_STATE(active_state), INACTIVE_STATE(inactive_state), CDIV(cdiv)); |
diff --git a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c index 1ca159786a..a99260f105 100644 --- a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c +++ b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c | |||
@@ -168,10 +168,10 @@ static inline uint32_t decode_18_to_16(uint32_t a) | |||
168 | static void setup_lcdif_clock(void) | 168 | static void setup_lcdif_clock(void) |
169 | { | 169 | { |
170 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ | 170 | /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ |
171 | imx233_clkctrl_enable_clock(CLK_PIX, false); | 171 | imx233_clkctrl_enable(CLK_PIX, false); |
172 | imx233_clkctrl_set_clock_divisor(CLK_PIX, 1); | 172 | imx233_clkctrl_set_div(CLK_PIX, 1); |
173 | imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */ | 173 | imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */ |
174 | imx233_clkctrl_enable_clock(CLK_PIX, true); | 174 | imx233_clkctrl_enable(CLK_PIX, true); |
175 | } | 175 | } |
176 | 176 | ||
177 | static uint32_t i80_read_register(uint32_t data_out) | 177 | static uint32_t i80_read_register(uint32_t data_out) |
diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c index 5f0880c2e9..295e64d810 100644 --- a/firmware/target/arm/imx233/ssp-imx233.c +++ b/firmware/target/arm/imx233/ssp-imx233.c | |||
@@ -114,7 +114,7 @@ void imx233_ssp_start(int ssp) | |||
114 | return; | 114 | return; |
115 | ssp_in_use[ssp - 1] = true; | 115 | ssp_in_use[ssp - 1] = true; |
116 | /* Gate block */ | 116 | /* Gate block */ |
117 | imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp)); | 117 | imx233_ssp_softreset(ssp); |
118 | /* Gate dma channel */ | 118 | /* Gate dma channel */ |
119 | imx233_dma_clkgate_channel(APB_SSP(ssp), true); | 119 | imx233_dma_clkgate_channel(APB_SSP(ssp), true); |
120 | /* If first block to start, start SSP clock */ | 120 | /* If first block to start, start SSP clock */ |
@@ -123,11 +123,11 @@ void imx233_ssp_start(int ssp) | |||
123 | /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */ | 123 | /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */ |
124 | /* fracdiv = 18 => clk_io = pll = 480Mhz | 124 | /* fracdiv = 18 => clk_io = pll = 480Mhz |
125 | * intdiv = 5 => clk_ssp = 96Mhz */ | 125 | * intdiv = 5 => clk_ssp = 96Mhz */ |
126 | imx233_clkctrl_set_fractional_divisor(CLK_IO, 18); | 126 | imx233_clkctrl_set_frac_div(CLK_IO, 18); |
127 | imx233_clkctrl_enable_clock(CLK_SSP, false); | 127 | imx233_clkctrl_enable(CLK_SSP, false); |
128 | imx233_clkctrl_set_clock_divisor(CLK_SSP, 5); | 128 | imx233_clkctrl_set_div(CLK_SSP, 5); |
129 | imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */ | 129 | imx233_clkctrl_set_bypass(CLK_SSP, false); /* use IO */ |
130 | imx233_clkctrl_enable_clock(CLK_SSP, true); | 130 | imx233_clkctrl_enable(CLK_SSP, true); |
131 | } | 131 | } |
132 | ssp_nr_in_use++; | 132 | ssp_nr_in_use++; |
133 | } | 133 | } |
@@ -145,16 +145,13 @@ void imx233_ssp_stop(int ssp) | |||
145 | /* If last block to stop, stop SSP clock */ | 145 | /* If last block to stop, stop SSP clock */ |
146 | ssp_nr_in_use--; | 146 | ssp_nr_in_use--; |
147 | if(ssp_nr_in_use == 0) | 147 | if(ssp_nr_in_use == 0) |
148 | { | 148 | imx233_clkctrl_enable(CLK_SSP, false); |
149 | imx233_clkctrl_enable_clock(CLK_SSP, false); | ||
150 | imx233_clkctrl_set_fractional_divisor(CLK_IO, 0); | ||
151 | } | ||
152 | } | 149 | } |
153 | 150 | ||
154 | void imx233_ssp_softreset(int ssp) | 151 | void imx233_ssp_softreset(int ssp) |
155 | { | 152 | { |
156 | ASSERT_SSP(ssp) | 153 | ASSERT_SSP(ssp) |
157 | imx233_reset_block(&HW_SSP_CTRL0(ssp)); | 154 | imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp)); |
158 | } | 155 | } |
159 | 156 | ||
160 | void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout) | 157 | void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout) |
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 8d705264bd..dcf3b82408 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -105,8 +105,12 @@ void system_init(void) | |||
105 | /* NOTE: don't use anything here that might require tick task ! | 105 | /* NOTE: don't use anything here that might require tick task ! |
106 | * It is initialized by kernel_init *after* system_init(). | 106 | * It is initialized by kernel_init *after* system_init(). |
107 | * The main() will naturally set cpu speed to normal after kernel_init() | 107 | * The main() will naturally set cpu speed to normal after kernel_init() |
108 | * so don't bother if the cpu is running at 24MHz here. */ | 108 | * so don't bother if the cpu is running at 24MHz here. |
109 | imx233_clkctrl_enable_clock(CLK_PLL, true); | 109 | * Make sure IO clock is running at expected speed */ |
110 | imx233_clkctrl_init(); | ||
111 | imx233_clkctrl_enable(CLK_PLL, true); | ||
112 | imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll | ||
113 | |||
110 | imx233_rtc_init(); | 114 | imx233_rtc_init(); |
111 | imx233_icoll_init(); | 115 | imx233_icoll_init(); |
112 | imx233_pinctrl_init(); | 116 | imx233_pinctrl_init(); |
@@ -119,19 +123,14 @@ void system_init(void) | |||
119 | imx233_power_init(); | 123 | imx233_power_init(); |
120 | imx233_i2c_init(); | 124 | imx233_i2c_init(); |
121 | 125 | ||
122 | imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_INSTR, true); | 126 | /* make sure auto-slow is disable now, we don't know at which frequency we |
123 | imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_DATA, true); | 127 | * are running and auto-slow could violate constraints on {xbus,hbus} */ |
124 | imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC, true); | 128 | imx233_clkctrl_enable_auto_slow(false); |
125 | imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC_JAM, true); | 129 | imx233_clkctrl_set_auto_slow_div(BV_CLKCTRL_HBUS_SLOW_DIV__BY8); |
126 | imx233_clkctrl_enable_auto_slow_monitor(AS_APBXDMA, true); | ||
127 | imx233_clkctrl_enable_auto_slow_monitor(AS_APBHDMA, true); | ||
128 | imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8); | ||
129 | imx233_clkctrl_enable_auto_slow(true); | ||
130 | 130 | ||
131 | cpu_frequency = imx233_clkctrl_get_clock_freq(CLK_CPU); | 131 | cpu_frequency = imx233_clkctrl_get_freq(CLK_CPU); |
132 | 132 | ||
133 | #if !defined(BOOTLOADER) &&(defined(SANSA_FUZEPLUS) || \ | 133 | #if CONFIG_TUNER |
134 | defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2)) | ||
135 | fmradio_i2c_init(); | 134 | fmradio_i2c_init(); |
136 | #endif | 135 | #endif |
137 | } | 136 | } |
@@ -210,7 +209,6 @@ void set_cpu_frequency(long frequency) | |||
210 | if(prof->cpu_freq == 0) | 209 | if(prof->cpu_freq == 0) |
211 | return; | 210 | return; |
212 | /* disable auto-slow (enable back afterwards) */ | 211 | /* disable auto-slow (enable back afterwards) */ |
213 | bool as = imx233_clkctrl_is_auto_slow_enabled(); | ||
214 | imx233_clkctrl_enable_auto_slow(false); | 212 | imx233_clkctrl_enable_auto_slow(false); |
215 | 213 | ||
216 | /* WARNING watch out the order ! */ | 214 | /* WARNING watch out the order ! */ |
@@ -221,28 +219,28 @@ void set_cpu_frequency(long frequency) | |||
221 | /* Change ARM cache timings */ | 219 | /* Change ARM cache timings */ |
222 | imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings); | 220 | imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings); |
223 | /* Switch CPU to crystal at 24MHz */ | 221 | /* Switch CPU to crystal at 24MHz */ |
224 | imx233_clkctrl_set_bypass_pll(CLK_CPU, true); | 222 | imx233_clkctrl_set_bypass(CLK_CPU, true); |
225 | /* Program CPU divider for PLL */ | 223 | /* Program CPU divider for PLL */ |
226 | imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv); | 224 | imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv); |
227 | imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv); | 225 | imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv); |
228 | /* Change the HBUS divider to its final value */ | 226 | /* Change the HBUS divider to its final value */ |
229 | imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div); | 227 | imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div); |
230 | /* Switch back CPU to PLL */ | 228 | /* Switch back CPU to PLL */ |
231 | imx233_clkctrl_set_bypass_pll(CLK_CPU, false); | 229 | imx233_clkctrl_set_bypass(CLK_CPU, false); |
232 | /* Set the new EMI frequency */ | 230 | /* Set the new EMI frequency */ |
233 | imx233_emi_set_frequency(prof->emi_freq); | 231 | imx233_emi_set_frequency(prof->emi_freq); |
234 | } | 232 | } |
235 | else | 233 | else |
236 | { | 234 | { |
237 | /* Switch CPU to crystal at 24MHz */ | 235 | /* Switch CPU to crystal at 24MHz */ |
238 | imx233_clkctrl_set_bypass_pll(CLK_CPU, true); | 236 | imx233_clkctrl_set_bypass(CLK_CPU, true); |
239 | /* Program HBUS divider to its final value */ | 237 | /* Program HBUS divider to its final value */ |
240 | imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div); | 238 | imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div); |
241 | /* Program CPU divider for PLL */ | 239 | /* Program CPU divider for PLL */ |
242 | imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv); | 240 | imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv); |
243 | imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv); | 241 | imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv); |
244 | /* Switch back CPU to PLL */ | 242 | /* Switch back CPU to PLL */ |
245 | imx233_clkctrl_set_bypass_pll(CLK_CPU, false); | 243 | imx233_clkctrl_set_bypass(CLK_CPU, false); |
246 | /* Set the new EMI frequency */ | 244 | /* Set the new EMI frequency */ |
247 | imx233_emi_set_frequency(prof->emi_freq); | 245 | imx233_emi_set_frequency(prof->emi_freq); |
248 | /* Change ARM cache timings */ | 246 | /* Change ARM cache timings */ |
@@ -251,7 +249,7 @@ void set_cpu_frequency(long frequency) | |||
251 | imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo); | 249 | imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo); |
252 | } | 250 | } |
253 | /* enable auto slow again */ | 251 | /* enable auto slow again */ |
254 | imx233_clkctrl_enable_auto_slow(as); | 252 | imx233_clkctrl_enable_auto_slow(true); |
255 | /* update frequency */ | 253 | /* update frequency */ |
256 | cpu_frequency = frequency; | 254 | cpu_frequency = frequency; |
257 | } | 255 | } |
diff --git a/firmware/target/arm/imx233/timrot-imx233.c b/firmware/target/arm/imx233/timrot-imx233.c index 723ecc31ab..848f640b5c 100644 --- a/firmware/target/arm/imx233/timrot-imx233.c +++ b/firmware/target/arm/imx233/timrot-imx233.c | |||
@@ -62,5 +62,5 @@ void imx233_timrot_init(void) | |||
62 | { | 62 | { |
63 | imx233_reset_block(&HW_TIMROT_ROTCTRL); | 63 | imx233_reset_block(&HW_TIMROT_ROTCTRL); |
64 | /* enable xtal path to timrot */ | 64 | /* enable xtal path to timrot */ |
65 | imx233_clkctrl_enable_xtal(XTAL_TIMROT, true); | 65 | imx233_clkctrl_enable(CLK_TIMROT, true); |
66 | } | 66 | } |
diff --git a/firmware/target/arm/imx233/usb-imx233.c b/firmware/target/arm/imx233/usb-imx233.c index 4e7656f7ab..a4099ceecf 100644 --- a/firmware/target/arm/imx233/usb-imx233.c +++ b/firmware/target/arm/imx233/usb-imx233.c | |||
@@ -68,7 +68,7 @@ void usb_enable(bool on) | |||
68 | { | 68 | { |
69 | if(on) | 69 | if(on) |
70 | { | 70 | { |
71 | imx233_clkctrl_enable_usb_pll(true); | 71 | imx233_clkctrl_enable_usb(true); |
72 | imx233_enable_usb_phy(true); | 72 | imx233_enable_usb_phy(true); |
73 | imx233_enable_usb_controller(true); | 73 | imx233_enable_usb_controller(true); |
74 | usb_core_init(); | 74 | usb_core_init(); |
@@ -78,6 +78,6 @@ void usb_enable(bool on) | |||
78 | usb_core_exit(); | 78 | usb_core_exit(); |
79 | imx233_enable_usb_controller(false); | 79 | imx233_enable_usb_controller(false); |
80 | imx233_enable_usb_phy(false); | 80 | imx233_enable_usb_phy(false); |
81 | imx233_clkctrl_enable_usb_pll(false); | 81 | imx233_clkctrl_enable_usb(false); |
82 | } | 82 | } |
83 | } | 83 | } |