diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/SOURCES | 4 | ||||
-rw-r--r-- | firmware/app.lds | 105 | ||||
-rw-r--r-- | firmware/target/arm/crt0.S | 177 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/crt0.S | 355 | ||||
-rwxr-xr-x | firmware/target/arm/s3c2440/debug-s3c2440.c | 1 |
5 files changed, 453 insertions, 189 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 465d10e662..9f3b490e5e 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -333,8 +333,10 @@ target/arm/crt0-pp.S | |||
333 | #endif | 333 | #endif |
334 | #elif CONFIG_CPU == PNX0101 | 334 | #elif CONFIG_CPU == PNX0101 |
335 | target/arm/pnx0101/crt0-pnx0101.S | 335 | target/arm/pnx0101/crt0-pnx0101.S |
336 | #elif defined(OLYMPUS_MROBE_500) | 336 | #elif CONFIG_CPU==DM320 |
337 | target/arm/tms320dm320/crt0.S | 337 | target/arm/tms320dm320/crt0.S |
338 | #elif CONFIG_CPU==S3C2440 | ||
339 | target/arm/s3c2440/crt0.S | ||
338 | #elif defined(CPU_TCC77X) | 340 | #elif defined(CPU_TCC77X) |
339 | target/arm/tcc77x/crt0.S | 341 | target/arm/tcc77x/crt0.S |
340 | #elif defined(CPU_ARM) | 342 | #elif defined(CPU_ARM) |
diff --git a/firmware/app.lds b/firmware/app.lds index 3b53c6e46a..e3f6ef2e50 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -9,8 +9,10 @@ OUTPUT_FORMAT(elf32-littlearm) | |||
9 | OUTPUT_ARCH(arm) | 9 | OUTPUT_ARCH(arm) |
10 | #ifdef CPU_PP | 10 | #ifdef CPU_PP |
11 | INPUT(target/arm/crt0-pp.o) | 11 | INPUT(target/arm/crt0-pp.o) |
12 | #elif defined(OLYMPUS_MROBE_500) | 12 | #elif CONFIG_CPU==DM320 |
13 | INPUT(target/arm/tms320dm320/crt0.o) | 13 | INPUT(target/arm/tms320dm320/crt0.o) |
14 | #elif CONFIG_CPU==S3C2440 | ||
15 | INPUT(target/arm/s3c2440/crt0.o) | ||
14 | #elif CONFIG_CPU == PNX0101 | 16 | #elif CONFIG_CPU == PNX0101 |
15 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) | 17 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) |
16 | #elif defined(CPU_ARM) | 18 | #elif defined(CPU_ARM) |
@@ -61,8 +63,8 @@ INPUT(target/sh/crt0.o) | |||
61 | #elif CONFIG_CPU==S3C2440 | 63 | #elif CONFIG_CPU==S3C2440 |
62 | #define DRAMORIG 0x00000100 + STUBOFFSET | 64 | #define DRAMORIG 0x00000100 + STUBOFFSET |
63 | #define IRAMORIG DRAMORIG | 65 | #define IRAMORIG DRAMORIG |
64 | #define IRAMSIZE 0x1000 | ||
65 | #define IRAM DRAM | 66 | #define IRAM DRAM |
67 | #define IRAMSIZE 0x1000 | ||
66 | #elif CONFIG_CPU==DM320 | 68 | #elif CONFIG_CPU==DM320 |
67 | #define DRAMORIG 0x00900000 + STUBOFFSET | 69 | #define DRAMORIG 0x00900000 + STUBOFFSET |
68 | #define IRAMORIG 0x00000000 | 70 | #define IRAMORIG 0x00000000 |
@@ -182,7 +184,94 @@ SECTIONS | |||
182 | _end = .; | 184 | _end = .; |
183 | } > DRAM | 185 | } > DRAM |
184 | 186 | ||
185 | #else /* End DM320 */ | 187 | #elif CONFIG_CPU==S3C2440 |
188 | .text : | ||
189 | { | ||
190 | loadaddress = .; | ||
191 | _loadaddress = .; | ||
192 | . = ALIGN(0x200); | ||
193 | *(.init.text) | ||
194 | *(.text*) | ||
195 | *(.glue_7) | ||
196 | *(.glue_7t) | ||
197 | . = ALIGN(0x4); | ||
198 | } > DRAM | ||
199 | |||
200 | .rodata : | ||
201 | { | ||
202 | *(.rodata) /* problems without this, dunno why */ | ||
203 | *(.rodata*) | ||
204 | *(.rodata.str1.1) | ||
205 | *(.rodata.str1.4) | ||
206 | . = ALIGN(0x4); | ||
207 | |||
208 | /* Pseudo-allocate the copies of the data sections */ | ||
209 | _datacopy = .; | ||
210 | } > DRAM | ||
211 | |||
212 | /* TRICK ALERT! For RAM execution, we put the .data section at the | ||
213 | same load address as the copy. Thus, we don't waste extra RAM | ||
214 | when we don't actually need the copy. */ | ||
215 | .data : AT ( _datacopy ) | ||
216 | { | ||
217 | _datastart = .; | ||
218 | *(.data*) | ||
219 | . = ALIGN(0x4); | ||
220 | _dataend = .; | ||
221 | } > DRAM | ||
222 | |||
223 | /DISCARD/ : | ||
224 | { | ||
225 | *(.eh_frame) | ||
226 | } | ||
227 | |||
228 | .vectors 0x0 : | ||
229 | { | ||
230 | _vectorsstart = .; | ||
231 | *(.vectors); | ||
232 | _vectorsend = .; | ||
233 | } AT> DRAM | ||
234 | |||
235 | _vectorscopy = LOADADDR(.vectors); | ||
236 | |||
237 | .iram : | ||
238 | { | ||
239 | _iramstart = .; | ||
240 | *(.icode) | ||
241 | *(.irodata) | ||
242 | *(.idata) | ||
243 | _iramend = .; | ||
244 | } > DRAM | ||
245 | |||
246 | _iramcopy = LOADADDR(.iram); | ||
247 | |||
248 | .ibss (NOLOAD) : | ||
249 | { | ||
250 | _iedata = .; | ||
251 | *(.ibss) | ||
252 | . = ALIGN(0x4); | ||
253 | _iend = .; | ||
254 | } > DRAM | ||
255 | |||
256 | .stack : | ||
257 | { | ||
258 | *(.stack) | ||
259 | stackbegin = .; | ||
260 | . += 0x2000; | ||
261 | stackend = .; | ||
262 | } > DRAM | ||
263 | |||
264 | .bss : | ||
265 | { | ||
266 | _edata = .; | ||
267 | *(.bss*) | ||
268 | *(COMMON) | ||
269 | . = ALIGN(0x4); | ||
270 | _end = .; | ||
271 | } > DRAM | ||
272 | |||
273 | #else /* End CONFIG_CPU */ | ||
274 | |||
186 | #if !defined(CPU_ARM) | 275 | #if !defined(CPU_ARM) |
187 | .vectors : | 276 | .vectors : |
188 | { | 277 | { |
@@ -241,11 +330,7 @@ SECTIONS | |||
241 | } | 330 | } |
242 | 331 | ||
243 | #if defined(CPU_ARM) | 332 | #if defined(CPU_ARM) |
244 | #if CONFIG_CPU==DM320 | ||
245 | .vectors IRAMORIG : | ||
246 | #else | ||
247 | .vectors 0x0 : | 333 | .vectors 0x0 : |
248 | #endif | ||
249 | { | 334 | { |
250 | _vectorsstart = .; | 335 | _vectorsstart = .; |
251 | *(.vectors); | 336 | *(.vectors); |
@@ -253,8 +338,6 @@ SECTIONS | |||
253 | #if CONFIG_CPU==PNX0101 | 338 | #if CONFIG_CPU==PNX0101 |
254 | *(.dmabuf) | 339 | *(.dmabuf) |
255 | } >IRAM0 AT> DRAM | 340 | } >IRAM0 AT> DRAM |
256 | #elif CONFIG_CPU==DM320 | ||
257 | } > IRAM AT> DRAM | ||
258 | #else | 341 | #else |
259 | } AT> DRAM | 342 | } AT> DRAM |
260 | #endif | 343 | #endif |
@@ -264,8 +347,6 @@ SECTIONS | |||
264 | 347 | ||
265 | #if CONFIG_CPU==PNX0101 | 348 | #if CONFIG_CPU==PNX0101 |
266 | .iram IRAMORIG + SIZEOF(.vectors) : | 349 | .iram IRAMORIG + SIZEOF(.vectors) : |
267 | #elif CONFIG_CPU==S3C2440 || CONFIG_CPU==DM320 | ||
268 | .iram : | ||
269 | #else | 350 | #else |
270 | .iram IRAMORIG : | 351 | .iram IRAMORIG : |
271 | #endif | 352 | #endif |
@@ -325,7 +406,7 @@ SECTIONS | |||
325 | 406 | ||
326 | #if defined(CPU_COLDFIRE) | 407 | #if defined(CPU_COLDFIRE) |
327 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram): | 408 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram): |
328 | #elif defined(CPU_ARM) && CONFIG_CPU != S3C2440 | 409 | #elif defined(CPU_ARM) |
329 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): | 410 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): |
330 | #else | 411 | #else |
331 | .bss : | 412 | .bss : |
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S index 1cc94ba9a2..c1bc9da059 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/crt0.S | |||
@@ -108,182 +108,7 @@ newstart: | |||
108 | #ifdef BOOTLOADER | 108 | #ifdef BOOTLOADER |
109 | /* Code for ARM bootloader targets other than iPod go here */ | 109 | /* Code for ARM bootloader targets other than iPod go here */ |
110 | 110 | ||
111 | #if CONFIG_CPU == S3C2440 | 111 | #if CONFIG_CPU == IMX31L |
112 | /* Proper initialization pulled from 0x5070 */ | ||
113 | |||
114 | /* BWSCON | ||
115 | * Reserved 0 | ||
116 | * Bank 0: | ||
117 | * Bus width 10 (16 bit) | ||
118 | * Bank 1: | ||
119 | * Buswidth 00 (8 bit) | ||
120 | * Disable wait 0 | ||
121 | * Not using UB/LB 0 | ||
122 | * Bank 2: | ||
123 | * Buswidth 10 (32 bit) | ||
124 | * Disable wait 0 | ||
125 | * Not using UB/LB 0 | ||
126 | * Bank 3: | ||
127 | * Buswidth 10 (32 bit) | ||
128 | * Disable wait 0 | ||
129 | * Use UB/LB 1 | ||
130 | * Bank 4: | ||
131 | * Buswidth 10 (32 bit) | ||
132 | * Disable wait 0 | ||
133 | * Use UB/LB 1 | ||
134 | * Bank 5: | ||
135 | * Buswidth 00 (8 bit) | ||
136 | * Disable wait 0 | ||
137 | * Not using UB/LB 0 | ||
138 | * Bank 6: | ||
139 | * Buswidth 10 (32 bit) | ||
140 | * Disable wait 0 | ||
141 | * Not using UB/LB 0 | ||
142 | * Bank 7: | ||
143 | * Buswidth 00 (8 bit) | ||
144 | * Disable wait 0 | ||
145 | * Not using UB/LB 0 | ||
146 | */ | ||
147 | ldr r2,=0x01055102 | ||
148 | mov r1, #0x48000000 | ||
149 | str r2, [r1] | ||
150 | |||
151 | /* BANKCON0 | ||
152 | * Pagemode: normal (1 data) 00 | ||
153 | * Pagemode access cycle: 2 clocks 00 | ||
154 | * Address hold: 2 clocks 10 | ||
155 | * Chip selection hold time: 1 clock 10 | ||
156 | * Access cycle: 8 clocks 101 | ||
157 | * Chip select setup time: 1 clock 01 | ||
158 | * Address setup time: 0 clock 00 | ||
159 | */ | ||
160 | ldr r2,=0x00000D60 | ||
161 | str r2, [r1, #4] | ||
162 | |||
163 | |||
164 | /* BANKCON1 | ||
165 | * Pagemode: normal (1 data) 00 | ||
166 | * Pagemode access cycle: 2 clocks 00 | ||
167 | * Address hold: 0 clocks 00 | ||
168 | * Chip selection hold time: 0 clock 00 | ||
169 | * Access cycle: 1 clocks 000 | ||
170 | * Chip select setup time: 0 clocks 00 | ||
171 | * Address setup time: 0 clocks 00 | ||
172 | */ | ||
173 | ldr r2,=0x00000000 | ||
174 | str r2, [r1, #8] | ||
175 | |||
176 | /* BANKCON2 | ||
177 | * Pagemode: normal (1 data) 00 | ||
178 | * Pagemode access cycle: 2 clocks 00 | ||
179 | * Address hold: 2 clocks 10 | ||
180 | * Chip selection hold time: 2 clocks 10 | ||
181 | * Access cycle: 14 clocks 111 | ||
182 | * Chip select setup time: 4 clocks 11 | ||
183 | * Address setup time: 0 clocks 00 | ||
184 | */ | ||
185 | ldr r2,=0x00001FA0 | ||
186 | str r2, [r1, #0xC] | ||
187 | |||
188 | /* BANKCON3 */ | ||
189 | ldr r2,=0x00001D80 | ||
190 | str r2, [r1, #0x10] | ||
191 | /* BANKCON4 */ | ||
192 | str r2, [r1, #0x14] | ||
193 | |||
194 | /* BANKCON5 */ | ||
195 | ldr r2,=0x00000000 | ||
196 | str r2, [r1, #0x18] | ||
197 | |||
198 | /* BANKCON6/7 | ||
199 | * SCAN: 9 bit 01 | ||
200 | * Trcd: 3 clocks 01 | ||
201 | * Tcah: 0 clock 00 | ||
202 | * Tcoh: 0 clock 00 | ||
203 | * Tacc: 1 clock 000 | ||
204 | * Tcos: 0 clock 00 | ||
205 | * Tacs: 0 clock 00 | ||
206 | * MT: Sync DRAM 11 | ||
207 | */ | ||
208 | ldr r2,=0x00018005 | ||
209 | str r2, [r1, #0x1C] | ||
210 | /* BANKCON7 */ | ||
211 | str r2, [r1, #0x20] | ||
212 | |||
213 | /* REFRESH */ | ||
214 | ldr r2,=0x00980501 | ||
215 | str r2, [r1, #0x24] | ||
216 | |||
217 | /* BANKSIZE | ||
218 | * BK76MAP: 32M/32M 000 | ||
219 | * Reserved: 0 0 (was 1) | ||
220 | * SCLK_EN: always 1 (was 0) | ||
221 | * SCKE_EN: disable 0 | ||
222 | * Reserved: 0 0 | ||
223 | * BURST_EN: enabled 1 | ||
224 | */ | ||
225 | ldr r2,=0x00000090 | ||
226 | str r2, [r1, #0x28] | ||
227 | |||
228 | /* MRSRB6 */ | ||
229 | ldr r2,=0x00000030 | ||
230 | str r2, [r1, #0x2C] | ||
231 | /* MRSRB7 */ | ||
232 | str r2, [r1, #0x30] | ||
233 | |||
234 | #if 0 | ||
235 | /* This next part I am not sure of the purpose */ | ||
236 | |||
237 | /* GPACON */ | ||
238 | mov r2,#0x01FFFCFF | ||
239 | str r2,=0x56000000 | ||
240 | |||
241 | /* GPADAT */ | ||
242 | mov r2,#0x01FFFEFF | ||
243 | str r2,=0x56000004 | ||
244 | |||
245 | /* MRSRB6 */ | ||
246 | mov r2,#0x00000000 | ||
247 | str r2,=0x4800002C | ||
248 | |||
249 | /* GPADAT */ | ||
250 | ldr r2,=0x01FFFFFF | ||
251 | mov r1, #0x56000000 | ||
252 | str r2, [r1, #4] | ||
253 | |||
254 | /* MRSRB6 */ | ||
255 | mov r2,#0x00000030 | ||
256 | str r2,=0x4800002C | ||
257 | |||
258 | /* GPACON */ | ||
259 | mov r2,#0x01FFFFFF | ||
260 | str r2,=0x56000000 | ||
261 | |||
262 | /* End of the unknown */ | ||
263 | #endif | ||
264 | |||
265 | /* get the high part of our execute address */ | ||
266 | ldr r2, =0xffffff00 | ||
267 | and r4, pc, r2 | ||
268 | |||
269 | /* Copy bootloader to safe area - 0x31000000 */ | ||
270 | mov r5, #0x30000000 | ||
271 | add r5, r5, #0x1000000 | ||
272 | ldr r6, = _dataend | ||
273 | sub r0, r6, r5 /* length of loader */ | ||
274 | add r0, r4, r0 /* r0 points to start of loader */ | ||
275 | 1: | ||
276 | cmp r5, r6 | ||
277 | ldrcc r2, [r4], #4 | ||
278 | strcc r2, [r5], #4 | ||
279 | bcc 1b | ||
280 | |||
281 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
282 | |||
283 | start_loc: | ||
284 | bl main | ||
285 | |||
286 | #elif CONFIG_CPU == IMX31L | ||
287 | 112 | ||
288 | mov r0, #0 | 113 | mov r0, #0 |
289 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | 114 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S new file mode 100644 index 0000000000..2c94fc4510 --- /dev/null +++ b/firmware/target/arm/s3c2440/crt0.S | |||
@@ -0,0 +1,355 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",%progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | ||
28 | * | ||
29 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
30 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
31 | * | ||
32 | */ | ||
33 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
34 | |||
35 | #if !defined(BOOTLOADER) | ||
36 | /* Copy exception handler code to address 0 */ | ||
37 | ldr r2, =_vectorsstart | ||
38 | ldr r3, =_vectorsend | ||
39 | ldr r4, =_vectorscopy | ||
40 | 1: | ||
41 | cmp r3, r2 | ||
42 | ldrhi r5, [r4], #4 | ||
43 | strhi r5, [r2], #4 | ||
44 | bhi 1b | ||
45 | #endif | ||
46 | |||
47 | #if !defined(BOOTLOADER) && !defined(STUB) | ||
48 | /* Zero out IBSS */ | ||
49 | ldr r2, =_iedata | ||
50 | ldr r3, =_iend | ||
51 | mov r4, #0 | ||
52 | 1: | ||
53 | cmp r3, r2 | ||
54 | strhi r4, [r2], #4 | ||
55 | bhi 1b | ||
56 | |||
57 | /* Copy the IRAM */ | ||
58 | ldr r2, =_iramcopy | ||
59 | ldr r3, =_iramstart | ||
60 | ldr r4, =_iramend | ||
61 | 1: | ||
62 | cmp r4, r3 | ||
63 | ldrhi r5, [r2], #4 | ||
64 | strhi r5, [r3], #4 | ||
65 | bhi 1b | ||
66 | #endif /* !BOOTLOADER, !STUB */ | ||
67 | |||
68 | /* Initialise bss section to zero */ | ||
69 | ldr r2, =_edata | ||
70 | ldr r3, =_end | ||
71 | mov r4, #0 | ||
72 | 1: | ||
73 | cmp r3, r2 | ||
74 | strhi r4, [r2], #4 | ||
75 | bhi 1b | ||
76 | |||
77 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
78 | ldr sp, =stackend | ||
79 | mov r3, sp | ||
80 | ldr r2, =stackbegin | ||
81 | ldr r4, =0xdeadbeef | ||
82 | 1: | ||
83 | cmp r3, r2 | ||
84 | strhi r4, [r2], #4 | ||
85 | bhi 1b | ||
86 | |||
87 | #ifdef BOOTLOADER | ||
88 | /* Code for ARM bootloader targets other than iPod go here */ | ||
89 | |||
90 | /* Proper initialization pulled from 0x5070 */ | ||
91 | |||
92 | /* BWSCON | ||
93 | * Reserved 0 | ||
94 | * Bank 0: | ||
95 | * Bus width 01 (16 bit) | ||
96 | * Bank 1: | ||
97 | * Buswidth 00 (8 bit) | ||
98 | * Disable wait 0 | ||
99 | * Not using UB/LB 0 | ||
100 | * Bank 2: | ||
101 | * Buswidth 10 (32 bit) | ||
102 | * Disable wait 0 | ||
103 | * Not using UB/LB 0 | ||
104 | * Bank 3: | ||
105 | * Buswidth 10 (32 bit) | ||
106 | * Disable wait 0 | ||
107 | * Use UB/LB 1 | ||
108 | * Bank 4: | ||
109 | * Buswidth 10 (32 bit) | ||
110 | * Disable wait 0 | ||
111 | * Use UB/LB 1 | ||
112 | * Bank 5: | ||
113 | * Buswidth 00 (8 bit) | ||
114 | * Disable wait 0 | ||
115 | * Not using UB/LB 0 | ||
116 | * Bank 6: | ||
117 | * Buswidth 10 (32 bit) | ||
118 | * Disable wait 0 | ||
119 | * Not using UB/LB 0 | ||
120 | * Bank 7: | ||
121 | * Buswidth 00 (8 bit) | ||
122 | * Disable wait 0 | ||
123 | * Not using UB/LB 0 | ||
124 | */ | ||
125 | ldr r2,=0x01055102 | ||
126 | mov r1, #0x48000000 | ||
127 | str r2, [r1] | ||
128 | |||
129 | /* BANKCON0 | ||
130 | * Pagemode: normal (1 data) 00 | ||
131 | * Pagemode access cycle: 2 clocks 00 | ||
132 | * Address hold: 2 clocks 10 | ||
133 | * Chip selection hold time: 1 clock 10 | ||
134 | * Access cycle: 8 clocks 101 | ||
135 | * Chip select setup time: 1 clock 01 | ||
136 | * Address setup time: 0 clock 00 | ||
137 | */ | ||
138 | ldr r2,=0x00000D60 | ||
139 | str r2, [r1, #4] | ||
140 | |||
141 | |||
142 | /* BANKCON1 | ||
143 | * Pagemode: normal (1 data) 00 | ||
144 | * Pagemode access cycle: 2 clocks 00 | ||
145 | * Address hold: 0 clocks 00 | ||
146 | * Chip selection hold time: 0 clock 00 | ||
147 | * Access cycle: 1 clocks 000 | ||
148 | * Chip select setup time: 0 clocks 00 | ||
149 | * Address setup time: 0 clocks 00 | ||
150 | */ | ||
151 | ldr r2,=0x00000000 | ||
152 | str r2, [r1, #8] | ||
153 | |||
154 | /* BANKCON2 | ||
155 | * Pagemode: normal (1 data) 00 | ||
156 | * Pagemode access cycle: 2 clocks 00 | ||
157 | * Address hold: 2 clocks 10 | ||
158 | * Chip selection hold time: 2 clocks 10 | ||
159 | * Access cycle: 14 clocks 111 | ||
160 | * Chip select setup time: 4 clocks 11 | ||
161 | * Address setup time: 0 clocks 00 | ||
162 | */ | ||
163 | ldr r2,=0x00001FA0 | ||
164 | str r2, [r1, #0xC] | ||
165 | |||
166 | /* BANKCON3 */ | ||
167 | ldr r2,=0x00001D80 | ||
168 | str r2, [r1, #0x10] | ||
169 | /* BANKCON4 */ | ||
170 | str r2, [r1, #0x14] | ||
171 | |||
172 | /* BANKCON5 */ | ||
173 | ldr r2,=0x00000000 | ||
174 | str r2, [r1, #0x18] | ||
175 | |||
176 | /* BANKCON6/7 | ||
177 | * SCAN: 9 bit 01 | ||
178 | * Trcd: 3 clocks 01 | ||
179 | * Tcah: 0 clock 00 | ||
180 | * Tcoh: 0 clock 00 | ||
181 | * Tacc: 1 clock 000 | ||
182 | * Tcos: 0 clock 00 | ||
183 | * Tacs: 0 clock 00 | ||
184 | * MT: Sync DRAM 11 | ||
185 | */ | ||
186 | ldr r2,=0x00018005 | ||
187 | str r2, [r1, #0x1C] | ||
188 | /* BANKCON7 */ | ||
189 | str r2, [r1, #0x20] | ||
190 | |||
191 | /* REFRESH */ | ||
192 | ldr r2,=0x00980501 | ||
193 | str r2, [r1, #0x24] | ||
194 | |||
195 | /* BANKSIZE | ||
196 | * BK76MAP: 32M/32M 000 | ||
197 | * Reserved: 0 0 (was 1) | ||
198 | * SCLK_EN: always 1 (was 0) | ||
199 | * SCKE_EN: disable 0 | ||
200 | * Reserved: 0 0 | ||
201 | * BURST_EN: enabled 1 | ||
202 | */ | ||
203 | ldr r2,=0x00000090 | ||
204 | str r2, [r1, #0x28] | ||
205 | |||
206 | /* MRSRB6 */ | ||
207 | ldr r2,=0x00000030 | ||
208 | str r2, [r1, #0x2C] | ||
209 | /* MRSRB7 */ | ||
210 | str r2, [r1, #0x30] | ||
211 | |||
212 | #if 0 | ||
213 | /* This next part I am not sure of the purpose */ | ||
214 | |||
215 | /* GPACON */ | ||
216 | mov r2,#0x01FFFCFF | ||
217 | str r2,=0x56000000 | ||
218 | |||
219 | /* GPADAT */ | ||
220 | mov r2,#0x01FFFEFF | ||
221 | str r2,=0x56000004 | ||
222 | |||
223 | /* MRSRB6 */ | ||
224 | mov r2,#0x00000000 | ||
225 | str r2,=0x4800002C | ||
226 | |||
227 | /* GPADAT */ | ||
228 | ldr r2,=0x01FFFFFF | ||
229 | mov r1, #0x56000000 | ||
230 | str r2, [r1, #4] | ||
231 | |||
232 | /* MRSRB6 */ | ||
233 | mov r2,#0x00000030 | ||
234 | str r2,=0x4800002C | ||
235 | |||
236 | /* GPACON */ | ||
237 | mov r2,#0x01FFFFFF | ||
238 | str r2,=0x56000000 | ||
239 | |||
240 | /* End of the unknown */ | ||
241 | #endif | ||
242 | |||
243 | /* get the high part of our execute address */ | ||
244 | ldr r2, =0xffffff00 | ||
245 | and r4, pc, r2 | ||
246 | |||
247 | /* Copy bootloader to safe area - 0x31000000 */ | ||
248 | mov r5, #0x30000000 | ||
249 | add r5, r5, #0x1000000 | ||
250 | ldr r6, = _dataend | ||
251 | sub r0, r6, r5 /* length of loader */ | ||
252 | add r0, r4, r0 /* r0 points to start of loader */ | ||
253 | 1: | ||
254 | cmp r5, r6 | ||
255 | ldrcc r2, [r4], #4 | ||
256 | strcc r2, [r5], #4 | ||
257 | bcc 1b | ||
258 | |||
259 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
260 | |||
261 | start_loc: | ||
262 | bl main | ||
263 | |||
264 | #else /* BOOTLOADER */ | ||
265 | |||
266 | /* Set up stack for IRQ mode */ | ||
267 | msr cpsr_c, #0xd2 | ||
268 | ldr sp, =irq_stack | ||
269 | /* Set up stack for FIQ mode */ | ||
270 | msr cpsr_c, #0xd1 | ||
271 | ldr sp, =fiq_stack | ||
272 | |||
273 | /* Let abort and undefined modes use IRQ stack */ | ||
274 | msr cpsr_c, #0xd7 | ||
275 | ldr sp, =irq_stack | ||
276 | msr cpsr_c, #0xdb | ||
277 | ldr sp, =irq_stack | ||
278 | /* Switch to supervisor mode */ | ||
279 | msr cpsr_c, #0xd3 | ||
280 | ldr sp, =stackend | ||
281 | bl main | ||
282 | /* main() should never return */ | ||
283 | |||
284 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | ||
285 | .section .vectors,"aw" | ||
286 | ldr pc, [pc, #24] | ||
287 | ldr pc, [pc, #24] | ||
288 | ldr pc, [pc, #24] | ||
289 | ldr pc, [pc, #24] | ||
290 | ldr pc, [pc, #24] | ||
291 | ldr pc, [pc, #24] | ||
292 | ldr pc, [pc, #24] | ||
293 | ldr pc, [pc, #24] | ||
294 | |||
295 | /* Exception vectors */ | ||
296 | .global vectors | ||
297 | vectors: | ||
298 | .word start | ||
299 | .word undef_instr_handler | ||
300 | .word software_int_handler | ||
301 | .word prefetch_abort_handler | ||
302 | .word data_abort_handler | ||
303 | .word reserved_handler | ||
304 | .word irq_handler | ||
305 | .word fiq_handler | ||
306 | |||
307 | .text | ||
308 | |||
309 | #ifndef STUB | ||
310 | .global irq | ||
311 | .global fiq | ||
312 | .global UIE | ||
313 | #endif | ||
314 | |||
315 | /* All illegal exceptions call into UIE with exception address as first | ||
316 | parameter. This is calculated differently depending on which exception | ||
317 | we're in. Second parameter is exception number, used for a string lookup | ||
318 | in UIE. | ||
319 | */ | ||
320 | undef_instr_handler: | ||
321 | mov r0, lr | ||
322 | mov r1, #0 | ||
323 | b UIE | ||
324 | |||
325 | /* We run supervisor mode most of the time, and should never see a software | ||
326 | exception being thrown. Perhaps make it illegal and call UIE? | ||
327 | */ | ||
328 | software_int_handler: | ||
329 | reserved_handler: | ||
330 | movs pc, lr | ||
331 | |||
332 | prefetch_abort_handler: | ||
333 | sub r0, lr, #4 | ||
334 | mov r1, #1 | ||
335 | b UIE | ||
336 | |||
337 | data_abort_handler: | ||
338 | sub r0, lr, #8 | ||
339 | mov r1, #2 | ||
340 | b UIE | ||
341 | |||
342 | #ifdef STUB | ||
343 | UIE: | ||
344 | b UIE | ||
345 | #endif | ||
346 | |||
347 | /* 256 words of IRQ stack */ | ||
348 | .space 256*4 | ||
349 | irq_stack: | ||
350 | |||
351 | /* 256 words of FIQ stack */ | ||
352 | .space 256*4 | ||
353 | fiq_stack: | ||
354 | |||
355 | #endif /* BOOTLOADER */ | ||
diff --git a/firmware/target/arm/s3c2440/debug-s3c2440.c b/firmware/target/arm/s3c2440/debug-s3c2440.c index 23aa75ea38..5089d96f03 100755 --- a/firmware/target/arm/s3c2440/debug-s3c2440.c +++ b/firmware/target/arm/s3c2440/debug-s3c2440.c | |||
@@ -77,6 +77,7 @@ bool __dbg_ports(void) | |||
77 | snprintf(buf, sizeof(buf), "CLKCON: %08x CLKSLOW: %08x", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); | 77 | snprintf(buf, sizeof(buf), "CLKCON: %08x CLKSLOW: %08x", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); |
78 | snprintf(buf, sizeof(buf), "MPLLCON: %08x UPLLCON: %08x", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); | 78 | snprintf(buf, sizeof(buf), "MPLLCON: %08x UPLLCON: %08x", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); |
79 | snprintf(buf, sizeof(buf), "CLKDIVN: %08x", CLKDIVN); lcd_puts(0, line++, buf); | 79 | snprintf(buf, sizeof(buf), "CLKDIVN: %08x", CLKDIVN); lcd_puts(0, line++, buf); |
80 | snprintf(buf, sizeof(buf), "BWSCON: %08x ", BWSCON); lcd_puts(0, line++, buf); | ||
80 | 81 | ||
81 | lcd_update(); | 82 | lcd_update(); |
82 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) | 83 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) |