1 files changed, 1 insertions, 176 deletions
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S
index 1cc94ba9a2..c1bc9da059 100644
--- a/firmware/target/arm/crt0.S
+++ b/firmware/target/arm/crt0.S
@@ -108,182 +108,7 @@ newstart:
 #ifdef BOOTLOADER
 /* Code for ARM bootloader targets other than iPod go here */
-#if CONFIG_CPU == S3C2440
+#if CONFIG_CPU == IMX31L
-    /* Proper initialization pulled from 0x5070 */
-    /* BWSCON
-     *      Reserved 0
-     * Bank 0:
-     *      Bus width 10 (16 bit)
-     * Bank 1:
-     *      Buswidth 00 (8 bit)
-     *      Disable wait 0
-     *      Not using UB/LB 0
-     * Bank 2:
-     *      Buswidth 10 (32 bit)
-     *      Disable wait 0
-     *      Not using UB/LB 0
-     * Bank 3:
-     *      Buswidth 10 (32 bit)
-     *      Disable wait 0
-     *      Use UB/LB 1
-     * Bank 4:
-     *      Buswidth 10 (32 bit)
-     *      Disable wait 0
-     *      Use UB/LB 1
-     * Bank 5: 
-     *      Buswidth 00 (8 bit)
-     *      Disable wait 0
-     *      Not using UB/LB 0
-     * Bank 6:
-     *      Buswidth 10 (32 bit)
-     *      Disable wait 0
-     *      Not using UB/LB 0
-     * Bank 7:
-     *      Buswidth 00 (8 bit)
-     *      Disable wait 0
-     *      Not using UB/LB 0
-     */
-    ldr     r2,=0x01055102
-    mov     r1, #0x48000000
-    str     r2, [r1]
-    /* BANKCON0 
-     *      Pagemode: normal (1 data) 00
-     *      Pagemode access cycle: 2 clocks 00
-     *      Address hold: 2 clocks 10
-     *      Chip selection hold time: 1 clock 10
-     *      Access cycle: 8 clocks 101
-     *      Chip select setup time: 1 clock 01
-     *      Address setup time: 0 clock 00
-     */
-    ldr     r2,=0x00000D60
-    str     r2, [r1, #4]
-    /* BANKCON1 
-     *      Pagemode: normal (1 data) 00
-     *      Pagemode access cycle: 2 clocks 00
-     *      Address hold: 0 clocks 00
-     *      Chip selection hold time: 0 clock 00
-     *      Access cycle: 1 clocks 000
-     *      Chip select setup time: 0 clocks 00
-     *      Address setup time: 0 clocks 00
-     */
-    ldr     r2,=0x00000000
-    str     r2, [r1, #8]
-    /* BANKCON2 
-     *      Pagemode: normal (1 data) 00
-     *      Pagemode access cycle: 2 clocks 00
-     *      Address hold: 2 clocks 10
-     *      Chip selection hold time: 2 clocks 10
-     *      Access cycle: 14 clocks 111
-     *      Chip select setup time: 4 clocks 11
-     *      Address setup time: 0 clocks 00
-     */
-    ldr     r2,=0x00001FA0
-    str     r2, [r1, #0xC]
-    /* BANKCON3 */
-    ldr     r2,=0x00001D80
-    str     r2, [r1, #0x10]
-    /* BANKCON4 */
-    str     r2, [r1, #0x14]
-    /* BANKCON5 */
-    ldr     r2,=0x00000000
-    str     r2, [r1, #0x18]
-    /* BANKCON6/7
-     *      SCAN:   9 bit       01
-     *      Trcd:   3 clocks    01
-     *      Tcah:   0 clock     00
-     *      Tcoh:   0 clock     00
-     *      Tacc:   1 clock     000
-     *      Tcos:   0 clock     00
-     *      Tacs:   0 clock     00
-     *      MT:     Sync DRAM   11
-     */
-    ldr     r2,=0x00018005
-    str     r2, [r1, #0x1C]
-    /* BANKCON7 */
-    str     r2, [r1, #0x20]
-    /* REFRESH */
-    ldr     r2,=0x00980501
-    str     r2, [r1, #0x24]
-    /* BANKSIZE
-     *      BK76MAP: 32M/32M    000
-     *      Reserved: 0         0 (was 1)
-     *      SCLK_EN: always     1 (was 0)
-     *      SCKE_EN: disable    0
-     *      Reserved: 0         0
-     *      BURST_EN: enabled   1
-     */
-    ldr     r2,=0x00000090
-    str     r2, [r1, #0x28]
-    /* MRSRB6 */
-    ldr     r2,=0x00000030
-    str     r2, [r1, #0x2C]
-    /* MRSRB7 */
-    str     r2, [r1, #0x30]
-    
-#if 0
-    /* This next part I am not sure of the purpose */
-    
-    /* GPACON */
-    mov    r2,#0x01FFFCFF
-    str    r2,=0x56000000
-    
-    /* GPADAT */
-    mov    r2,#0x01FFFEFF
-    str    r2,=0x56000004
-    /* MRSRB6 */
-    mov    r2,#0x00000000
-    str    r2,=0x4800002C
-    /* GPADAT */
-    ldr     r2,=0x01FFFFFF
-    mov     r1, #0x56000000 
-    str     r2, [r1, #4]
-    /* MRSRB6 */
-    mov    r2,#0x00000030
-    str    r2,=0x4800002C
-    /* GPACON */
-    mov    r2,#0x01FFFFFF
-    str    r2,=0x56000000
-    /* End of the unknown */
-#endif
-    /* get the high part of our execute address */
-    ldr    r2, =0xffffff00
-    and    r4, pc, r2
-    /* Copy bootloader to safe area - 0x31000000 */
-    mov    r5, #0x30000000
-    add    r5, r5, #0x1000000
-    ldr    r6, = _dataend
-    sub    r0, r6, r5       /* length of loader */
-    add    r0, r4, r0     /* r0 points to start of loader */
-1:
-    cmp    r5, r6
-    ldrcc  r2, [r4], #4
-    strcc  r2, [r5], #4
-    bcc    1b
-    ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
-    
-start_loc:
-     bl main
-     
-#elif CONFIG_CPU == IMX31L
          
    mov r0, #0
    mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */

diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S index 1cc94ba9a2..c1bc9da059 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/crt0.S
@@ -108,182 +108,7 @@ newstart:
108	#ifdef BOOTLOADER	108	#ifdef BOOTLOADER
109	/* Code for ARM bootloader targets other than iPod go here */	109	/* Code for ARM bootloader targets other than iPod go here */
110		110
111	#if CONFIG_CPU == S3C2440	111	#if CONFIG_CPU == IMX31L
112	/* Proper initialization pulled from 0x5070 */
113
114	/* BWSCON
115	* Reserved 0
116	* Bank 0:
117	* Bus width 10 (16 bit)
118	* Bank 1:
119	* Buswidth 00 (8 bit)
120	* Disable wait 0
121	* Not using UB/LB 0
122	* Bank 2:
123	* Buswidth 10 (32 bit)
124	* Disable wait 0
125	* Not using UB/LB 0
126	* Bank 3:
127	* Buswidth 10 (32 bit)
128	* Disable wait 0
129	* Use UB/LB 1
130	* Bank 4:
131	* Buswidth 10 (32 bit)
132	* Disable wait 0
133	* Use UB/LB 1
134	* Bank 5:
135	* Buswidth 00 (8 bit)
136	* Disable wait 0
137	* Not using UB/LB 0
138	* Bank 6:
139	* Buswidth 10 (32 bit)
140	* Disable wait 0
141	* Not using UB/LB 0
142	* Bank 7:
143	* Buswidth 00 (8 bit)
144	* Disable wait 0
145	* Not using UB/LB 0
146	*/
147	ldr r2,=0x01055102
148	mov r1, #0x48000000
149	str r2, [r1]
150
151	/* BANKCON0
152	* Pagemode: normal (1 data) 00
153	* Pagemode access cycle: 2 clocks 00
154	* Address hold: 2 clocks 10
155	* Chip selection hold time: 1 clock 10
156	* Access cycle: 8 clocks 101
157	* Chip select setup time: 1 clock 01
158	* Address setup time: 0 clock 00
159	*/
160	ldr r2,=0x00000D60
161	str r2, [r1, #4]
162
163
164	/* BANKCON1
165	* Pagemode: normal (1 data) 00
166	* Pagemode access cycle: 2 clocks 00
167	* Address hold: 0 clocks 00
168	* Chip selection hold time: 0 clock 00
169	* Access cycle: 1 clocks 000
170	* Chip select setup time: 0 clocks 00
171	* Address setup time: 0 clocks 00
172	*/
173	ldr r2,=0x00000000
174	str r2, [r1, #8]
175
176	/* BANKCON2
177	* Pagemode: normal (1 data) 00
178	* Pagemode access cycle: 2 clocks 00
179	* Address hold: 2 clocks 10
180	* Chip selection hold time: 2 clocks 10
181	* Access cycle: 14 clocks 111
182	* Chip select setup time: 4 clocks 11
183	* Address setup time: 0 clocks 00
184	*/
185	ldr r2,=0x00001FA0
186	str r2, [r1, #0xC]
187
188	/* BANKCON3 */
189	ldr r2,=0x00001D80
190	str r2, [r1, #0x10]
191	/* BANKCON4 */
192	str r2, [r1, #0x14]
193
194	/* BANKCON5 */
195	ldr r2,=0x00000000
196	str r2, [r1, #0x18]
197
198	/* BANKCON6/7
199	* SCAN: 9 bit 01
200	* Trcd: 3 clocks 01
201	* Tcah: 0 clock 00
202	* Tcoh: 0 clock 00
203	* Tacc: 1 clock 000
204	* Tcos: 0 clock 00
205	* Tacs: 0 clock 00
206	* MT: Sync DRAM 11
207	*/
208	ldr r2,=0x00018005
209	str r2, [r1, #0x1C]
210	/* BANKCON7 */
211	str r2, [r1, #0x20]
212
213	/* REFRESH */
214	ldr r2,=0x00980501
215	str r2, [r1, #0x24]
216
217	/* BANKSIZE
218	* BK76MAP: 32M/32M 000
219	* Reserved: 0 0 (was 1)
220	* SCLK_EN: always 1 (was 0)
221	* SCKE_EN: disable 0
222	* Reserved: 0 0
223	* BURST_EN: enabled 1
224	*/
225	ldr r2,=0x00000090
226	str r2, [r1, #0x28]
227
228	/* MRSRB6 */
229	ldr r2,=0x00000030
230	str r2, [r1, #0x2C]
231	/* MRSRB7 */
232	str r2, [r1, #0x30]
233
234	#if 0
235	/* This next part I am not sure of the purpose */
236
237	/* GPACON */
238	mov r2,#0x01FFFCFF
239	str r2,=0x56000000
240
241	/* GPADAT */
242	mov r2,#0x01FFFEFF
243	str r2,=0x56000004
244
245	/* MRSRB6 */
246	mov r2,#0x00000000
247	str r2,=0x4800002C
248
249	/* GPADAT */
250	ldr r2,=0x01FFFFFF
251	mov r1, #0x56000000
252	str r2, [r1, #4]
253
254	/* MRSRB6 */
255	mov r2,#0x00000030
256	str r2,=0x4800002C
257
258	/* GPACON */
259	mov r2,#0x01FFFFFF
260	str r2,=0x56000000
261
262	/* End of the unknown */
263	#endif
264
265	/* get the high part of our execute address */
266	ldr r2, =0xffffff00
267	and r4, pc, r2
268
269	/* Copy bootloader to safe area - 0x31000000 */
270	mov r5, #0x30000000
271	add r5, r5, #0x1000000
272	ldr r6, = _dataend
273	sub r0, r6, r5 /* length of loader */
274	add r0, r4, r0 /* r0 points to start of loader */
275	1:
276	cmp r5, r6
277	ldrcc r2, [r4], #4
278	strcc r2, [r5], #4
279	bcc 1b
280
281	ldr pc, =start_loc /* jump to the relocated start_loc: */
282
283	start_loc:
284	bl main
285
286	#elif CONFIG_CPU == IMX31L
287		112
288	mov r0, #0	113	mov r0, #0
289	mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */	114	mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */