diff options
Diffstat (limited to 'firmware')
23 files changed, 10690 insertions, 0 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 3617f978ef..89f5a26c78 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -325,9 +325,11 @@ target/arm/i2c-telechips.c | |||
325 | #elif CONFIG_I2C == I2C_S3C2440 | 325 | #elif CONFIG_I2C == I2C_S3C2440 |
326 | /* no i2c driver yet */ | 326 | /* no i2c driver yet */ |
327 | #endif | 327 | #endif |
328 | |||
328 | #if CONFIG_CPU == PNX0101 | 329 | #if CONFIG_CPU == PNX0101 |
329 | target/arm/pnx0101/system-pnx0101.c | 330 | target/arm/pnx0101/system-pnx0101.c |
330 | #endif | 331 | #endif |
332 | |||
331 | #if defined(CPU_PP) | 333 | #if defined(CPU_PP) |
332 | #if CONFIG_CPU == PP5002 | 334 | #if CONFIG_CPU == PP5002 |
333 | target/arm/system-pp5002.c | 335 | target/arm/system-pp5002.c |
@@ -362,6 +364,21 @@ target/arm/crt0.S | |||
362 | #endif /* defined(CPU_*) */ | 364 | #endif /* defined(CPU_*) */ |
363 | #endif /* SIMULATOR */ | 365 | #endif /* SIMULATOR */ |
364 | 366 | ||
367 | #elif defined(CPU_MIPS) | ||
368 | #undef mips | ||
369 | /*target/mips/memcpy.S | ||
370 | target/mips/memset.S | ||
371 | common/memset16.c | ||
372 | target/mips/strlen.S*/ | ||
373 | common/memcpy.c | ||
374 | common/memmove.c | ||
375 | common/memset.c | ||
376 | common/memset16.c | ||
377 | common/strlen.c | ||
378 | #if CONFIG_CPU==JZ4732 | ||
379 | target/mips/ingenic_jz47xx/crt0.S | ||
380 | #endif /* CONFIG_CPU == JZ4732 */ | ||
381 | |||
365 | #else | 382 | #else |
366 | 383 | ||
367 | #ifdef HAVE_PRIORITY_SCHEDULING | 384 | #ifdef HAVE_PRIORITY_SCHEDULING |
@@ -1054,3 +1071,15 @@ target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c | |||
1054 | #endif /* BOOTLOADER */ | 1071 | #endif /* BOOTLOADER */ |
1055 | #endif /* SIMULATOR */ | 1072 | #endif /* SIMULATOR */ |
1056 | #endif /* MEIZU_M6SL */ | 1073 | #endif /* MEIZU_M6SL */ |
1074 | |||
1075 | #if CONFIG_CPU==JZ4732 | ||
1076 | target/mips/ingenic_jz47xx/ata-jz4740.c | ||
1077 | target/mips/ingenic_jz47xx/lcd-jz4740.c | ||
1078 | target/mips/ingenic_jz47xx/system-jz4740.c | ||
1079 | #endif | ||
1080 | |||
1081 | #ifdef ONDA_VX747 | ||
1082 | target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c | ||
1083 | target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c | ||
1084 | target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | ||
1085 | #endif | ||
diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h new file mode 100755 index 0000000000..b5519b21ee --- /dev/null +++ b/firmware/export/config-ondavx747.h | |||
@@ -0,0 +1,170 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* | ||
23 | * This config file is for the Onda VX747 | ||
24 | */ | ||
25 | #define TARGET_TREE /* this target is using the target tree system */ | ||
26 | |||
27 | #define CONFIG_SDRAM_START 0x80E00000 /* HACK! */ | ||
28 | |||
29 | #define ONDA_VX747 1 | ||
30 | |||
31 | /* For Rolo and boot loader */ | ||
32 | #define MODEL_NUMBER 30 | ||
33 | |||
34 | /* define this if you use an ATA controller */ | ||
35 | //#define HAVE_ATA | ||
36 | |||
37 | /* define this if you have a bitmap LCD display */ | ||
38 | #define HAVE_LCD_BITMAP | ||
39 | |||
40 | /* define this if you have a colour LCD */ | ||
41 | #define HAVE_LCD_COLOR | ||
42 | |||
43 | /* define this if you have access to the quickscreen */ | ||
44 | #define HAVE_QUICKSCREEN | ||
45 | |||
46 | /* define this if you have access to the pitchscreen */ | ||
47 | #define HAVE_PITCHSCREEN | ||
48 | |||
49 | /* define this if you would like tagcache to build on this target */ | ||
50 | #define HAVE_TAGCACHE | ||
51 | |||
52 | /* define this if the target has volume keys which can be used in the lists */ | ||
53 | #define HAVE_VOLUME_IN_LIST | ||
54 | |||
55 | /* LCD dimensions */ | ||
56 | #define CONFIG_LCD LCD_ONDAVX747 | ||
57 | |||
58 | /* choose the lcd orientation. both work */ | ||
59 | #define CONFIG_ORIENTATION SCREEN_PORTRAIT | ||
60 | |||
61 | #define LCD_WIDTH 400 | ||
62 | #define LCD_HEIGHT 240 | ||
63 | |||
64 | #define LCD_DEPTH 16 /* 16bit colours */ | ||
65 | #define LCD_PIXELFORMAT RGB565 /* rgb565 */ | ||
66 | |||
67 | /* Define this if your LCD can be enabled/disabled */ | ||
68 | #define HAVE_LCD_ENABLE | ||
69 | |||
70 | #define CONFIG_KEYPAD ONDAVX747_PAD | ||
71 | #define HAS_BUTTON_HOLD | ||
72 | //#define HAVE_HEADPHONE_DETECTION | ||
73 | #define HAVE_TOUCHPAD | ||
74 | #define HAVE_BUTTON_DATA | ||
75 | |||
76 | /* Define this if you do software codec */ | ||
77 | #define CONFIG_CODEC SWCODEC | ||
78 | |||
79 | /* define this if you have a real-time clock */ | ||
80 | //#define CONFIG_RTC RTC_RX5X348AB | ||
81 | |||
82 | /* Define this for LCD backlight available */ | ||
83 | #define HAVE_BACKLIGHT | ||
84 | |||
85 | #define HAVE_BACKLIGHT_BRIGHTNESS | ||
86 | |||
87 | /* Main LCD backlight brightness range and defaults */ | ||
88 | #define MIN_BRIGHTNESS_SETTING 0 /* TODO */ | ||
89 | #define MAX_BRIGHTNESS_SETTING 127 | ||
90 | #define DEFAULT_BRIGHTNESS_SETTING 85 | ||
91 | #define DEFAULT_DIMNESS_SETTING 22 | ||
92 | |||
93 | /* Define this if you have a software controlled poweroff */ | ||
94 | //#define HAVE_SW_POWEROFF | ||
95 | //TODO: enable this back | ||
96 | |||
97 | /* The number of bytes reserved for loadable codecs */ | ||
98 | #define CODEC_SIZE 0x80000 | ||
99 | |||
100 | /* The number of bytes reserved for loadable plugins */ | ||
101 | #define PLUGIN_BUFFER_SIZE 0x100000 | ||
102 | |||
103 | /* Define this if you have the */ | ||
104 | //#define HAVE_TLV320 | ||
105 | |||
106 | #define CONFIG_I2C I2C_JZ47XX | ||
107 | |||
108 | /* TLV320 has no tone controls, so we use the software ones */ | ||
109 | //#define HAVE_SW_TONE_CONTROLS | ||
110 | |||
111 | /*#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \ | ||
112 | SAMPR_CAP_11)*/ | ||
113 | |||
114 | #define BATTERY_CAPACITY_DEFAULT 1250 /* default battery capacity */ | ||
115 | #define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ | ||
116 | #define BATTERY_CAPACITY_MAX 2500 /* max. capacity selectable */ | ||
117 | #define BATTERY_CAPACITY_INC 100 /* capacity increment */ | ||
118 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
119 | |||
120 | /* Hardware controlled charging with monitoring */ | ||
121 | //#define CONFIG_CHARGING CHARGING_MONITOR | ||
122 | |||
123 | #ifndef SIMULATOR | ||
124 | |||
125 | /* Define this if you have a Ingenic JZ4732 */ | ||
126 | #define CONFIG_CPU JZ4732 | ||
127 | |||
128 | /* define this if the hardware can be powered off while charging */ | ||
129 | #define HAVE_POWEROFF_WHILE_CHARGING | ||
130 | |||
131 | /* Define this to the CPU frequency */ | ||
132 | #define CPU_FREQ 16934400 | ||
133 | |||
134 | /* define this if you have a flash memory storage */ | ||
135 | #define HAVE_FLASH_STORAGE | ||
136 | |||
137 | /* Virtual LED (icon) */ | ||
138 | #define CONFIG_LED LED_VIRTUAL | ||
139 | |||
140 | /* define this if the backlight can be set to a brightness */ | ||
141 | #define __BACKLIGHT_INIT | ||
142 | |||
143 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
144 | #define FIRMWARE_OFFSET_FILE_CRC 0 | ||
145 | |||
146 | /* Offset ( in the firmware file's header ) to the real data */ | ||
147 | #define FIRMWARE_OFFSET_FILE_DATA 8 | ||
148 | |||
149 | /* Define this if you have adjustable CPU frequency */ | ||
150 | /* #define HAVE_ADJUSTABLE_CPU_FREQ */ | ||
151 | |||
152 | #define BOOTFILE_EXT "vx747" | ||
153 | #define BOOTFILE "rockbox." BOOTFILE_EXT | ||
154 | #define BOOTDIR "/.rockbox" | ||
155 | |||
156 | /*#define CONFIG_USBOTG USBOTG_INGENIC | ||
157 | #define HAVE_USBSTACK | ||
158 | #define USB_VENDOR_ID 0x041e | ||
159 | #define USB_PRODUCT_ID 0x4133*/ | ||
160 | |||
161 | /*DEBUGGING!*/ | ||
162 | #ifdef BOOTLOADER | ||
163 | #define THREAD_EXTRA_CHECKS 1 | ||
164 | #define DEBUG 1 | ||
165 | #define debug(msg) printf(msg) | ||
166 | #endif | ||
167 | |||
168 | #include <stdbool.h> /* HACKY */ | ||
169 | |||
170 | #endif | ||
diff --git a/firmware/export/config.h b/firmware/export/config.h index 265f9c8e0f..d700a15102 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -60,6 +60,7 @@ | |||
60 | #define TCC773L 773 | 60 | #define TCC773L 773 |
61 | #define TCC7801 7801 | 61 | #define TCC7801 7801 |
62 | #define S5L8700 8700 | 62 | #define S5L8700 8700 |
63 | #define JZ4732 4732 | ||
63 | 64 | ||
64 | /* CONFIG_KEYPAD */ | 65 | /* CONFIG_KEYPAD */ |
65 | #define PLAYER_PAD 1 | 66 | #define PLAYER_PAD 1 |
@@ -92,6 +93,7 @@ | |||
92 | #define SANSA_C100_PAD 28 | 93 | #define SANSA_C100_PAD 28 |
93 | #define PHILIPS_HDD1630_PAD 29 | 94 | #define PHILIPS_HDD1630_PAD 29 |
94 | #define MEIZU_M6SL_PAD 30 | 95 | #define MEIZU_M6SL_PAD 30 |
96 | #define ONDAVX747_PAD 31 | ||
95 | 97 | ||
96 | /* CONFIG_REMOTE_KEYPAD */ | 98 | /* CONFIG_REMOTE_KEYPAD */ |
97 | #define H100_REMOTE 1 | 99 | #define H100_REMOTE 1 |
@@ -134,6 +136,7 @@ | |||
134 | #define LCD_S6B33B2 26 /* as used by the Sansa c100 */ | 136 | #define LCD_S6B33B2 26 /* as used by the Sansa c100 */ |
135 | #define LCD_HDD1630 27 /* as used by the Philips HDD1630 */ | 137 | #define LCD_HDD1630 27 /* as used by the Philips HDD1630 */ |
136 | #define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */ | 138 | #define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */ |
139 | #define LCD_ONDAVX747 29 /* as used by the Onda VX747 */ | ||
137 | 140 | ||
138 | /* LCD_PIXELFORMAT */ | 141 | /* LCD_PIXELFORMAT */ |
139 | #define HORIZONTAL_PACKING 1 | 142 | #define HORIZONTAL_PACKING 1 |
@@ -162,6 +165,7 @@ | |||
162 | #define I2C_TCC780X 11 | 165 | #define I2C_TCC780X 11 |
163 | #define I2C_DM320 12 /* DM320 style */ | 166 | #define I2C_DM320 12 /* DM320 style */ |
164 | #define I2C_S5L8700 13 | 167 | #define I2C_S5L8700 13 |
168 | #define I2C_JZ47XX 14 /* Ingenic Jz47XX style */ | ||
165 | 169 | ||
166 | /* CONFIG_LED */ | 170 | /* CONFIG_LED */ |
167 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ | 171 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ |
@@ -187,12 +191,14 @@ | |||
187 | #define RTC_MC13783 13 /* Freescale MC13783 PMIC */ | 191 | #define RTC_MC13783 13 /* Freescale MC13783 PMIC */ |
188 | #define RTC_S5L8700 14 | 192 | #define RTC_S5L8700 14 |
189 | #define RTC_S35390A 15 | 193 | #define RTC_S35390A 15 |
194 | #define RTC_JZ47XX 16 /* Ingenic Jz47XX */ | ||
190 | 195 | ||
191 | /* USB On-the-go */ | 196 | /* USB On-the-go */ |
192 | #define USBOTG_ISP1362 1362 /* iriver H300 */ | 197 | #define USBOTG_ISP1362 1362 /* iriver H300 */ |
193 | #define USBOTG_ISP1583 1583 /* Creative Zen Vision:M */ | 198 | #define USBOTG_ISP1583 1583 /* Creative Zen Vision:M */ |
194 | #define USBOTG_M5636 5636 /* iAudio X5 */ | 199 | #define USBOTG_M5636 5636 /* iAudio X5 */ |
195 | #define USBOTG_ARC 5020 /* PortalPlayer 502x */ | 200 | #define USBOTG_ARC 5020 /* PortalPlayer 502x */ |
201 | #define USBOTG_JZ4740 4740 /* Ingenic Jz4740/Jz4732 */ | ||
196 | 202 | ||
197 | /* Multiple cores */ | 203 | /* Multiple cores */ |
198 | #define CPU 0 | 204 | #define CPU 0 |
@@ -283,6 +289,8 @@ | |||
283 | #include "config-c100.h" | 289 | #include "config-c100.h" |
284 | #elif defined(MEIZU_M6SL) | 290 | #elif defined(MEIZU_M6SL) |
285 | #include "config-meizu-m6sl.h" | 291 | #include "config-meizu-m6sl.h" |
292 | #elif defined(ONDA_VX747) | ||
293 | #include "config-ondavx747.h" | ||
286 | #else | 294 | #else |
287 | /* no known platform */ | 295 | /* no known platform */ |
288 | #endif | 296 | #endif |
@@ -448,6 +456,10 @@ | |||
448 | #define ROCKBOX_STRICT_ALIGN 1 | 456 | #define ROCKBOX_STRICT_ALIGN 1 |
449 | #endif | 457 | #endif |
450 | 458 | ||
459 | #if (CONFIG_CPU == JZ4732) | ||
460 | #define CPU_MIPS 32 | ||
461 | #endif | ||
462 | |||
451 | #ifndef CODEC_SIZE | 463 | #ifndef CODEC_SIZE |
452 | #define CODEC_SIZE 0 | 464 | #define CODEC_SIZE 0 |
453 | #endif | 465 | #endif |
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h new file mode 100755 index 0000000000..7ad10b76a6 --- /dev/null +++ b/firmware/export/jz4740.h | |||
@@ -0,0 +1,4902 @@ | |||
1 | /* | ||
2 | * Include file for Ingenic Semiconductor's JZ4740 CPU. | ||
3 | */ | ||
4 | #ifndef __JZ4740_H__ | ||
5 | #define __JZ4740_H__ | ||
6 | |||
7 | #ifndef __ASSEMBLY__ | ||
8 | |||
9 | #define cache_unroll(base,op) \ | ||
10 | __asm__ __volatile__(" \ | ||
11 | .set noreorder; \ | ||
12 | .set mips3; \ | ||
13 | cache %1, (%0); \ | ||
14 | .set mips0; \ | ||
15 | .set reorder" \ | ||
16 | : \ | ||
17 | : "r" (base), \ | ||
18 | "i" (op)); | ||
19 | |||
20 | #define Index_Invalidate_I 0x00 | ||
21 | #define Index_Writeback_Inv_D 0x01 | ||
22 | |||
23 | #define CFG_DCACHE_SIZE 16384 | ||
24 | #define CFG_ICACHE_SIZE 16384 | ||
25 | #define CFG_CACHELINE_SIZE 32 | ||
26 | |||
27 | #define KSEG0BASE 0x80003FFF /* HACK */ | ||
28 | |||
29 | static inline void jz_flush_dcache(void) | ||
30 | { | ||
31 | unsigned long start; | ||
32 | unsigned long end; | ||
33 | |||
34 | start = KSEG0BASE; | ||
35 | end = start + CFG_DCACHE_SIZE; | ||
36 | while (start < end) { | ||
37 | cache_unroll(start,Index_Writeback_Inv_D); | ||
38 | start += CFG_CACHELINE_SIZE; | ||
39 | } | ||
40 | } | ||
41 | |||
42 | static inline void jz_flush_icache(void) | ||
43 | { | ||
44 | unsigned long start; | ||
45 | unsigned long end; | ||
46 | |||
47 | start = KSEG0BASE; | ||
48 | end = start + CFG_ICACHE_SIZE; | ||
49 | while(start < end) { | ||
50 | cache_unroll(start,Index_Invalidate_I); | ||
51 | start += CFG_CACHELINE_SIZE; | ||
52 | } | ||
53 | } | ||
54 | |||
55 | /* cpu pipeline flush */ | ||
56 | static inline void jz_sync(void) | ||
57 | { | ||
58 | __asm__ volatile ("sync"); | ||
59 | } | ||
60 | |||
61 | #define REG8(addr) (*(volatile unsigned char *)(addr)) | ||
62 | #define REG16(addr) (*(volatile unsigned short *)(addr)) | ||
63 | #define REG32(addr) (*(volatile unsigned int *)(addr)) | ||
64 | |||
65 | #endif /* !ASSEMBLY */ | ||
66 | |||
67 | //---------------------------------------------------------------------- | ||
68 | // Boot ROM Specification | ||
69 | // | ||
70 | |||
71 | /* NOR Boot config */ | ||
72 | #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ | ||
73 | #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ | ||
74 | #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ | ||
75 | |||
76 | /* NAND Boot config */ | ||
77 | #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ | ||
78 | #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ | ||
79 | #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ | ||
80 | #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ | ||
81 | |||
82 | |||
83 | //---------------------------------------------------------------------- | ||
84 | // Register Definitions | ||
85 | // | ||
86 | #define CPM_BASE 0xB0000000 | ||
87 | #define INTC_BASE 0xB0001000 | ||
88 | #define TCU_BASE 0xB0002000 | ||
89 | #define WDT_BASE 0xB0002000 | ||
90 | #define RTC_BASE 0xB0003000 | ||
91 | #define GPIO_BASE 0xB0010000 | ||
92 | #define AIC_BASE 0xB0020000 | ||
93 | #define ICDC_BASE 0xB0020000 | ||
94 | #define MSC_BASE 0xB0021000 | ||
95 | #define UART0_BASE 0xB0030000 | ||
96 | #define I2C_BASE 0xB0042000 | ||
97 | #define SSI_BASE 0xB0043000 | ||
98 | #define SADC_BASE 0xB0070000 | ||
99 | #define EMC_BASE 0xB3010000 | ||
100 | #define DMAC_BASE 0xB3020000 | ||
101 | #define UHC_BASE 0xB3030000 | ||
102 | #define UDC_BASE 0xB3040000 | ||
103 | #define LCD_BASE 0xB3050000 | ||
104 | #define SLCD_BASE 0xB3050000 | ||
105 | #define CIM_BASE 0xB3060000 | ||
106 | #define ETH_BASE 0xB3100000 | ||
107 | |||
108 | |||
109 | /************************************************************************* | ||
110 | * INTC (Interrupt Controller) | ||
111 | *************************************************************************/ | ||
112 | #define INTC_ISR (INTC_BASE + 0x00) | ||
113 | #define INTC_IMR (INTC_BASE + 0x04) | ||
114 | #define INTC_IMSR (INTC_BASE + 0x08) | ||
115 | #define INTC_IMCR (INTC_BASE + 0x0c) | ||
116 | #define INTC_IPR (INTC_BASE + 0x10) | ||
117 | |||
118 | #define REG_INTC_ISR REG32(INTC_ISR) | ||
119 | #define REG_INTC_IMR REG32(INTC_IMR) | ||
120 | #define REG_INTC_IMSR REG32(INTC_IMSR) | ||
121 | #define REG_INTC_IMCR REG32(INTC_IMCR) | ||
122 | #define REG_INTC_IPR REG32(INTC_IPR) | ||
123 | |||
124 | // 1st-level interrupts | ||
125 | #define IRQ_I2C 1 | ||
126 | #define IRQ_EMC 2 | ||
127 | #define IRQ_UHC 3 | ||
128 | #define IRQ_UART0 9 | ||
129 | #define IRQ_SADC 12 | ||
130 | #define IRQ_MSC 14 | ||
131 | #define IRQ_RTC 15 | ||
132 | #define IRQ_SSI 16 | ||
133 | #define IRQ_CIM 17 | ||
134 | #define IRQ_AIC 18 | ||
135 | #define IRQ_ETH 19 | ||
136 | #define IRQ_DMAC 20 | ||
137 | #define IRQ_TCU2 21 | ||
138 | #define IRQ_TCU1 22 | ||
139 | #define IRQ_TCU0 23 | ||
140 | #define IRQ_UDC 24 | ||
141 | #define IRQ_GPIO3 25 | ||
142 | #define IRQ_GPIO2 26 | ||
143 | #define IRQ_GPIO1 27 | ||
144 | #define IRQ_GPIO0 28 | ||
145 | #define IRQ_IPU 29 | ||
146 | #define IRQ_LCD 30 | ||
147 | |||
148 | // 2nd-level interrupts | ||
149 | #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ | ||
150 | #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ | ||
151 | |||
152 | |||
153 | /************************************************************************* | ||
154 | * RTC | ||
155 | *************************************************************************/ | ||
156 | #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ | ||
157 | #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ | ||
158 | #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ | ||
159 | #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ | ||
160 | |||
161 | #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ | ||
162 | #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ | ||
163 | #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ | ||
164 | #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ | ||
165 | #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ | ||
166 | #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ | ||
167 | |||
168 | #define REG_RTC_RCR REG32(RTC_RCR) | ||
169 | #define REG_RTC_RSR REG32(RTC_RSR) | ||
170 | #define REG_RTC_RSAR REG32(RTC_RSAR) | ||
171 | #define REG_RTC_RGR REG32(RTC_RGR) | ||
172 | #define REG_RTC_HCR REG32(RTC_HCR) | ||
173 | #define REG_RTC_HWFCR REG32(RTC_HWFCR) | ||
174 | #define REG_RTC_HRCR REG32(RTC_HRCR) | ||
175 | #define REG_RTC_HWCR REG32(RTC_HWCR) | ||
176 | #define REG_RTC_HWRSR REG32(RTC_HWRSR) | ||
177 | #define REG_RTC_HSPR REG32(RTC_HSPR) | ||
178 | |||
179 | /* RTC Control Register */ | ||
180 | #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ | ||
181 | #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ | ||
182 | #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ | ||
183 | #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ | ||
184 | #define RTC_RCR_AF_BIT 4 /* Alarm Flag */ | ||
185 | #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ | ||
186 | #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ | ||
187 | #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ | ||
188 | |||
189 | /* RTC Regulator Register */ | ||
190 | #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ | ||
191 | #define RTC_RGR_ADJC_BIT 16 | ||
192 | #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) | ||
193 | #define RTC_RGR_NC1HZ_BIT 0 | ||
194 | #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) | ||
195 | |||
196 | /* Hibernate Control Register */ | ||
197 | #define RTC_HCR_PD (1 << 0) /* Power Down */ | ||
198 | |||
199 | /* Hibernate Wakeup Filter Counter Register */ | ||
200 | #define RTC_HWFCR_BIT 5 | ||
201 | #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) | ||
202 | |||
203 | /* Hibernate Reset Counter Register */ | ||
204 | #define RTC_HRCR_BIT 5 | ||
205 | #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) | ||
206 | |||
207 | /* Hibernate Wakeup Control Register */ | ||
208 | #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ | ||
209 | |||
210 | /* Hibernate Wakeup Status Register */ | ||
211 | #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ | ||
212 | #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ | ||
213 | #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ | ||
214 | #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ | ||
215 | |||
216 | |||
217 | /************************************************************************* | ||
218 | * CPM (Clock reset and Power control Management) | ||
219 | *************************************************************************/ | ||
220 | #define CPM_CPCCR (CPM_BASE+0x00) | ||
221 | #define CPM_CPPCR (CPM_BASE+0x10) | ||
222 | #define CPM_I2SCDR (CPM_BASE+0x60) | ||
223 | #define CPM_LPCDR (CPM_BASE+0x64) | ||
224 | #define CPM_MSCCDR (CPM_BASE+0x68) | ||
225 | #define CPM_UHCCDR (CPM_BASE+0x6C) | ||
226 | |||
227 | #define CPM_LCR (CPM_BASE+0x04) | ||
228 | #define CPM_CLKGR (CPM_BASE+0x20) | ||
229 | #define CPM_SCR (CPM_BASE+0x24) | ||
230 | |||
231 | #define CPM_HCR (CPM_BASE+0x30) | ||
232 | #define CPM_HWFCR (CPM_BASE+0x34) | ||
233 | #define CPM_HRCR (CPM_BASE+0x38) | ||
234 | #define CPM_HWCR (CPM_BASE+0x3c) | ||
235 | #define CPM_HWSR (CPM_BASE+0x40) | ||
236 | #define CPM_HSPR (CPM_BASE+0x44) | ||
237 | |||
238 | #define CPM_RSR (CPM_BASE+0x08) | ||
239 | |||
240 | |||
241 | #define REG_CPM_CPCCR REG32(CPM_CPCCR) | ||
242 | #define REG_CPM_CPPCR REG32(CPM_CPPCR) | ||
243 | #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) | ||
244 | #define REG_CPM_LPCDR REG32(CPM_LPCDR) | ||
245 | #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) | ||
246 | #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) | ||
247 | |||
248 | #define REG_CPM_LCR REG32(CPM_LCR) | ||
249 | #define REG_CPM_CLKGR REG32(CPM_CLKGR) | ||
250 | #define REG_CPM_SCR REG32(CPM_SCR) | ||
251 | #define REG_CPM_HCR REG32(CPM_HCR) | ||
252 | #define REG_CPM_HWFCR REG32(CPM_HWFCR) | ||
253 | #define REG_CPM_HRCR REG32(CPM_HRCR) | ||
254 | #define REG_CPM_HWCR REG32(CPM_HWCR) | ||
255 | #define REG_CPM_HWSR REG32(CPM_HWSR) | ||
256 | #define REG_CPM_HSPR REG32(CPM_HSPR) | ||
257 | |||
258 | #define REG_CPM_RSR REG32(CPM_RSR) | ||
259 | |||
260 | |||
261 | /* Clock Control Register */ | ||
262 | #define CPM_CPCCR_I2CS (1 << 31) | ||
263 | #define CPM_CPCCR_CLKOEN (1 << 30) | ||
264 | #define CPM_CPCCR_UCS (1 << 29) | ||
265 | #define CPM_CPCCR_UDIV_BIT 23 | ||
266 | #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) | ||
267 | #define CPM_CPCCR_CE (1 << 22) | ||
268 | #define CPM_CPCCR_PCS (1 << 21) | ||
269 | #define CPM_CPCCR_LDIV_BIT 16 | ||
270 | #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) | ||
271 | #define CPM_CPCCR_MDIV_BIT 12 | ||
272 | #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) | ||
273 | #define CPM_CPCCR_PDIV_BIT 8 | ||
274 | #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) | ||
275 | #define CPM_CPCCR_HDIV_BIT 4 | ||
276 | #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) | ||
277 | #define CPM_CPCCR_CDIV_BIT 0 | ||
278 | #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) | ||
279 | |||
280 | /* I2S Clock Divider Register */ | ||
281 | #define CPM_I2SCDR_I2SDIV_BIT 0 | ||
282 | #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) | ||
283 | |||
284 | /* LCD Pixel Clock Divider Register */ | ||
285 | #define CPM_LPCDR_PIXDIV_BIT 0 | ||
286 | #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) | ||
287 | |||
288 | /* MSC Clock Divider Register */ | ||
289 | #define CPM_MSCCDR_MSCDIV_BIT 0 | ||
290 | #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) | ||
291 | |||
292 | /* PLL Control Register */ | ||
293 | #define CPM_CPPCR_PLLM_BIT 23 | ||
294 | #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) | ||
295 | #define CPM_CPPCR_PLLN_BIT 18 | ||
296 | #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) | ||
297 | #define CPM_CPPCR_PLLOD_BIT 16 | ||
298 | #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) | ||
299 | #define CPM_CPPCR_PLLS (1 << 10) | ||
300 | #define CPM_CPPCR_PLLBP (1 << 9) | ||
301 | #define CPM_CPPCR_PLLEN (1 << 8) | ||
302 | #define CPM_CPPCR_PLLST_BIT 0 | ||
303 | #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) | ||
304 | |||
305 | /* Low Power Control Register */ | ||
306 | #define CPM_LCR_DOZE_DUTY_BIT 3 | ||
307 | #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) | ||
308 | #define CPM_LCR_DOZE_ON (1 << 2) | ||
309 | #define CPM_LCR_LPM_BIT 0 | ||
310 | #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) | ||
311 | #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) | ||
312 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) | ||
313 | |||
314 | /* Clock Gate Register */ | ||
315 | #define CPM_CLKGR_UART1 (1 << 15) | ||
316 | #define CPM_CLKGR_UHC (1 << 14) | ||
317 | #define CPM_CLKGR_IPU (1 << 13) | ||
318 | #define CPM_CLKGR_DMAC (1 << 12) | ||
319 | #define CPM_CLKGR_UDC (1 << 11) | ||
320 | #define CPM_CLKGR_LCD (1 << 10) | ||
321 | #define CPM_CLKGR_CIM (1 << 9) | ||
322 | #define CPM_CLKGR_SADC (1 << 8) | ||
323 | #define CPM_CLKGR_MSC (1 << 7) | ||
324 | #define CPM_CLKGR_AIC1 (1 << 6) | ||
325 | #define CPM_CLKGR_AIC2 (1 << 5) | ||
326 | #define CPM_CLKGR_SSI (1 << 4) | ||
327 | #define CPM_CLKGR_I2C (1 << 3) | ||
328 | #define CPM_CLKGR_RTC (1 << 2) | ||
329 | #define CPM_CLKGR_TCU (1 << 1) | ||
330 | #define CPM_CLKGR_UART0 (1 << 0) | ||
331 | |||
332 | /* Sleep Control Register */ | ||
333 | #define CPM_SCR_O1ST_BIT 8 | ||
334 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) | ||
335 | #define CPM_SCR_USBPHY_ENABLE (1 << 6) | ||
336 | #define CPM_SCR_OSC_ENABLE (1 << 4) | ||
337 | |||
338 | /* Hibernate Control Register */ | ||
339 | #define CPM_HCR_PD (1 << 0) | ||
340 | |||
341 | /* Wakeup Filter Counter Register in Hibernate Mode */ | ||
342 | #define CPM_HWFCR_TIME_BIT 0 | ||
343 | #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) | ||
344 | |||
345 | /* Reset Counter Register in Hibernate Mode */ | ||
346 | #define CPM_HRCR_TIME_BIT 0 | ||
347 | #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) | ||
348 | |||
349 | /* Wakeup Control Register in Hibernate Mode */ | ||
350 | #define CPM_HWCR_WLE_LOW (0 << 2) | ||
351 | #define CPM_HWCR_WLE_HIGH (1 << 2) | ||
352 | #define CPM_HWCR_PIN_WAKEUP (1 << 1) | ||
353 | #define CPM_HWCR_RTC_WAKEUP (1 << 0) | ||
354 | |||
355 | /* Wakeup Status Register in Hibernate Mode */ | ||
356 | #define CPM_HWSR_WSR_PIN (1 << 1) | ||
357 | #define CPM_HWSR_WSR_RTC (1 << 0) | ||
358 | |||
359 | /* Reset Status Register */ | ||
360 | #define CPM_RSR_HR (1 << 2) | ||
361 | #define CPM_RSR_WR (1 << 1) | ||
362 | #define CPM_RSR_PR (1 << 0) | ||
363 | |||
364 | |||
365 | /************************************************************************* | ||
366 | * TCU (Timer Counter Unit) | ||
367 | *************************************************************************/ | ||
368 | #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ | ||
369 | #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ | ||
370 | #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ | ||
371 | #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ | ||
372 | #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ | ||
373 | #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ | ||
374 | #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ | ||
375 | #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ | ||
376 | #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ | ||
377 | #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ | ||
378 | #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ | ||
379 | #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ | ||
380 | #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ | ||
381 | #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ | ||
382 | #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ | ||
383 | #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ | ||
384 | #define TCU_TDFR1 (TCU_BASE + 0x50) | ||
385 | #define TCU_TDHR1 (TCU_BASE + 0x54) | ||
386 | #define TCU_TCNT1 (TCU_BASE + 0x58) | ||
387 | #define TCU_TCSR1 (TCU_BASE + 0x5C) | ||
388 | #define TCU_TDFR2 (TCU_BASE + 0x60) | ||
389 | #define TCU_TDHR2 (TCU_BASE + 0x64) | ||
390 | #define TCU_TCNT2 (TCU_BASE + 0x68) | ||
391 | #define TCU_TCSR2 (TCU_BASE + 0x6C) | ||
392 | #define TCU_TDFR3 (TCU_BASE + 0x70) | ||
393 | #define TCU_TDHR3 (TCU_BASE + 0x74) | ||
394 | #define TCU_TCNT3 (TCU_BASE + 0x78) | ||
395 | #define TCU_TCSR3 (TCU_BASE + 0x7C) | ||
396 | #define TCU_TDFR4 (TCU_BASE + 0x80) | ||
397 | #define TCU_TDHR4 (TCU_BASE + 0x84) | ||
398 | #define TCU_TCNT4 (TCU_BASE + 0x88) | ||
399 | #define TCU_TCSR4 (TCU_BASE + 0x8C) | ||
400 | #define TCU_TDFR5 (TCU_BASE + 0x90) | ||
401 | #define TCU_TDHR5 (TCU_BASE + 0x94) | ||
402 | #define TCU_TCNT5 (TCU_BASE + 0x98) | ||
403 | #define TCU_TCSR5 (TCU_BASE + 0x9C) | ||
404 | |||
405 | #define REG_TCU_TSR REG32(TCU_TSR) | ||
406 | #define REG_TCU_TSSR REG32(TCU_TSSR) | ||
407 | #define REG_TCU_TSCR REG32(TCU_TSCR) | ||
408 | #define REG_TCU_TER REG8(TCU_TER) | ||
409 | #define REG_TCU_TESR REG8(TCU_TESR) | ||
410 | #define REG_TCU_TECR REG8(TCU_TECR) | ||
411 | #define REG_TCU_TFR REG32(TCU_TFR) | ||
412 | #define REG_TCU_TFSR REG32(TCU_TFSR) | ||
413 | #define REG_TCU_TFCR REG32(TCU_TFCR) | ||
414 | #define REG_TCU_TMR REG32(TCU_TMR) | ||
415 | #define REG_TCU_TMSR REG32(TCU_TMSR) | ||
416 | #define REG_TCU_TMCR REG32(TCU_TMCR) | ||
417 | #define REG_TCU_TDFR0 REG16(TCU_TDFR0) | ||
418 | #define REG_TCU_TDHR0 REG16(TCU_TDHR0) | ||
419 | #define REG_TCU_TCNT0 REG16(TCU_TCNT0) | ||
420 | #define REG_TCU_TCSR0 REG16(TCU_TCSR0) | ||
421 | #define REG_TCU_TDFR1 REG16(TCU_TDFR1) | ||
422 | #define REG_TCU_TDHR1 REG16(TCU_TDHR1) | ||
423 | #define REG_TCU_TCNT1 REG16(TCU_TCNT1) | ||
424 | #define REG_TCU_TCSR1 REG16(TCU_TCSR1) | ||
425 | #define REG_TCU_TDFR2 REG16(TCU_TDFR2) | ||
426 | #define REG_TCU_TDHR2 REG16(TCU_TDHR2) | ||
427 | #define REG_TCU_TCNT2 REG16(TCU_TCNT2) | ||
428 | #define REG_TCU_TCSR2 REG16(TCU_TCSR2) | ||
429 | #define REG_TCU_TDFR3 REG16(TCU_TDFR3) | ||
430 | #define REG_TCU_TDHR3 REG16(TCU_TDHR3) | ||
431 | #define REG_TCU_TCNT3 REG16(TCU_TCNT3) | ||
432 | #define REG_TCU_TCSR3 REG16(TCU_TCSR3) | ||
433 | #define REG_TCU_TDFR4 REG16(TCU_TDFR4) | ||
434 | #define REG_TCU_TDHR4 REG16(TCU_TDHR4) | ||
435 | #define REG_TCU_TCNT4 REG16(TCU_TCNT4) | ||
436 | #define REG_TCU_TCSR4 REG16(TCU_TCSR4) | ||
437 | |||
438 | // n = 0,1,2,3,4,5 | ||
439 | #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ | ||
440 | #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ | ||
441 | #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ | ||
442 | #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ | ||
443 | |||
444 | #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) | ||
445 | #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) | ||
446 | #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) | ||
447 | #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) | ||
448 | |||
449 | // Register definitions | ||
450 | #define TCU_TCSR_PWM_SD (1 << 9) | ||
451 | #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) | ||
452 | #define TCU_TCSR_PWM_EN (1 << 7) | ||
453 | #define TCU_TCSR_PRESCALE_BIT 3 | ||
454 | #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) | ||
455 | #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) | ||
456 | #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) | ||
457 | #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) | ||
458 | #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) | ||
459 | #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) | ||
460 | #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) | ||
461 | #define TCU_TCSR_EXT_EN (1 << 2) | ||
462 | #define TCU_TCSR_RTC_EN (1 << 1) | ||
463 | #define TCU_TCSR_PCK_EN (1 << 0) | ||
464 | |||
465 | #define TCU_TER_TCEN5 (1 << 5) | ||
466 | #define TCU_TER_TCEN4 (1 << 4) | ||
467 | #define TCU_TER_TCEN3 (1 << 3) | ||
468 | #define TCU_TER_TCEN2 (1 << 2) | ||
469 | #define TCU_TER_TCEN1 (1 << 1) | ||
470 | #define TCU_TER_TCEN0 (1 << 0) | ||
471 | |||
472 | #define TCU_TESR_TCST5 (1 << 5) | ||
473 | #define TCU_TESR_TCST4 (1 << 4) | ||
474 | #define TCU_TESR_TCST3 (1 << 3) | ||
475 | #define TCU_TESR_TCST2 (1 << 2) | ||
476 | #define TCU_TESR_TCST1 (1 << 1) | ||
477 | #define TCU_TESR_TCST0 (1 << 0) | ||
478 | |||
479 | #define TCU_TECR_TCCL5 (1 << 5) | ||
480 | #define TCU_TECR_TCCL4 (1 << 4) | ||
481 | #define TCU_TECR_TCCL3 (1 << 3) | ||
482 | #define TCU_TECR_TCCL2 (1 << 2) | ||
483 | #define TCU_TECR_TCCL1 (1 << 1) | ||
484 | #define TCU_TECR_TCCL0 (1 << 0) | ||
485 | |||
486 | #define TCU_TFR_HFLAG5 (1 << 21) | ||
487 | #define TCU_TFR_HFLAG4 (1 << 20) | ||
488 | #define TCU_TFR_HFLAG3 (1 << 19) | ||
489 | #define TCU_TFR_HFLAG2 (1 << 18) | ||
490 | #define TCU_TFR_HFLAG1 (1 << 17) | ||
491 | #define TCU_TFR_HFLAG0 (1 << 16) | ||
492 | #define TCU_TFR_FFLAG5 (1 << 5) | ||
493 | #define TCU_TFR_FFLAG4 (1 << 4) | ||
494 | #define TCU_TFR_FFLAG3 (1 << 3) | ||
495 | #define TCU_TFR_FFLAG2 (1 << 2) | ||
496 | #define TCU_TFR_FFLAG1 (1 << 1) | ||
497 | #define TCU_TFR_FFLAG0 (1 << 0) | ||
498 | |||
499 | #define TCU_TFSR_HFLAG5 (1 << 21) | ||
500 | #define TCU_TFSR_HFLAG4 (1 << 20) | ||
501 | #define TCU_TFSR_HFLAG3 (1 << 19) | ||
502 | #define TCU_TFSR_HFLAG2 (1 << 18) | ||
503 | #define TCU_TFSR_HFLAG1 (1 << 17) | ||
504 | #define TCU_TFSR_HFLAG0 (1 << 16) | ||
505 | #define TCU_TFSR_FFLAG5 (1 << 5) | ||
506 | #define TCU_TFSR_FFLAG4 (1 << 4) | ||
507 | #define TCU_TFSR_FFLAG3 (1 << 3) | ||
508 | #define TCU_TFSR_FFLAG2 (1 << 2) | ||
509 | #define TCU_TFSR_FFLAG1 (1 << 1) | ||
510 | #define TCU_TFSR_FFLAG0 (1 << 0) | ||
511 | |||
512 | #define TCU_TFCR_HFLAG5 (1 << 21) | ||
513 | #define TCU_TFCR_HFLAG4 (1 << 20) | ||
514 | #define TCU_TFCR_HFLAG3 (1 << 19) | ||
515 | #define TCU_TFCR_HFLAG2 (1 << 18) | ||
516 | #define TCU_TFCR_HFLAG1 (1 << 17) | ||
517 | #define TCU_TFCR_HFLAG0 (1 << 16) | ||
518 | #define TCU_TFCR_FFLAG5 (1 << 5) | ||
519 | #define TCU_TFCR_FFLAG4 (1 << 4) | ||
520 | #define TCU_TFCR_FFLAG3 (1 << 3) | ||
521 | #define TCU_TFCR_FFLAG2 (1 << 2) | ||
522 | #define TCU_TFCR_FFLAG1 (1 << 1) | ||
523 | #define TCU_TFCR_FFLAG0 (1 << 0) | ||
524 | |||
525 | #define TCU_TMR_HMASK5 (1 << 21) | ||
526 | #define TCU_TMR_HMASK4 (1 << 20) | ||
527 | #define TCU_TMR_HMASK3 (1 << 19) | ||
528 | #define TCU_TMR_HMASK2 (1 << 18) | ||
529 | #define TCU_TMR_HMASK1 (1 << 17) | ||
530 | #define TCU_TMR_HMASK0 (1 << 16) | ||
531 | #define TCU_TMR_FMASK5 (1 << 5) | ||
532 | #define TCU_TMR_FMASK4 (1 << 4) | ||
533 | #define TCU_TMR_FMASK3 (1 << 3) | ||
534 | #define TCU_TMR_FMASK2 (1 << 2) | ||
535 | #define TCU_TMR_FMASK1 (1 << 1) | ||
536 | #define TCU_TMR_FMASK0 (1 << 0) | ||
537 | |||
538 | #define TCU_TMSR_HMST5 (1 << 21) | ||
539 | #define TCU_TMSR_HMST4 (1 << 20) | ||
540 | #define TCU_TMSR_HMST3 (1 << 19) | ||
541 | #define TCU_TMSR_HMST2 (1 << 18) | ||
542 | #define TCU_TMSR_HMST1 (1 << 17) | ||
543 | #define TCU_TMSR_HMST0 (1 << 16) | ||
544 | #define TCU_TMSR_FMST5 (1 << 5) | ||
545 | #define TCU_TMSR_FMST4 (1 << 4) | ||
546 | #define TCU_TMSR_FMST3 (1 << 3) | ||
547 | #define TCU_TMSR_FMST2 (1 << 2) | ||
548 | #define TCU_TMSR_FMST1 (1 << 1) | ||
549 | #define TCU_TMSR_FMST0 (1 << 0) | ||
550 | |||
551 | #define TCU_TMCR_HMCL5 (1 << 21) | ||
552 | #define TCU_TMCR_HMCL4 (1 << 20) | ||
553 | #define TCU_TMCR_HMCL3 (1 << 19) | ||
554 | #define TCU_TMCR_HMCL2 (1 << 18) | ||
555 | #define TCU_TMCR_HMCL1 (1 << 17) | ||
556 | #define TCU_TMCR_HMCL0 (1 << 16) | ||
557 | #define TCU_TMCR_FMCL5 (1 << 5) | ||
558 | #define TCU_TMCR_FMCL4 (1 << 4) | ||
559 | #define TCU_TMCR_FMCL3 (1 << 3) | ||
560 | #define TCU_TMCR_FMCL2 (1 << 2) | ||
561 | #define TCU_TMCR_FMCL1 (1 << 1) | ||
562 | #define TCU_TMCR_FMCL0 (1 << 0) | ||
563 | |||
564 | #define TCU_TSR_WDTS (1 << 16) | ||
565 | #define TCU_TSR_STOP5 (1 << 5) | ||
566 | #define TCU_TSR_STOP4 (1 << 4) | ||
567 | #define TCU_TSR_STOP3 (1 << 3) | ||
568 | #define TCU_TSR_STOP2 (1 << 2) | ||
569 | #define TCU_TSR_STOP1 (1 << 1) | ||
570 | #define TCU_TSR_STOP0 (1 << 0) | ||
571 | |||
572 | #define TCU_TSSR_WDTSS (1 << 16) | ||
573 | #define TCU_TSSR_STPS5 (1 << 5) | ||
574 | #define TCU_TSSR_STPS4 (1 << 4) | ||
575 | #define TCU_TSSR_STPS3 (1 << 3) | ||
576 | #define TCU_TSSR_STPS2 (1 << 2) | ||
577 | #define TCU_TSSR_STPS1 (1 << 1) | ||
578 | #define TCU_TSSR_STPS0 (1 << 0) | ||
579 | |||
580 | #define TCU_TSSR_WDTSC (1 << 16) | ||
581 | #define TCU_TSSR_STPC5 (1 << 5) | ||
582 | #define TCU_TSSR_STPC4 (1 << 4) | ||
583 | #define TCU_TSSR_STPC3 (1 << 3) | ||
584 | #define TCU_TSSR_STPC2 (1 << 2) | ||
585 | #define TCU_TSSR_STPC1 (1 << 1) | ||
586 | #define TCU_TSSR_STPC0 (1 << 0) | ||
587 | |||
588 | |||
589 | /************************************************************************* | ||
590 | * WDT (WatchDog Timer) | ||
591 | *************************************************************************/ | ||
592 | #define WDT_TDR (WDT_BASE + 0x00) | ||
593 | #define WDT_TCER (WDT_BASE + 0x04) | ||
594 | #define WDT_TCNT (WDT_BASE + 0x08) | ||
595 | #define WDT_TCSR (WDT_BASE + 0x0C) | ||
596 | |||
597 | #define REG_WDT_TDR REG16(WDT_TDR) | ||
598 | #define REG_WDT_TCER REG8(WDT_TCER) | ||
599 | #define REG_WDT_TCNT REG16(WDT_TCNT) | ||
600 | #define REG_WDT_TCSR REG16(WDT_TCSR) | ||
601 | |||
602 | // Register definition | ||
603 | #define WDT_TCSR_PRESCALE_BIT 3 | ||
604 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) | ||
605 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) | ||
606 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) | ||
607 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) | ||
608 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) | ||
609 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) | ||
610 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) | ||
611 | #define WDT_TCSR_EXT_EN (1 << 2) | ||
612 | #define WDT_TCSR_RTC_EN (1 << 1) | ||
613 | #define WDT_TCSR_PCK_EN (1 << 0) | ||
614 | |||
615 | #define WDT_TCER_TCEN (1 << 0) | ||
616 | |||
617 | |||
618 | /************************************************************************* | ||
619 | * DMAC (DMA Controller) | ||
620 | *************************************************************************/ | ||
621 | |||
622 | #define MAX_DMA_NUM 6 /* max 6 channels */ | ||
623 | |||
624 | #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ | ||
625 | #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ | ||
626 | #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ | ||
627 | #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ | ||
628 | #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ | ||
629 | #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ | ||
630 | #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ | ||
631 | #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ | ||
632 | #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ | ||
633 | #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ | ||
634 | #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ | ||
635 | |||
636 | // channel 0 | ||
637 | #define DMAC_DSAR0 DMAC_DSAR(0) | ||
638 | #define DMAC_DTAR0 DMAC_DTAR(0) | ||
639 | #define DMAC_DTCR0 DMAC_DTCR(0) | ||
640 | #define DMAC_DRSR0 DMAC_DRSR(0) | ||
641 | #define DMAC_DCCSR0 DMAC_DCCSR(0) | ||
642 | #define DMAC_DCMD0 DMAC_DCMD(0) | ||
643 | #define DMAC_DDA0 DMAC_DDA(0) | ||
644 | |||
645 | // channel 1 | ||
646 | #define DMAC_DSAR1 DMAC_DSAR(1) | ||
647 | #define DMAC_DTAR1 DMAC_DTAR(1) | ||
648 | #define DMAC_DTCR1 DMAC_DTCR(1) | ||
649 | #define DMAC_DRSR1 DMAC_DRSR(1) | ||
650 | #define DMAC_DCCSR1 DMAC_DCCSR(1) | ||
651 | #define DMAC_DCMD1 DMAC_DCMD(1) | ||
652 | #define DMAC_DDA1 DMAC_DDA(1) | ||
653 | |||
654 | // channel 2 | ||
655 | #define DMAC_DSAR2 DMAC_DSAR(2) | ||
656 | #define DMAC_DTAR2 DMAC_DTAR(2) | ||
657 | #define DMAC_DTCR2 DMAC_DTCR(2) | ||
658 | #define DMAC_DRSR2 DMAC_DRSR(2) | ||
659 | #define DMAC_DCCSR2 DMAC_DCCSR(2) | ||
660 | #define DMAC_DCMD2 DMAC_DCMD(2) | ||
661 | #define DMAC_DDA2 DMAC_DDA(2) | ||
662 | |||
663 | // channel 3 | ||
664 | #define DMAC_DSAR3 DMAC_DSAR(3) | ||
665 | #define DMAC_DTAR3 DMAC_DTAR(3) | ||
666 | #define DMAC_DTCR3 DMAC_DTCR(3) | ||
667 | #define DMAC_DRSR3 DMAC_DRSR(3) | ||
668 | #define DMAC_DCCSR3 DMAC_DCCSR(3) | ||
669 | #define DMAC_DCMD3 DMAC_DCMD(3) | ||
670 | #define DMAC_DDA3 DMAC_DDA(3) | ||
671 | |||
672 | // channel 4 | ||
673 | #define DMAC_DSAR4 DMAC_DSAR(4) | ||
674 | #define DMAC_DTAR4 DMAC_DTAR(4) | ||
675 | #define DMAC_DTCR4 DMAC_DTCR(4) | ||
676 | #define DMAC_DRSR4 DMAC_DRSR(4) | ||
677 | #define DMAC_DCCSR4 DMAC_DCCSR(4) | ||
678 | #define DMAC_DCMD4 DMAC_DCMD(4) | ||
679 | #define DMAC_DDA4 DMAC_DDA(4) | ||
680 | |||
681 | // channel 5 | ||
682 | #define DMAC_DSAR5 DMAC_DSAR(5) | ||
683 | #define DMAC_DTAR5 DMAC_DTAR(5) | ||
684 | #define DMAC_DTCR5 DMAC_DTCR(5) | ||
685 | #define DMAC_DRSR5 DMAC_DRSR(5) | ||
686 | #define DMAC_DCCSR5 DMAC_DCCSR(5) | ||
687 | #define DMAC_DCMD5 DMAC_DCMD(5) | ||
688 | #define DMAC_DDA5 DMAC_DDA(5) | ||
689 | |||
690 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) | ||
691 | #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) | ||
692 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) | ||
693 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) | ||
694 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) | ||
695 | #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) | ||
696 | #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) | ||
697 | #define REG_DMAC_DMACR REG32(DMAC_DMACR) | ||
698 | #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) | ||
699 | #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) | ||
700 | #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) | ||
701 | |||
702 | // DMA request source register | ||
703 | #define DMAC_DRSR_RS_BIT 0 | ||
704 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) | ||
705 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) | ||
706 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) | ||
707 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) | ||
708 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) | ||
709 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) | ||
710 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) | ||
711 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) | ||
712 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) | ||
713 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) | ||
714 | #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) | ||
715 | #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) | ||
716 | #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) | ||
717 | |||
718 | // DMA channel control/status register | ||
719 | #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ | ||
720 | #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ | ||
721 | #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) | ||
722 | #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ | ||
723 | #define DMAC_DCCSR_AR (1 << 4) /* address error */ | ||
724 | #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ | ||
725 | #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ | ||
726 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ | ||
727 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ | ||
728 | |||
729 | // DMA channel command register | ||
730 | #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ | ||
731 | #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ | ||
732 | #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ | ||
733 | #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) | ||
734 | #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) | ||
735 | #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) | ||
736 | #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) | ||
737 | #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) | ||
738 | #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) | ||
739 | #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) | ||
740 | #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) | ||
741 | #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) | ||
742 | #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) | ||
743 | #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) | ||
744 | #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) | ||
745 | #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) | ||
746 | #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) | ||
747 | #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) | ||
748 | #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) | ||
749 | #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) | ||
750 | #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ | ||
751 | #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) | ||
752 | #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) | ||
753 | #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) | ||
754 | #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) | ||
755 | #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ | ||
756 | #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) | ||
757 | #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) | ||
758 | #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) | ||
759 | #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) | ||
760 | #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ | ||
761 | #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) | ||
762 | #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) | ||
763 | #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) | ||
764 | #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) | ||
765 | #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) | ||
766 | #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) | ||
767 | #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ | ||
768 | #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ | ||
769 | #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ | ||
770 | #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ | ||
771 | #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ | ||
772 | #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ | ||
773 | |||
774 | // DMA descriptor address register | ||
775 | #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ | ||
776 | #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) | ||
777 | #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ | ||
778 | #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) | ||
779 | |||
780 | // DMA control register | ||
781 | #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ | ||
782 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) | ||
783 | #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) | ||
784 | #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) | ||
785 | #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) | ||
786 | #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ | ||
787 | #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ | ||
788 | #define DMAC_DMACR_AR (1 << 2) /* address error flag */ | ||
789 | #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ | ||
790 | |||
791 | // DMA doorbell register | ||
792 | #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ | ||
793 | #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ | ||
794 | #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ | ||
795 | #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ | ||
796 | #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ | ||
797 | #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ | ||
798 | |||
799 | // DMA doorbell set register | ||
800 | #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ | ||
801 | #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ | ||
802 | #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ | ||
803 | #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ | ||
804 | #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ | ||
805 | #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ | ||
806 | |||
807 | // DMA interrupt pending register | ||
808 | #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ | ||
809 | #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ | ||
810 | #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ | ||
811 | #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ | ||
812 | #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ | ||
813 | #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ | ||
814 | |||
815 | |||
816 | /************************************************************************* | ||
817 | * GPIO (General-Purpose I/O Ports) | ||
818 | *************************************************************************/ | ||
819 | #define MAX_GPIO_NUM 128 | ||
820 | |||
821 | //n = 0,1,2,3 | ||
822 | #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ | ||
823 | #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ | ||
824 | #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ | ||
825 | #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ | ||
826 | #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ | ||
827 | #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ | ||
828 | #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ | ||
829 | #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ | ||
830 | #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ | ||
831 | #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ | ||
832 | #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ | ||
833 | #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ | ||
834 | #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ | ||
835 | #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ | ||
836 | #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ | ||
837 | #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ | ||
838 | #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ | ||
839 | #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ | ||
840 | #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ | ||
841 | #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ | ||
842 | #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ | ||
843 | #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ | ||
844 | #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ | ||
845 | #define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ | ||
846 | |||
847 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ | ||
848 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ | ||
849 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) | ||
850 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) | ||
851 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ | ||
852 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) | ||
853 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) | ||
854 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ | ||
855 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) | ||
856 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) | ||
857 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ | ||
858 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) | ||
859 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) | ||
860 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ | ||
861 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) | ||
862 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) | ||
863 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ | ||
864 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) | ||
865 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) | ||
866 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ | ||
867 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) | ||
868 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) | ||
869 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ | ||
870 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ | ||
871 | |||
872 | |||
873 | /************************************************************************* | ||
874 | * UART | ||
875 | *************************************************************************/ | ||
876 | |||
877 | #define IRDA_BASE UART0_BASE | ||
878 | #define UART_BASE UART0_BASE | ||
879 | #define UART_OFF 0x1000 | ||
880 | |||
881 | /* Register Offset */ | ||
882 | #define OFF_RDR (0x00) /* R 8b H'xx */ | ||
883 | #define OFF_TDR (0x00) /* W 8b H'xx */ | ||
884 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ | ||
885 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ | ||
886 | #define OFF_IER (0x04) /* RW 8b H'00 */ | ||
887 | #define OFF_ISR (0x08) /* R 8b H'01 */ | ||
888 | #define OFF_FCR (0x08) /* W 8b H'00 */ | ||
889 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ | ||
890 | #define OFF_MCR (0x10) /* RW 8b H'00 */ | ||
891 | #define OFF_LSR (0x14) /* R 8b H'00 */ | ||
892 | #define OFF_MSR (0x18) /* R 8b H'00 */ | ||
893 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ | ||
894 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ | ||
895 | #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ | ||
896 | #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ | ||
897 | |||
898 | /* Register Address */ | ||
899 | #define UART0_RDR (UART0_BASE + OFF_RDR) | ||
900 | #define UART0_TDR (UART0_BASE + OFF_TDR) | ||
901 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) | ||
902 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) | ||
903 | #define UART0_IER (UART0_BASE + OFF_IER) | ||
904 | #define UART0_ISR (UART0_BASE + OFF_ISR) | ||
905 | #define UART0_FCR (UART0_BASE + OFF_FCR) | ||
906 | #define UART0_LCR (UART0_BASE + OFF_LCR) | ||
907 | #define UART0_MCR (UART0_BASE + OFF_MCR) | ||
908 | #define UART0_LSR (UART0_BASE + OFF_LSR) | ||
909 | #define UART0_MSR (UART0_BASE + OFF_MSR) | ||
910 | #define UART0_SPR (UART0_BASE + OFF_SPR) | ||
911 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) | ||
912 | #define UART0_UMR (UART0_BASE + OFF_UMR) | ||
913 | #define UART0_UACR (UART0_BASE + OFF_UACR) | ||
914 | |||
915 | /* | ||
916 | * Define macros for UART_IER | ||
917 | * UART Interrupt Enable Register | ||
918 | */ | ||
919 | #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ | ||
920 | #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ | ||
921 | #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ | ||
922 | #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ | ||
923 | #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ | ||
924 | |||
925 | /* | ||
926 | * Define macros for UART_ISR | ||
927 | * UART Interrupt Status Register | ||
928 | */ | ||
929 | #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ | ||
930 | #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ | ||
931 | #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ | ||
932 | #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ | ||
933 | #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ | ||
934 | #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ | ||
935 | #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ | ||
936 | #define UART_ISR_FFMS_NO_FIFO (0 << 6) | ||
937 | #define UART_ISR_FFMS_FIFO_MODE (3 << 6) | ||
938 | |||
939 | /* | ||
940 | * Define macros for UART_FCR | ||
941 | * UART FIFO Control Register | ||
942 | */ | ||
943 | #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ | ||
944 | #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ | ||
945 | #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ | ||
946 | #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ | ||
947 | #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ | ||
948 | #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ | ||
949 | #define UART_FCR_RTRG_1 (0 << 6) | ||
950 | #define UART_FCR_RTRG_4 (1 << 6) | ||
951 | #define UART_FCR_RTRG_8 (2 << 6) | ||
952 | #define UART_FCR_RTRG_15 (3 << 6) | ||
953 | |||
954 | /* | ||
955 | * Define macros for UART_LCR | ||
956 | * UART Line Control Register | ||
957 | */ | ||
958 | #define UART_LCR_WLEN (3 << 0) /* word length */ | ||
959 | #define UART_LCR_WLEN_5 (0 << 0) | ||
960 | #define UART_LCR_WLEN_6 (1 << 0) | ||
961 | #define UART_LCR_WLEN_7 (2 << 0) | ||
962 | #define UART_LCR_WLEN_8 (3 << 0) | ||
963 | #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 | ||
964 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ | ||
965 | #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 | ||
966 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ | ||
967 | #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 | ||
968 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ | ||
969 | |||
970 | #define UART_LCR_PE (1 << 3) /* 0: parity disable */ | ||
971 | #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ | ||
972 | #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ | ||
973 | #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ | ||
974 | #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ | ||
975 | |||
976 | /* | ||
977 | * Define macros for UART_LSR | ||
978 | * UART Line Status Register | ||
979 | */ | ||
980 | #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ | ||
981 | #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ | ||
982 | #define UART_LSR_PER (1 << 2) /* 0: no parity error */ | ||
983 | #define UART_LSR_FER (1 << 3) /* 0; no framing error */ | ||
984 | #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ | ||
985 | #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ | ||
986 | #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ | ||
987 | #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ | ||
988 | |||
989 | /* | ||
990 | * Define macros for UART_MCR | ||
991 | * UART Modem Control Register | ||
992 | */ | ||
993 | #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ | ||
994 | #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ | ||
995 | #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ | ||
996 | #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ | ||
997 | #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ | ||
998 | #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ | ||
999 | |||
1000 | /* | ||
1001 | * Define macros for UART_MSR | ||
1002 | * UART Modem Status Register | ||
1003 | */ | ||
1004 | #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ | ||
1005 | #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ | ||
1006 | #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ | ||
1007 | #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ | ||
1008 | #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ | ||
1009 | #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ | ||
1010 | #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ | ||
1011 | #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ | ||
1012 | |||
1013 | /* | ||
1014 | * Define macros for SIRCR | ||
1015 | * Slow IrDA Control Register | ||
1016 | */ | ||
1017 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ | ||
1018 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ | ||
1019 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length | ||
1020 | 1: 0 pulse width is 1.6us for 115.2Kbps */ | ||
1021 | #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ | ||
1022 | #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ | ||
1023 | |||
1024 | |||
1025 | /************************************************************************* | ||
1026 | * AIC (AC97/I2S Controller) | ||
1027 | *************************************************************************/ | ||
1028 | #define AIC_FR (AIC_BASE + 0x000) | ||
1029 | #define AIC_CR (AIC_BASE + 0x004) | ||
1030 | #define AIC_ACCR1 (AIC_BASE + 0x008) | ||
1031 | #define AIC_ACCR2 (AIC_BASE + 0x00C) | ||
1032 | #define AIC_I2SCR (AIC_BASE + 0x010) | ||
1033 | #define AIC_SR (AIC_BASE + 0x014) | ||
1034 | #define AIC_ACSR (AIC_BASE + 0x018) | ||
1035 | #define AIC_I2SSR (AIC_BASE + 0x01C) | ||
1036 | #define AIC_ACCAR (AIC_BASE + 0x020) | ||
1037 | #define AIC_ACCDR (AIC_BASE + 0x024) | ||
1038 | #define AIC_ACSAR (AIC_BASE + 0x028) | ||
1039 | #define AIC_ACSDR (AIC_BASE + 0x02C) | ||
1040 | #define AIC_I2SDIV (AIC_BASE + 0x030) | ||
1041 | #define AIC_DR (AIC_BASE + 0x034) | ||
1042 | |||
1043 | #define REG_AIC_FR REG32(AIC_FR) | ||
1044 | #define REG_AIC_CR REG32(AIC_CR) | ||
1045 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) | ||
1046 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) | ||
1047 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) | ||
1048 | #define REG_AIC_SR REG32(AIC_SR) | ||
1049 | #define REG_AIC_ACSR REG32(AIC_ACSR) | ||
1050 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) | ||
1051 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) | ||
1052 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) | ||
1053 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) | ||
1054 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) | ||
1055 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) | ||
1056 | #define REG_AIC_DR REG32(AIC_DR) | ||
1057 | |||
1058 | /* AIC Controller Configuration Register (AIC_FR) */ | ||
1059 | |||
1060 | #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ | ||
1061 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) | ||
1062 | #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ | ||
1063 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) | ||
1064 | #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ | ||
1065 | #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ | ||
1066 | #define AIC_FR_RST (1 << 3) /* AIC registers reset */ | ||
1067 | #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ | ||
1068 | #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ | ||
1069 | #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ | ||
1070 | |||
1071 | /* AIC Controller Common Control Register (AIC_CR) */ | ||
1072 | |||
1073 | #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ | ||
1074 | #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) | ||
1075 | #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) | ||
1076 | #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) | ||
1077 | #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) | ||
1078 | #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) | ||
1079 | #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) | ||
1080 | #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ | ||
1081 | #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) | ||
1082 | #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) | ||
1083 | #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) | ||
1084 | #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) | ||
1085 | #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) | ||
1086 | #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) | ||
1087 | #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ | ||
1088 | #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ | ||
1089 | #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ | ||
1090 | #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ | ||
1091 | #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ | ||
1092 | #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ | ||
1093 | #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ | ||
1094 | #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ | ||
1095 | #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ | ||
1096 | #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ | ||
1097 | #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ | ||
1098 | #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ | ||
1099 | #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ | ||
1100 | |||
1101 | /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ | ||
1102 | |||
1103 | #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ | ||
1104 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) | ||
1105 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ | ||
1106 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ | ||
1107 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ | ||
1108 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ | ||
1109 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ | ||
1110 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ | ||
1111 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ | ||
1112 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ | ||
1113 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ | ||
1114 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ | ||
1115 | #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ | ||
1116 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) | ||
1117 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ | ||
1118 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ | ||
1119 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ | ||
1120 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ | ||
1121 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ | ||
1122 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ | ||
1123 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ | ||
1124 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ | ||
1125 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ | ||
1126 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ | ||
1127 | |||
1128 | /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ | ||
1129 | |||
1130 | #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ | ||
1131 | #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ | ||
1132 | #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ | ||
1133 | #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ | ||
1134 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) | ||
1135 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ | ||
1136 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ | ||
1137 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ | ||
1138 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ | ||
1139 | #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ | ||
1140 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) | ||
1141 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ | ||
1142 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ | ||
1143 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ | ||
1144 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ | ||
1145 | #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ | ||
1146 | #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ | ||
1147 | #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ | ||
1148 | #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ | ||
1149 | |||
1150 | /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ | ||
1151 | |||
1152 | #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ | ||
1153 | #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ | ||
1154 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) | ||
1155 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ | ||
1156 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ | ||
1157 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ | ||
1158 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ | ||
1159 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ | ||
1160 | #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ | ||
1161 | |||
1162 | /* AIC Controller FIFO Status Register (AIC_SR) */ | ||
1163 | |||
1164 | #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ | ||
1165 | #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) | ||
1166 | #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ | ||
1167 | #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) | ||
1168 | #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ | ||
1169 | #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ | ||
1170 | #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ | ||
1171 | #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ | ||
1172 | |||
1173 | /* AIC Controller AC-link Status Register (AIC_ACSR) */ | ||
1174 | |||
1175 | #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ | ||
1176 | #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ | ||
1177 | #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ | ||
1178 | #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ | ||
1179 | #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ | ||
1180 | #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ | ||
1181 | |||
1182 | /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ | ||
1183 | |||
1184 | #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ | ||
1185 | |||
1186 | /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ | ||
1187 | |||
1188 | #define AIC_ACCAR_CAR_BIT 0 | ||
1189 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) | ||
1190 | |||
1191 | /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ | ||
1192 | |||
1193 | #define AIC_ACCDR_CDR_BIT 0 | ||
1194 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) | ||
1195 | |||
1196 | /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ | ||
1197 | |||
1198 | #define AIC_ACSAR_SAR_BIT 0 | ||
1199 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) | ||
1200 | |||
1201 | /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ | ||
1202 | |||
1203 | #define AIC_ACSDR_SDR_BIT 0 | ||
1204 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) | ||
1205 | |||
1206 | /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ | ||
1207 | |||
1208 | #define AIC_I2SDIV_DIV_BIT 0 | ||
1209 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) | ||
1210 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ | ||
1211 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ | ||
1212 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ | ||
1213 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ | ||
1214 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ | ||
1215 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ | ||
1216 | |||
1217 | |||
1218 | /************************************************************************* | ||
1219 | * ICDC (Internal CODEC) | ||
1220 | *************************************************************************/ | ||
1221 | #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ | ||
1222 | #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ | ||
1223 | #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ | ||
1224 | #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ | ||
1225 | #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ | ||
1226 | #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) | ||
1227 | #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) | ||
1228 | |||
1229 | #define REG_ICDC_CR REG32(ICDC_CR) | ||
1230 | #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) | ||
1231 | #define REG_ICDC_APPRE REG32(ICDC_APPRE) | ||
1232 | #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) | ||
1233 | #define REG_ICDC_APSR REG32(ICDC_APSR) | ||
1234 | #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) | ||
1235 | #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) | ||
1236 | |||
1237 | /* ICDC Control Register */ | ||
1238 | #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ | ||
1239 | #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) | ||
1240 | #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ | ||
1241 | #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) | ||
1242 | #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) | ||
1243 | #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) | ||
1244 | #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) | ||
1245 | #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) | ||
1246 | #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) | ||
1247 | #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) | ||
1248 | #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) | ||
1249 | #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) | ||
1250 | #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) | ||
1251 | #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ | ||
1252 | #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) | ||
1253 | #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) | ||
1254 | #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) | ||
1255 | #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) | ||
1256 | #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) | ||
1257 | #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ | ||
1258 | #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) | ||
1259 | #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) | ||
1260 | #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) | ||
1261 | #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) | ||
1262 | #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) | ||
1263 | #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ | ||
1264 | #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ | ||
1265 | #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ | ||
1266 | #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ | ||
1267 | #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ | ||
1268 | #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ | ||
1269 | #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ | ||
1270 | #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ | ||
1271 | #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ | ||
1272 | #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ | ||
1273 | #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ | ||
1274 | #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ | ||
1275 | |||
1276 | /* Anti-Pop WAIT Stage Timing Control Register */ | ||
1277 | #define ICDC_APWAIT_WAITSN_BIT 0 | ||
1278 | #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) | ||
1279 | |||
1280 | /* Anti-Pop HPEN-PRE Stage Timing Control Register */ | ||
1281 | #define ICDC_APPRE_PRESN_BIT 0 | ||
1282 | #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) | ||
1283 | |||
1284 | /* Anti-Pop HPEN Stage Timing Control Register */ | ||
1285 | #define ICDC_APHPEN_HPENSN_BIT 0 | ||
1286 | #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) | ||
1287 | |||
1288 | /* Anti-Pop Status Register */ | ||
1289 | #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ | ||
1290 | #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) | ||
1291 | #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ | ||
1292 | #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ | ||
1293 | #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ | ||
1294 | #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ | ||
1295 | #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ | ||
1296 | #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ | ||
1297 | #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ | ||
1298 | #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ | ||
1299 | #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ | ||
1300 | #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) | ||
1301 | |||
1302 | |||
1303 | /************************************************************************* | ||
1304 | * I2C | ||
1305 | *************************************************************************/ | ||
1306 | #define I2C_DR (I2C_BASE + 0x000) | ||
1307 | #define I2C_CR (I2C_BASE + 0x004) | ||
1308 | #define I2C_SR (I2C_BASE + 0x008) | ||
1309 | #define I2C_GR (I2C_BASE + 0x00C) | ||
1310 | |||
1311 | #define REG_I2C_DR REG8(I2C_DR) | ||
1312 | #define REG_I2C_CR REG8(I2C_CR) | ||
1313 | #define REG_I2C_SR REG8(I2C_SR) | ||
1314 | #define REG_I2C_GR REG16(I2C_GR) | ||
1315 | |||
1316 | /* I2C Control Register (I2C_CR) */ | ||
1317 | |||
1318 | #define I2C_CR_IEN (1 << 4) | ||
1319 | #define I2C_CR_STA (1 << 3) | ||
1320 | #define I2C_CR_STO (1 << 2) | ||
1321 | #define I2C_CR_AC (1 << 1) | ||
1322 | #define I2C_CR_I2CE (1 << 0) | ||
1323 | |||
1324 | /* I2C Status Register (I2C_SR) */ | ||
1325 | |||
1326 | #define I2C_SR_STX (1 << 4) | ||
1327 | #define I2C_SR_BUSY (1 << 3) | ||
1328 | #define I2C_SR_TEND (1 << 2) | ||
1329 | #define I2C_SR_DRF (1 << 1) | ||
1330 | #define I2C_SR_ACKF (1 << 0) | ||
1331 | |||
1332 | |||
1333 | /************************************************************************* | ||
1334 | * SSI | ||
1335 | *************************************************************************/ | ||
1336 | #define SSI_DR (SSI_BASE + 0x000) | ||
1337 | #define SSI_CR0 (SSI_BASE + 0x004) | ||
1338 | #define SSI_CR1 (SSI_BASE + 0x008) | ||
1339 | #define SSI_SR (SSI_BASE + 0x00C) | ||
1340 | #define SSI_ITR (SSI_BASE + 0x010) | ||
1341 | #define SSI_ICR (SSI_BASE + 0x014) | ||
1342 | #define SSI_GR (SSI_BASE + 0x018) | ||
1343 | |||
1344 | #define REG_SSI_DR REG32(SSI_DR) | ||
1345 | #define REG_SSI_CR0 REG16(SSI_CR0) | ||
1346 | #define REG_SSI_CR1 REG32(SSI_CR1) | ||
1347 | #define REG_SSI_SR REG32(SSI_SR) | ||
1348 | #define REG_SSI_ITR REG16(SSI_ITR) | ||
1349 | #define REG_SSI_ICR REG8(SSI_ICR) | ||
1350 | #define REG_SSI_GR REG16(SSI_GR) | ||
1351 | |||
1352 | /* SSI Data Register (SSI_DR) */ | ||
1353 | |||
1354 | #define SSI_DR_GPC_BIT 0 | ||
1355 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) | ||
1356 | |||
1357 | /* SSI Control Register 0 (SSI_CR0) */ | ||
1358 | |||
1359 | #define SSI_CR0_SSIE (1 << 15) | ||
1360 | #define SSI_CR0_TIE (1 << 14) | ||
1361 | #define SSI_CR0_RIE (1 << 13) | ||
1362 | #define SSI_CR0_TEIE (1 << 12) | ||
1363 | #define SSI_CR0_REIE (1 << 11) | ||
1364 | #define SSI_CR0_LOOP (1 << 10) | ||
1365 | #define SSI_CR0_RFINE (1 << 9) | ||
1366 | #define SSI_CR0_RFINC (1 << 8) | ||
1367 | #define SSI_CR0_FSEL (1 << 6) | ||
1368 | #define SSI_CR0_TFLUSH (1 << 2) | ||
1369 | #define SSI_CR0_RFLUSH (1 << 1) | ||
1370 | #define SSI_CR0_DISREV (1 << 0) | ||
1371 | |||
1372 | /* SSI Control Register 1 (SSI_CR1) */ | ||
1373 | |||
1374 | #define SSI_CR1_FRMHL_BIT 30 | ||
1375 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) | ||
1376 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ | ||
1377 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ | ||
1378 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ | ||
1379 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ | ||
1380 | #define SSI_CR1_TFVCK_BIT 28 | ||
1381 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) | ||
1382 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) | ||
1383 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) | ||
1384 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) | ||
1385 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) | ||
1386 | #define SSI_CR1_TCKFI_BIT 26 | ||
1387 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) | ||
1388 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) | ||
1389 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) | ||
1390 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) | ||
1391 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) | ||
1392 | #define SSI_CR1_LFST (1 << 25) | ||
1393 | #define SSI_CR1_ITFRM (1 << 24) | ||
1394 | #define SSI_CR1_UNFIN (1 << 23) | ||
1395 | #define SSI_CR1_MULTS (1 << 22) | ||
1396 | #define SSI_CR1_FMAT_BIT 20 | ||
1397 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) | ||
1398 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ | ||
1399 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ | ||
1400 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ | ||
1401 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ | ||
1402 | #define SSI_CR1_TTRG_BIT 16 | ||
1403 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) | ||
1404 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) | ||
1405 | #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) | ||
1406 | #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) | ||
1407 | #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) | ||
1408 | #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) | ||
1409 | #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) | ||
1410 | #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) | ||
1411 | #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) | ||
1412 | #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) | ||
1413 | #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) | ||
1414 | #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) | ||
1415 | #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) | ||
1416 | #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) | ||
1417 | #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) | ||
1418 | #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) | ||
1419 | #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) | ||
1420 | #define SSI_CR1_MCOM_BIT 12 | ||
1421 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) | ||
1422 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ | ||
1423 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ | ||
1424 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ | ||
1425 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ | ||
1426 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ | ||
1427 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ | ||
1428 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ | ||
1429 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ | ||
1430 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ | ||
1431 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ | ||
1432 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ | ||
1433 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ | ||
1434 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ | ||
1435 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ | ||
1436 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ | ||
1437 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ | ||
1438 | #define SSI_CR1_RTRG_BIT 8 | ||
1439 | #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) | ||
1440 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) | ||
1441 | #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) | ||
1442 | #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) | ||
1443 | #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) | ||
1444 | #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) | ||
1445 | #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) | ||
1446 | #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) | ||
1447 | #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) | ||
1448 | #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) | ||
1449 | #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) | ||
1450 | #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) | ||
1451 | #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) | ||
1452 | #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) | ||
1453 | #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) | ||
1454 | #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) | ||
1455 | #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) | ||
1456 | #define SSI_CR1_FLEN_BIT 4 | ||
1457 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) | ||
1458 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) | ||
1459 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) | ||
1460 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) | ||
1461 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) | ||
1462 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) | ||
1463 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) | ||
1464 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) | ||
1465 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) | ||
1466 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) | ||
1467 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) | ||
1468 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) | ||
1469 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) | ||
1470 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) | ||
1471 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) | ||
1472 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) | ||
1473 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) | ||
1474 | #define SSI_CR1_PHA (1 << 1) | ||
1475 | #define SSI_CR1_POL (1 << 0) | ||
1476 | |||
1477 | /* SSI Status Register (SSI_SR) */ | ||
1478 | |||
1479 | #define SSI_SR_TFIFONUM_BIT 16 | ||
1480 | #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) | ||
1481 | #define SSI_SR_RFIFONUM_BIT 8 | ||
1482 | #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) | ||
1483 | #define SSI_SR_END (1 << 7) | ||
1484 | #define SSI_SR_BUSY (1 << 6) | ||
1485 | #define SSI_SR_TFF (1 << 5) | ||
1486 | #define SSI_SR_RFE (1 << 4) | ||
1487 | #define SSI_SR_TFHE (1 << 3) | ||
1488 | #define SSI_SR_RFHF (1 << 2) | ||
1489 | #define SSI_SR_UNDR (1 << 1) | ||
1490 | #define SSI_SR_OVER (1 << 0) | ||
1491 | |||
1492 | /* SSI Interval Time Control Register (SSI_ITR) */ | ||
1493 | |||
1494 | #define SSI_ITR_CNTCLK (1 << 15) | ||
1495 | #define SSI_ITR_IVLTM_BIT 0 | ||
1496 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) | ||
1497 | |||
1498 | |||
1499 | /************************************************************************* | ||
1500 | * MSC | ||
1501 | *************************************************************************/ | ||
1502 | #define MSC_STRPCL (MSC_BASE + 0x000) | ||
1503 | #define MSC_STAT (MSC_BASE + 0x004) | ||
1504 | #define MSC_CLKRT (MSC_BASE + 0x008) | ||
1505 | #define MSC_CMDAT (MSC_BASE + 0x00C) | ||
1506 | #define MSC_RESTO (MSC_BASE + 0x010) | ||
1507 | #define MSC_RDTO (MSC_BASE + 0x014) | ||
1508 | #define MSC_BLKLEN (MSC_BASE + 0x018) | ||
1509 | #define MSC_NOB (MSC_BASE + 0x01C) | ||
1510 | #define MSC_SNOB (MSC_BASE + 0x020) | ||
1511 | #define MSC_IMASK (MSC_BASE + 0x024) | ||
1512 | #define MSC_IREG (MSC_BASE + 0x028) | ||
1513 | #define MSC_CMD (MSC_BASE + 0x02C) | ||
1514 | #define MSC_ARG (MSC_BASE + 0x030) | ||
1515 | #define MSC_RES (MSC_BASE + 0x034) | ||
1516 | #define MSC_RXFIFO (MSC_BASE + 0x038) | ||
1517 | #define MSC_TXFIFO (MSC_BASE + 0x03C) | ||
1518 | |||
1519 | #define REG_MSC_STRPCL REG16(MSC_STRPCL) | ||
1520 | #define REG_MSC_STAT REG32(MSC_STAT) | ||
1521 | #define REG_MSC_CLKRT REG16(MSC_CLKRT) | ||
1522 | #define REG_MSC_CMDAT REG32(MSC_CMDAT) | ||
1523 | #define REG_MSC_RESTO REG16(MSC_RESTO) | ||
1524 | #define REG_MSC_RDTO REG16(MSC_RDTO) | ||
1525 | #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) | ||
1526 | #define REG_MSC_NOB REG16(MSC_NOB) | ||
1527 | #define REG_MSC_SNOB REG16(MSC_SNOB) | ||
1528 | #define REG_MSC_IMASK REG16(MSC_IMASK) | ||
1529 | #define REG_MSC_IREG REG16(MSC_IREG) | ||
1530 | #define REG_MSC_CMD REG8(MSC_CMD) | ||
1531 | #define REG_MSC_ARG REG32(MSC_ARG) | ||
1532 | #define REG_MSC_RES REG16(MSC_RES) | ||
1533 | #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) | ||
1534 | #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) | ||
1535 | |||
1536 | /* MSC Clock and Control Register (MSC_STRPCL) */ | ||
1537 | |||
1538 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) | ||
1539 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) | ||
1540 | #define MSC_STRPCL_START_READWAIT (1 << 5) | ||
1541 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) | ||
1542 | #define MSC_STRPCL_RESET (1 << 3) | ||
1543 | #define MSC_STRPCL_START_OP (1 << 2) | ||
1544 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 | ||
1545 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) | ||
1546 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ | ||
1547 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ | ||
1548 | |||
1549 | /* MSC Status Register (MSC_STAT) */ | ||
1550 | |||
1551 | #define MSC_STAT_IS_RESETTING (1 << 15) | ||
1552 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) | ||
1553 | #define MSC_STAT_PRG_DONE (1 << 13) | ||
1554 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) | ||
1555 | #define MSC_STAT_END_CMD_RES (1 << 11) | ||
1556 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) | ||
1557 | #define MSC_STAT_IS_READWAIT (1 << 9) | ||
1558 | #define MSC_STAT_CLK_EN (1 << 8) | ||
1559 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) | ||
1560 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) | ||
1561 | #define MSC_STAT_CRC_RES_ERR (1 << 5) | ||
1562 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) | ||
1563 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 | ||
1564 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) | ||
1565 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ | ||
1566 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ | ||
1567 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ | ||
1568 | #define MSC_STAT_TIME_OUT_RES (1 << 1) | ||
1569 | #define MSC_STAT_TIME_OUT_READ (1 << 0) | ||
1570 | |||
1571 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ | ||
1572 | |||
1573 | #define MSC_CLKRT_CLK_RATE_BIT 0 | ||
1574 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) | ||
1575 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ | ||
1576 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ | ||
1577 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ | ||
1578 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ | ||
1579 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ | ||
1580 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ | ||
1581 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ | ||
1582 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ | ||
1583 | |||
1584 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ | ||
1585 | |||
1586 | #define MSC_CMDAT_IO_ABORT (1 << 11) | ||
1587 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 | ||
1588 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) | ||
1589 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ | ||
1590 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ | ||
1591 | #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) | ||
1592 | #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) | ||
1593 | #define MSC_CMDAT_DMA_EN (1 << 8) | ||
1594 | #define MSC_CMDAT_INIT (1 << 7) | ||
1595 | #define MSC_CMDAT_BUSY (1 << 6) | ||
1596 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) | ||
1597 | #define MSC_CMDAT_WRITE (1 << 4) | ||
1598 | #define MSC_CMDAT_READ (0 << 4) | ||
1599 | #define MSC_CMDAT_DATA_EN (1 << 3) | ||
1600 | #define MSC_CMDAT_RESPONSE_BIT 0 | ||
1601 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) | ||
1602 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ | ||
1603 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ | ||
1604 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ | ||
1605 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ | ||
1606 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ | ||
1607 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ | ||
1608 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ | ||
1609 | |||
1610 | #define CMDAT_DMA_EN (1 << 8) | ||
1611 | #define CMDAT_INIT (1 << 7) | ||
1612 | #define CMDAT_BUSY (1 << 6) | ||
1613 | #define CMDAT_STREAM (1 << 5) | ||
1614 | #define CMDAT_WRITE (1 << 4) | ||
1615 | #define CMDAT_DATA_EN (1 << 3) | ||
1616 | |||
1617 | /* MSC Interrupts Mask Register (MSC_IMASK) */ | ||
1618 | |||
1619 | #define MSC_IMASK_SDIO (1 << 7) | ||
1620 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) | ||
1621 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) | ||
1622 | #define MSC_IMASK_END_CMD_RES (1 << 2) | ||
1623 | #define MSC_IMASK_PRG_DONE (1 << 1) | ||
1624 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) | ||
1625 | |||
1626 | |||
1627 | /* MSC Interrupts Status Register (MSC_IREG) */ | ||
1628 | |||
1629 | #define MSC_IREG_SDIO (1 << 7) | ||
1630 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) | ||
1631 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) | ||
1632 | #define MSC_IREG_END_CMD_RES (1 << 2) | ||
1633 | #define MSC_IREG_PRG_DONE (1 << 1) | ||
1634 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) | ||
1635 | |||
1636 | |||
1637 | /************************************************************************* | ||
1638 | * EMC (External Memory Controller) | ||
1639 | *************************************************************************/ | ||
1640 | #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ | ||
1641 | |||
1642 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ | ||
1643 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ | ||
1644 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ | ||
1645 | #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ | ||
1646 | #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ | ||
1647 | #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ | ||
1648 | #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ | ||
1649 | #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ | ||
1650 | #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ | ||
1651 | #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ | ||
1652 | |||
1653 | #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ | ||
1654 | #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ | ||
1655 | #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ | ||
1656 | #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ | ||
1657 | #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ | ||
1658 | #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ | ||
1659 | #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ | ||
1660 | #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ | ||
1661 | #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ | ||
1662 | #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ | ||
1663 | #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ | ||
1664 | #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ | ||
1665 | |||
1666 | #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ | ||
1667 | #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ | ||
1668 | #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ | ||
1669 | #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ | ||
1670 | #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ | ||
1671 | #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ | ||
1672 | |||
1673 | #define REG_EMC_BCR REG32(EMC_BCR) | ||
1674 | |||
1675 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) | ||
1676 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) | ||
1677 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) | ||
1678 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) | ||
1679 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) | ||
1680 | #define REG_EMC_SACR0 REG32(EMC_SACR0) | ||
1681 | #define REG_EMC_SACR1 REG32(EMC_SACR1) | ||
1682 | #define REG_EMC_SACR2 REG32(EMC_SACR2) | ||
1683 | #define REG_EMC_SACR3 REG32(EMC_SACR3) | ||
1684 | #define REG_EMC_SACR4 REG32(EMC_SACR4) | ||
1685 | |||
1686 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) | ||
1687 | #define REG_EMC_NFECR REG32(EMC_NFECR) | ||
1688 | #define REG_EMC_NFECC REG32(EMC_NFECC) | ||
1689 | #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) | ||
1690 | #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) | ||
1691 | #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) | ||
1692 | #define REG_EMC_NFINTS REG32(EMC_NFINTS) | ||
1693 | #define REG_EMC_NFINTE REG32(EMC_NFINTE) | ||
1694 | #define REG_EMC_NFERR0 REG32(EMC_NFERR0) | ||
1695 | #define REG_EMC_NFERR1 REG32(EMC_NFERR1) | ||
1696 | #define REG_EMC_NFERR2 REG32(EMC_NFERR2) | ||
1697 | #define REG_EMC_NFERR3 REG32(EMC_NFERR3) | ||
1698 | |||
1699 | #define REG_EMC_DMCR REG32(EMC_DMCR) | ||
1700 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) | ||
1701 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) | ||
1702 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) | ||
1703 | #define REG_EMC_DMAR0 REG32(EMC_DMAR0) | ||
1704 | |||
1705 | /* Static Memory Control Register */ | ||
1706 | #define EMC_SMCR_STRV_BIT 24 | ||
1707 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) | ||
1708 | #define EMC_SMCR_TAW_BIT 20 | ||
1709 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) | ||
1710 | #define EMC_SMCR_TBP_BIT 16 | ||
1711 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) | ||
1712 | #define EMC_SMCR_TAH_BIT 12 | ||
1713 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) | ||
1714 | #define EMC_SMCR_TAS_BIT 8 | ||
1715 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) | ||
1716 | #define EMC_SMCR_BW_BIT 6 | ||
1717 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) | ||
1718 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) | ||
1719 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) | ||
1720 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) | ||
1721 | #define EMC_SMCR_BCM (1 << 3) | ||
1722 | #define EMC_SMCR_BL_BIT 1 | ||
1723 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) | ||
1724 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) | ||
1725 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) | ||
1726 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) | ||
1727 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) | ||
1728 | #define EMC_SMCR_SMT (1 << 0) | ||
1729 | |||
1730 | /* Static Memory Bank Addr Config Reg */ | ||
1731 | #define EMC_SACR_BASE_BIT 8 | ||
1732 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) | ||
1733 | #define EMC_SACR_MASK_BIT 0 | ||
1734 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) | ||
1735 | |||
1736 | /* NAND Flash Control/Status Register */ | ||
1737 | #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ | ||
1738 | #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ | ||
1739 | #define EMC_NFCSR_NFCE3 (1 << 5) | ||
1740 | #define EMC_NFCSR_NFE3 (1 << 4) | ||
1741 | #define EMC_NFCSR_NFCE2 (1 << 3) | ||
1742 | #define EMC_NFCSR_NFE2 (1 << 2) | ||
1743 | #define EMC_NFCSR_NFCE1 (1 << 1) | ||
1744 | #define EMC_NFCSR_NFE1 (1 << 0) | ||
1745 | |||
1746 | /* NAND Flash ECC Control Register */ | ||
1747 | #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ | ||
1748 | #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ | ||
1749 | #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ | ||
1750 | #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ | ||
1751 | #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ | ||
1752 | #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ | ||
1753 | #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ | ||
1754 | |||
1755 | /* NAND Flash ECC Data Register */ | ||
1756 | #define EMC_NFECC_ECC2_BIT 16 | ||
1757 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) | ||
1758 | #define EMC_NFECC_ECC1_BIT 8 | ||
1759 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) | ||
1760 | #define EMC_NFECC_ECC0_BIT 0 | ||
1761 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) | ||
1762 | |||
1763 | /* NAND Flash Interrupt Status Register */ | ||
1764 | #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ | ||
1765 | #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) | ||
1766 | #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ | ||
1767 | #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ | ||
1768 | #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ | ||
1769 | #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ | ||
1770 | #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ | ||
1771 | |||
1772 | /* NAND Flash Interrupt Enable Register */ | ||
1773 | #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ | ||
1774 | #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ | ||
1775 | #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ | ||
1776 | #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ | ||
1777 | #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ | ||
1778 | |||
1779 | /* NAND Flash RS Error Report Register */ | ||
1780 | #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ | ||
1781 | #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) | ||
1782 | #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ | ||
1783 | #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) | ||
1784 | |||
1785 | |||
1786 | /* DRAM Control Register */ | ||
1787 | #define EMC_DMCR_BW_BIT 31 | ||
1788 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) | ||
1789 | #define EMC_DMCR_CA_BIT 26 | ||
1790 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) | ||
1791 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) | ||
1792 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) | ||
1793 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) | ||
1794 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) | ||
1795 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) | ||
1796 | #define EMC_DMCR_RMODE (1 << 25) | ||
1797 | #define EMC_DMCR_RFSH (1 << 24) | ||
1798 | #define EMC_DMCR_MRSET (1 << 23) | ||
1799 | #define EMC_DMCR_RA_BIT 20 | ||
1800 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) | ||
1801 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) | ||
1802 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) | ||
1803 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) | ||
1804 | #define EMC_DMCR_BA_BIT 19 | ||
1805 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) | ||
1806 | #define EMC_DMCR_PDM (1 << 18) | ||
1807 | #define EMC_DMCR_EPIN (1 << 17) | ||
1808 | #define EMC_DMCR_TRAS_BIT 13 | ||
1809 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) | ||
1810 | #define EMC_DMCR_RCD_BIT 11 | ||
1811 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) | ||
1812 | #define EMC_DMCR_TPC_BIT 8 | ||
1813 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) | ||
1814 | #define EMC_DMCR_TRWL_BIT 5 | ||
1815 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) | ||
1816 | #define EMC_DMCR_TRC_BIT 2 | ||
1817 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) | ||
1818 | #define EMC_DMCR_TCL_BIT 0 | ||
1819 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) | ||
1820 | |||
1821 | /* Refresh Time Control/Status Register */ | ||
1822 | #define EMC_RTCSR_CMF (1 << 7) | ||
1823 | #define EMC_RTCSR_CKS_BIT 0 | ||
1824 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) | ||
1825 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) | ||
1826 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) | ||
1827 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) | ||
1828 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) | ||
1829 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) | ||
1830 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) | ||
1831 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) | ||
1832 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) | ||
1833 | |||
1834 | /* SDRAM Bank Address Configuration Register */ | ||
1835 | #define EMC_DMAR_BASE_BIT 8 | ||
1836 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) | ||
1837 | #define EMC_DMAR_MASK_BIT 0 | ||
1838 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) | ||
1839 | |||
1840 | /* Mode Register of SDRAM bank 0 */ | ||
1841 | #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ | ||
1842 | #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ | ||
1843 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) | ||
1844 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) | ||
1845 | #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ | ||
1846 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) | ||
1847 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) | ||
1848 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) | ||
1849 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) | ||
1850 | #define EMC_SDMR_BT_BIT 3 /* Burst Type */ | ||
1851 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) | ||
1852 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ | ||
1853 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ | ||
1854 | #define EMC_SDMR_BL_BIT 0 /* Burst Length */ | ||
1855 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) | ||
1856 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) | ||
1857 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) | ||
1858 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) | ||
1859 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) | ||
1860 | |||
1861 | #define EMC_SDMR_CAS2_16BIT \ | ||
1862 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) | ||
1863 | #define EMC_SDMR_CAS2_32BIT \ | ||
1864 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) | ||
1865 | #define EMC_SDMR_CAS3_16BIT \ | ||
1866 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) | ||
1867 | #define EMC_SDMR_CAS3_32BIT \ | ||
1868 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) | ||
1869 | |||
1870 | |||
1871 | /************************************************************************* | ||
1872 | * CIM | ||
1873 | *************************************************************************/ | ||
1874 | #define CIM_CFG (CIM_BASE + 0x0000) | ||
1875 | #define CIM_CTRL (CIM_BASE + 0x0004) | ||
1876 | #define CIM_STATE (CIM_BASE + 0x0008) | ||
1877 | #define CIM_IID (CIM_BASE + 0x000C) | ||
1878 | #define CIM_RXFIFO (CIM_BASE + 0x0010) | ||
1879 | #define CIM_DA (CIM_BASE + 0x0020) | ||
1880 | #define CIM_FA (CIM_BASE + 0x0024) | ||
1881 | #define CIM_FID (CIM_BASE + 0x0028) | ||
1882 | #define CIM_CMD (CIM_BASE + 0x002C) | ||
1883 | |||
1884 | #define REG_CIM_CFG REG32(CIM_CFG) | ||
1885 | #define REG_CIM_CTRL REG32(CIM_CTRL) | ||
1886 | #define REG_CIM_STATE REG32(CIM_STATE) | ||
1887 | #define REG_CIM_IID REG32(CIM_IID) | ||
1888 | #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) | ||
1889 | #define REG_CIM_DA REG32(CIM_DA) | ||
1890 | #define REG_CIM_FA REG32(CIM_FA) | ||
1891 | #define REG_CIM_FID REG32(CIM_FID) | ||
1892 | #define REG_CIM_CMD REG32(CIM_CMD) | ||
1893 | |||
1894 | /* CIM Configuration Register (CIM_CFG) */ | ||
1895 | |||
1896 | #define CIM_CFG_INV_DAT (1 << 15) | ||
1897 | #define CIM_CFG_VSP (1 << 14) | ||
1898 | #define CIM_CFG_HSP (1 << 13) | ||
1899 | #define CIM_CFG_PCP (1 << 12) | ||
1900 | #define CIM_CFG_DUMMY_ZERO (1 << 9) | ||
1901 | #define CIM_CFG_EXT_VSYNC (1 << 8) | ||
1902 | #define CIM_CFG_PACK_BIT 4 | ||
1903 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) | ||
1904 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) | ||
1905 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) | ||
1906 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) | ||
1907 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) | ||
1908 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) | ||
1909 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) | ||
1910 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) | ||
1911 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) | ||
1912 | #define CIM_CFG_DSM_BIT 0 | ||
1913 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) | ||
1914 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ | ||
1915 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ | ||
1916 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ | ||
1917 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ | ||
1918 | |||
1919 | /* CIM Control Register (CIM_CTRL) */ | ||
1920 | |||
1921 | #define CIM_CTRL_MCLKDIV_BIT 24 | ||
1922 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) | ||
1923 | #define CIM_CTRL_FRC_BIT 16 | ||
1924 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) | ||
1925 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ | ||
1926 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ | ||
1927 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ | ||
1928 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ | ||
1929 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ | ||
1930 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ | ||
1931 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ | ||
1932 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ | ||
1933 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ | ||
1934 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ | ||
1935 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ | ||
1936 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ | ||
1937 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ | ||
1938 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ | ||
1939 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ | ||
1940 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ | ||
1941 | #define CIM_CTRL_VDDM (1 << 13) | ||
1942 | #define CIM_CTRL_DMA_SOFM (1 << 12) | ||
1943 | #define CIM_CTRL_DMA_EOFM (1 << 11) | ||
1944 | #define CIM_CTRL_DMA_STOPM (1 << 10) | ||
1945 | #define CIM_CTRL_RXF_TRIGM (1 << 9) | ||
1946 | #define CIM_CTRL_RXF_OFM (1 << 8) | ||
1947 | #define CIM_CTRL_RXF_TRIG_BIT 4 | ||
1948 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) | ||
1949 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ | ||
1950 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ | ||
1951 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ | ||
1952 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ | ||
1953 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ | ||
1954 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ | ||
1955 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ | ||
1956 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ | ||
1957 | #define CIM_CTRL_DMA_EN (1 << 2) | ||
1958 | #define CIM_CTRL_RXF_RST (1 << 1) | ||
1959 | #define CIM_CTRL_ENA (1 << 0) | ||
1960 | |||
1961 | /* CIM State Register (CIM_STATE) */ | ||
1962 | |||
1963 | #define CIM_STATE_DMA_SOF (1 << 6) | ||
1964 | #define CIM_STATE_DMA_EOF (1 << 5) | ||
1965 | #define CIM_STATE_DMA_STOP (1 << 4) | ||
1966 | #define CIM_STATE_RXF_OF (1 << 3) | ||
1967 | #define CIM_STATE_RXF_TRIG (1 << 2) | ||
1968 | #define CIM_STATE_RXF_EMPTY (1 << 1) | ||
1969 | #define CIM_STATE_VDD (1 << 0) | ||
1970 | |||
1971 | /* CIM DMA Command Register (CIM_CMD) */ | ||
1972 | |||
1973 | #define CIM_CMD_SOFINT (1 << 31) | ||
1974 | #define CIM_CMD_EOFINT (1 << 30) | ||
1975 | #define CIM_CMD_STOP (1 << 28) | ||
1976 | #define CIM_CMD_LEN_BIT 0 | ||
1977 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) | ||
1978 | |||
1979 | |||
1980 | /************************************************************************* | ||
1981 | * SADC (Smart A/D Controller) | ||
1982 | *************************************************************************/ | ||
1983 | |||
1984 | #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ | ||
1985 | #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ | ||
1986 | #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ | ||
1987 | #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ | ||
1988 | #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ | ||
1989 | #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ | ||
1990 | #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ | ||
1991 | #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ | ||
1992 | #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ | ||
1993 | |||
1994 | #define REG_SADC_ENA REG8(SADC_ENA) | ||
1995 | #define REG_SADC_CFG REG32(SADC_CFG) | ||
1996 | #define REG_SADC_CTRL REG8(SADC_CTRL) | ||
1997 | #define REG_SADC_STATE REG8(SADC_STATE) | ||
1998 | #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) | ||
1999 | #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) | ||
2000 | #define REG_SADC_TSDAT REG32(SADC_TSDAT) | ||
2001 | #define REG_SADC_BATDAT REG16(SADC_BATDAT) | ||
2002 | #define REG_SADC_SADDAT REG16(SADC_SADDAT) | ||
2003 | |||
2004 | /* ADC Enable Register */ | ||
2005 | #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ | ||
2006 | #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ | ||
2007 | #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ | ||
2008 | #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ | ||
2009 | |||
2010 | /* ADC Configure Register */ | ||
2011 | #define SADC_CFG_CLKOUT_NUM_BIT 16 | ||
2012 | #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) | ||
2013 | #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ | ||
2014 | #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ | ||
2015 | #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) | ||
2016 | #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) | ||
2017 | #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) | ||
2018 | #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) | ||
2019 | #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ | ||
2020 | #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) | ||
2021 | #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) | ||
2022 | #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) | ||
2023 | #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) | ||
2024 | #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) | ||
2025 | #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) | ||
2026 | #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) | ||
2027 | #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) | ||
2028 | #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) | ||
2029 | #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ | ||
2030 | #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) | ||
2031 | #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ | ||
2032 | #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ | ||
2033 | #define SADC_CFG_CMD_BIT 0 /* ADC Command */ | ||
2034 | #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) | ||
2035 | #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ | ||
2036 | #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ | ||
2037 | #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ | ||
2038 | #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ | ||
2039 | #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ | ||
2040 | #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ | ||
2041 | #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ | ||
2042 | #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ | ||
2043 | #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ | ||
2044 | #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ | ||
2045 | #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ | ||
2046 | #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ | ||
2047 | #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ | ||
2048 | |||
2049 | /* ADC Control Register */ | ||
2050 | #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ | ||
2051 | #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ | ||
2052 | #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ | ||
2053 | #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ | ||
2054 | #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ | ||
2055 | |||
2056 | /* ADC Status Register */ | ||
2057 | #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ | ||
2058 | #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ | ||
2059 | #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ | ||
2060 | #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ | ||
2061 | #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ | ||
2062 | #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ | ||
2063 | #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ | ||
2064 | #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ | ||
2065 | |||
2066 | /* ADC Touch Screen Data Register */ | ||
2067 | #define SADC_TSDAT_DATA0_BIT 0 | ||
2068 | #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) | ||
2069 | #define SADC_TSDAT_TYPE0 (1 << 15) | ||
2070 | #define SADC_TSDAT_DATA1_BIT 16 | ||
2071 | #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) | ||
2072 | #define SADC_TSDAT_TYPE1 (1 << 31) | ||
2073 | |||
2074 | |||
2075 | /************************************************************************* | ||
2076 | * SLCD (Smart LCD Controller) | ||
2077 | *************************************************************************/ | ||
2078 | |||
2079 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ | ||
2080 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ | ||
2081 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ | ||
2082 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ | ||
2083 | #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ | ||
2084 | |||
2085 | #define REG_SLCD_CFG REG32(SLCD_CFG) | ||
2086 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) | ||
2087 | #define REG_SLCD_STATE REG8(SLCD_STATE) | ||
2088 | #define REG_SLCD_DATA REG32(SLCD_DATA) | ||
2089 | #define REG_SLCD_FIFO REG32(SLCD_FIFO) | ||
2090 | |||
2091 | /* SLCD Configure Register */ | ||
2092 | #define SLCD_CFG_BURST_BIT 14 | ||
2093 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) | ||
2094 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) | ||
2095 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) | ||
2096 | #define SLCD_CFG_DWIDTH_BIT 10 | ||
2097 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) | ||
2098 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) | ||
2099 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) | ||
2100 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) | ||
2101 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) | ||
2102 | #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) | ||
2103 | #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) | ||
2104 | #define SLCD_CFG_CWIDTH_BIT 8 | ||
2105 | #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) | ||
2106 | #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) | ||
2107 | #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) | ||
2108 | #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) | ||
2109 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) | ||
2110 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) | ||
2111 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) | ||
2112 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) | ||
2113 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) | ||
2114 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) | ||
2115 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) | ||
2116 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) | ||
2117 | |||
2118 | /* SLCD Control Register */ | ||
2119 | #define SLCD_CTRL_DMA_EN (1 << 0) | ||
2120 | |||
2121 | /* SLCD Status Register */ | ||
2122 | #define SLCD_STATE_BUSY (1 << 0) | ||
2123 | |||
2124 | /* SLCD Data Register */ | ||
2125 | #define SLCD_DATA_RS_DATA (0 << 31) | ||
2126 | #define SLCD_DATA_RS_COMMAND (1 << 31) | ||
2127 | |||
2128 | /* SLCD FIFO Register */ | ||
2129 | #define SLCD_FIFO_RS_DATA (0 << 31) | ||
2130 | #define SLCD_FIFO_RS_COMMAND (1 << 31) | ||
2131 | |||
2132 | |||
2133 | /************************************************************************* | ||
2134 | * LCD (LCD Controller) | ||
2135 | *************************************************************************/ | ||
2136 | #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ | ||
2137 | #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ | ||
2138 | #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ | ||
2139 | #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ | ||
2140 | #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ | ||
2141 | #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ | ||
2142 | #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ | ||
2143 | #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ | ||
2144 | #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ | ||
2145 | #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ | ||
2146 | #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ | ||
2147 | #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ | ||
2148 | #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ | ||
2149 | #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ | ||
2150 | #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ | ||
2151 | #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ | ||
2152 | #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ | ||
2153 | #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ | ||
2154 | #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ | ||
2155 | #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ | ||
2156 | #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ | ||
2157 | |||
2158 | #define REG_LCD_CFG REG32(LCD_CFG) | ||
2159 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) | ||
2160 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) | ||
2161 | #define REG_LCD_VAT REG32(LCD_VAT) | ||
2162 | #define REG_LCD_DAH REG32(LCD_DAH) | ||
2163 | #define REG_LCD_DAV REG32(LCD_DAV) | ||
2164 | #define REG_LCD_PS REG32(LCD_PS) | ||
2165 | #define REG_LCD_CLS REG32(LCD_CLS) | ||
2166 | #define REG_LCD_SPL REG32(LCD_SPL) | ||
2167 | #define REG_LCD_REV REG32(LCD_REV) | ||
2168 | #define REG_LCD_CTRL REG32(LCD_CTRL) | ||
2169 | #define REG_LCD_STATE REG32(LCD_STATE) | ||
2170 | #define REG_LCD_IID REG32(LCD_IID) | ||
2171 | #define REG_LCD_DA0 REG32(LCD_DA0) | ||
2172 | #define REG_LCD_SA0 REG32(LCD_SA0) | ||
2173 | #define REG_LCD_FID0 REG32(LCD_FID0) | ||
2174 | #define REG_LCD_CMD0 REG32(LCD_CMD0) | ||
2175 | #define REG_LCD_DA1 REG32(LCD_DA1) | ||
2176 | #define REG_LCD_SA1 REG32(LCD_SA1) | ||
2177 | #define REG_LCD_FID1 REG32(LCD_FID1) | ||
2178 | #define REG_LCD_CMD1 REG32(LCD_CMD1) | ||
2179 | |||
2180 | /* LCD Configure Register */ | ||
2181 | #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ | ||
2182 | #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) | ||
2183 | #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) | ||
2184 | #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) | ||
2185 | #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ | ||
2186 | #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ | ||
2187 | #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ | ||
2188 | #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ | ||
2189 | #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ | ||
2190 | #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ | ||
2191 | #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ | ||
2192 | #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ | ||
2193 | #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ | ||
2194 | #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ | ||
2195 | #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ | ||
2196 | #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ | ||
2197 | #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ | ||
2198 | #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ | ||
2199 | #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ | ||
2200 | #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ | ||
2201 | #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ | ||
2202 | #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) | ||
2203 | #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ | ||
2204 | #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ | ||
2205 | #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ | ||
2206 | #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ | ||
2207 | #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ | ||
2208 | #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) | ||
2209 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ | ||
2210 | #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) | ||
2211 | #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) | ||
2212 | #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) | ||
2213 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) | ||
2214 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) | ||
2215 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) | ||
2216 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) | ||
2217 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) | ||
2218 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) | ||
2219 | #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) | ||
2220 | #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) | ||
2221 | /* JZ47XX defines */ | ||
2222 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) | ||
2223 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) | ||
2224 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) | ||
2225 | |||
2226 | |||
2227 | |||
2228 | /* Vertical Synchronize Register */ | ||
2229 | #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ | ||
2230 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) | ||
2231 | #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ | ||
2232 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) | ||
2233 | |||
2234 | /* Horizontal Synchronize Register */ | ||
2235 | #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ | ||
2236 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) | ||
2237 | #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ | ||
2238 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) | ||
2239 | |||
2240 | /* Virtual Area Setting Register */ | ||
2241 | #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ | ||
2242 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) | ||
2243 | #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ | ||
2244 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) | ||
2245 | |||
2246 | /* Display Area Horizontal Start/End Point Register */ | ||
2247 | #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ | ||
2248 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) | ||
2249 | #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ | ||
2250 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) | ||
2251 | |||
2252 | /* Display Area Vertical Start/End Point Register */ | ||
2253 | #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ | ||
2254 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) | ||
2255 | #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ | ||
2256 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) | ||
2257 | |||
2258 | /* PS Signal Setting */ | ||
2259 | #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ | ||
2260 | #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) | ||
2261 | #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ | ||
2262 | #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) | ||
2263 | |||
2264 | /* CLS Signal Setting */ | ||
2265 | #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ | ||
2266 | #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) | ||
2267 | #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ | ||
2268 | #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) | ||
2269 | |||
2270 | /* SPL Signal Setting */ | ||
2271 | #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ | ||
2272 | #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) | ||
2273 | #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ | ||
2274 | #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) | ||
2275 | |||
2276 | /* REV Signal Setting */ | ||
2277 | #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ | ||
2278 | #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) | ||
2279 | |||
2280 | /* LCD Control Register */ | ||
2281 | #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ | ||
2282 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) | ||
2283 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ | ||
2284 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ | ||
2285 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ | ||
2286 | #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ | ||
2287 | #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ | ||
2288 | #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ | ||
2289 | #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ | ||
2290 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) | ||
2291 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ | ||
2292 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ | ||
2293 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ | ||
2294 | #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ | ||
2295 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) | ||
2296 | #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ | ||
2297 | #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ | ||
2298 | #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ | ||
2299 | #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ | ||
2300 | #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ | ||
2301 | #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ | ||
2302 | #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ | ||
2303 | #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ | ||
2304 | #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ | ||
2305 | #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ | ||
2306 | #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ | ||
2307 | #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ | ||
2308 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) | ||
2309 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ | ||
2310 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ | ||
2311 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ | ||
2312 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ | ||
2313 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ | ||
2314 | #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ | ||
2315 | |||
2316 | /* LCD Status Register */ | ||
2317 | #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ | ||
2318 | #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ | ||
2319 | #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ | ||
2320 | #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ | ||
2321 | #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ | ||
2322 | #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ | ||
2323 | #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ | ||
2324 | |||
2325 | /* DMA Command Register */ | ||
2326 | #define LCD_CMD_SOFINT (1 << 31) | ||
2327 | #define LCD_CMD_EOFINT (1 << 30) | ||
2328 | #define LCD_CMD_PAL (1 << 28) | ||
2329 | #define LCD_CMD_LEN_BIT 0 | ||
2330 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) | ||
2331 | |||
2332 | |||
2333 | /************************************************************************* | ||
2334 | * USB Device | ||
2335 | *************************************************************************/ | ||
2336 | #define USB_BASE UDC_BASE | ||
2337 | |||
2338 | #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ | ||
2339 | #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ | ||
2340 | #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ | ||
2341 | #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ | ||
2342 | #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ | ||
2343 | #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ | ||
2344 | #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ | ||
2345 | #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ | ||
2346 | #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ | ||
2347 | #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ | ||
2348 | #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ | ||
2349 | |||
2350 | #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ | ||
2351 | #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ | ||
2352 | #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ | ||
2353 | #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ | ||
2354 | #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ | ||
2355 | #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ | ||
2356 | #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ | ||
2357 | #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ | ||
2358 | |||
2359 | #define USB_FIFO_EP0 (USB_BASE + 0x20) | ||
2360 | #define USB_FIFO_EP1 (USB_BASE + 0x24) | ||
2361 | #define USB_FIFO_EP2 (USB_BASE + 0x28) | ||
2362 | |||
2363 | #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ | ||
2364 | #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ | ||
2365 | |||
2366 | #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ | ||
2367 | #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ | ||
2368 | #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ | ||
2369 | #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ | ||
2370 | #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ | ||
2371 | #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ | ||
2372 | #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ | ||
2373 | |||
2374 | |||
2375 | /* Power register bit masks */ | ||
2376 | #define USB_POWER_SUSPENDM 0x01 | ||
2377 | #define USB_POWER_RESUME 0x04 | ||
2378 | #define USB_POWER_HSMODE 0x10 | ||
2379 | #define USB_POWER_HSENAB 0x20 | ||
2380 | #define USB_POWER_SOFTCONN 0x40 | ||
2381 | |||
2382 | /* Interrupt register bit masks */ | ||
2383 | #define USB_INTR_SUSPEND 0x01 | ||
2384 | #define USB_INTR_RESUME 0x02 | ||
2385 | #define USB_INTR_RESET 0x04 | ||
2386 | |||
2387 | #define USB_INTR_EP0 0x0001 | ||
2388 | #define USB_INTR_INEP1 0x0002 | ||
2389 | #define USB_INTR_INEP2 0x0004 | ||
2390 | #define USB_INTR_OUTEP1 0x0002 | ||
2391 | |||
2392 | /* CSR0 bit masks */ | ||
2393 | #define USB_CSR0_OUTPKTRDY 0x01 | ||
2394 | #define USB_CSR0_INPKTRDY 0x02 | ||
2395 | #define USB_CSR0_SENTSTALL 0x04 | ||
2396 | #define USB_CSR0_DATAEND 0x08 | ||
2397 | #define USB_CSR0_SETUPEND 0x10 | ||
2398 | #define USB_CSR0_SENDSTALL 0x20 | ||
2399 | #define USB_CSR0_SVDOUTPKTRDY 0x40 | ||
2400 | #define USB_CSR0_SVDSETUPEND 0x80 | ||
2401 | |||
2402 | /* Endpoint CSR register bits */ | ||
2403 | #define USB_INCSRH_AUTOSET 0x80 | ||
2404 | #define USB_INCSRH_ISO 0x40 | ||
2405 | #define USB_INCSRH_MODE 0x20 | ||
2406 | #define USB_INCSRH_DMAREQENAB 0x10 | ||
2407 | #define USB_INCSRH_DMAREQMODE 0x04 | ||
2408 | #define USB_INCSR_CDT 0x40 | ||
2409 | #define USB_INCSR_SENTSTALL 0x20 | ||
2410 | #define USB_INCSR_SENDSTALL 0x10 | ||
2411 | #define USB_INCSR_FF 0x08 | ||
2412 | #define USB_INCSR_UNDERRUN 0x04 | ||
2413 | #define USB_INCSR_FFNOTEMPT 0x02 | ||
2414 | #define USB_INCSR_INPKTRDY 0x01 | ||
2415 | #define USB_OUTCSRH_AUTOCLR 0x80 | ||
2416 | #define USB_OUTCSRH_ISO 0x40 | ||
2417 | #define USB_OUTCSRH_DMAREQENAB 0x20 | ||
2418 | #define USB_OUTCSRH_DNYT 0x10 | ||
2419 | #define USB_OUTCSRH_DMAREQMODE 0x08 | ||
2420 | #define USB_OUTCSR_CDT 0x80 | ||
2421 | #define USB_OUTCSR_SENTSTALL 0x40 | ||
2422 | #define USB_OUTCSR_SENDSTALL 0x20 | ||
2423 | #define USB_OUTCSR_FF 0x10 | ||
2424 | #define USB_OUTCSR_DATAERR 0x08 | ||
2425 | #define USB_OUTCSR_OVERRUN 0x04 | ||
2426 | #define USB_OUTCSR_FFFULL 0x02 | ||
2427 | #define USB_OUTCSR_OUTPKTRDY 0x01 | ||
2428 | |||
2429 | /* Testmode register bits */ | ||
2430 | #define USB_TEST_SE0NAK 0x01 | ||
2431 | #define USB_TEST_J 0x02 | ||
2432 | #define USB_TEST_K 0x04 | ||
2433 | #define USB_TEST_PACKET 0x08 | ||
2434 | |||
2435 | /* DMA control bits */ | ||
2436 | #define USB_CNTL_ENA 0x01 | ||
2437 | #define USB_CNTL_DIR_IN 0x02 | ||
2438 | #define USB_CNTL_MODE_1 0x04 | ||
2439 | #define USB_CNTL_INTR_EN 0x08 | ||
2440 | #define USB_CNTL_EP(n) ((n) << 4) | ||
2441 | #define USB_CNTL_BURST_0 (0 << 9) | ||
2442 | #define USB_CNTL_BURST_4 (1 << 9) | ||
2443 | #define USB_CNTL_BURST_8 (2 << 9) | ||
2444 | #define USB_CNTL_BURST_16 (3 << 9) | ||
2445 | |||
2446 | |||
2447 | //---------------------------------------------------------------------- | ||
2448 | // | ||
2449 | // Module Operation Definitions | ||
2450 | // | ||
2451 | //---------------------------------------------------------------------- | ||
2452 | #ifndef __ASSEMBLY__ | ||
2453 | |||
2454 | /*************************************************************************** | ||
2455 | * GPIO | ||
2456 | ***************************************************************************/ | ||
2457 | |||
2458 | //------------------------------------------------------ | ||
2459 | // GPIO Pins Description | ||
2460 | // | ||
2461 | // PORT 0: | ||
2462 | // | ||
2463 | // PIN/BIT N FUNC0 FUNC1 | ||
2464 | // 0 D0 - | ||
2465 | // 1 D1 - | ||
2466 | // 2 D2 - | ||
2467 | // 3 D3 - | ||
2468 | // 4 D4 - | ||
2469 | // 5 D5 - | ||
2470 | // 6 D6 - | ||
2471 | // 7 D7 - | ||
2472 | // 8 D8 - | ||
2473 | // 9 D9 - | ||
2474 | // 10 D10 - | ||
2475 | // 11 D11 - | ||
2476 | // 12 D12 - | ||
2477 | // 13 D13 - | ||
2478 | // 14 D14 - | ||
2479 | // 15 D15 - | ||
2480 | // 16 D16 - | ||
2481 | // 17 D17 - | ||
2482 | // 18 D18 - | ||
2483 | // 19 D19 - | ||
2484 | // 20 D20 - | ||
2485 | // 21 D21 - | ||
2486 | // 22 D22 - | ||
2487 | // 23 D23 - | ||
2488 | // 24 D24 - | ||
2489 | // 25 D25 - | ||
2490 | // 26 D26 - | ||
2491 | // 27 D27 - | ||
2492 | // 28 D28 - | ||
2493 | // 29 D29 - | ||
2494 | // 30 D30 - | ||
2495 | // 31 D31 - | ||
2496 | // | ||
2497 | //------------------------------------------------------ | ||
2498 | // PORT 1: | ||
2499 | // | ||
2500 | // PIN/BIT N FUNC0 FUNC1 | ||
2501 | // 0 A0 - | ||
2502 | // 1 A1 - | ||
2503 | // 2 A2 - | ||
2504 | // 3 A3 - | ||
2505 | // 4 A4 - | ||
2506 | // 5 A5 - | ||
2507 | // 6 A6 - | ||
2508 | // 7 A7 - | ||
2509 | // 8 A8 - | ||
2510 | // 9 A9 - | ||
2511 | // 10 A10 - | ||
2512 | // 11 A11 - | ||
2513 | // 12 A12 - | ||
2514 | // 13 A13 - | ||
2515 | // 14 A14 - | ||
2516 | // 15 A15/CL - | ||
2517 | // 16 A16/AL - | ||
2518 | // 17 LCD_CLS A21 | ||
2519 | // 18 LCD_SPL A22 | ||
2520 | // 19 DCS# - | ||
2521 | // 20 RAS# - | ||
2522 | // 21 CAS# - | ||
2523 | // 22 RDWE#/BUFD# - | ||
2524 | // 23 CKE - | ||
2525 | // 24 CKO - | ||
2526 | // 25 CS1# - | ||
2527 | // 26 CS2# - | ||
2528 | // 27 CS3# - | ||
2529 | // 28 CS4# - | ||
2530 | // 29 RD# - | ||
2531 | // 30 WR# - | ||
2532 | // 31 WE0# - | ||
2533 | // | ||
2534 | // Note: PIN15&16 are CL&AL when connecting to NAND flash. | ||
2535 | //------------------------------------------------------ | ||
2536 | // PORT 2: | ||
2537 | // | ||
2538 | // PIN/BIT N FUNC0 FUNC1 | ||
2539 | // 0 LCD_D0 - | ||
2540 | // 1 LCD_D1 - | ||
2541 | // 2 LCD_D2 - | ||
2542 | // 3 LCD_D3 - | ||
2543 | // 4 LCD_D4 - | ||
2544 | // 5 LCD_D5 - | ||
2545 | // 6 LCD_D6 - | ||
2546 | // 7 LCD_D7 - | ||
2547 | // 8 LCD_D8 - | ||
2548 | // 9 LCD_D9 - | ||
2549 | // 10 LCD_D10 - | ||
2550 | // 11 LCD_D11 - | ||
2551 | // 12 LCD_D12 - | ||
2552 | // 13 LCD_D13 - | ||
2553 | // 14 LCD_D14 - | ||
2554 | // 15 LCD_D15 - | ||
2555 | // 16 LCD_D16 - | ||
2556 | // 17 LCD_D17 - | ||
2557 | // 18 LCD_PCLK - | ||
2558 | // 19 LCD_HSYNC - | ||
2559 | // 20 LCD_VSYNC - | ||
2560 | // 21 LCD_DE - | ||
2561 | // 22 LCD_PS A19 | ||
2562 | // 23 LCD_REV A20 | ||
2563 | // 24 WE1# - | ||
2564 | // 25 WE2# - | ||
2565 | // 26 WE3# - | ||
2566 | // 27 WAIT# - | ||
2567 | // 28 FRE# - | ||
2568 | // 29 FWE# - | ||
2569 | // 30(NOTE:FRB#) - - | ||
2570 | // 31 - - | ||
2571 | // | ||
2572 | // NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. | ||
2573 | //------------------------------------------------------ | ||
2574 | // PORT 3: | ||
2575 | // | ||
2576 | // PIN/BIT N FUNC0 FUNC1 | ||
2577 | // 0 CIM_D0 - | ||
2578 | // 1 CIM_D1 - | ||
2579 | // 2 CIM_D2 - | ||
2580 | // 3 CIM_D3 - | ||
2581 | // 4 CIM_D4 - | ||
2582 | // 5 CIM_D5 - | ||
2583 | // 6 CIM_D6 - | ||
2584 | // 7 CIM_D7 - | ||
2585 | // 8 MSC_CMD - | ||
2586 | // 9 MSC_CLK - | ||
2587 | // 10 MSC_D0 - | ||
2588 | // 11 MSC_D1 - | ||
2589 | // 12 MSC_D2 - | ||
2590 | // 13 MSC_D3 - | ||
2591 | // 14 CIM_MCLK - | ||
2592 | // 15 CIM_PCLK - | ||
2593 | // 16 CIM_VSYNC - | ||
2594 | // 17 CIM_HSYNC - | ||
2595 | // 18 SSI_CLK SCLK_RSTN | ||
2596 | // 19 SSI_CE0# BIT_CLK(AIC) | ||
2597 | // 20 SSI_DT SDATA_OUT(AIC) | ||
2598 | // 21 SSI_DR SDATA_IN(AIC) | ||
2599 | // 22 SSI_CE1#&GPC SYNC(AIC) | ||
2600 | // 23 PWM0 I2C_SDA | ||
2601 | // 24 PWM1 I2C_SCK | ||
2602 | // 25 PWM2 UART0_TxD | ||
2603 | // 26 PWM3 UART0_RxD | ||
2604 | // 27 PWM4 A17 | ||
2605 | // 28 PWM5 A18 | ||
2606 | // 29 - - | ||
2607 | // 30 PWM6 UART0_CTS/UART1_RxD | ||
2608 | // 31 PWM7 UART0_RTS/UART1_TxD | ||
2609 | // | ||
2610 | ////////////////////////////////////////////////////////// | ||
2611 | |||
2612 | /* | ||
2613 | * p is the port number (0,1,2,3) | ||
2614 | * o is the pin offset (0-31) inside the port | ||
2615 | * n is the absolute number of a pin (0-127), regardless of the port | ||
2616 | */ | ||
2617 | |||
2618 | //------------------------------------------- | ||
2619 | // Function Pins Mode | ||
2620 | |||
2621 | #define __gpio_as_func0(n) \ | ||
2622 | do { \ | ||
2623 | unsigned int p, o; \ | ||
2624 | p = (n) / 32; \ | ||
2625 | o = (n) % 32; \ | ||
2626 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
2627 | REG_GPIO_PXSELC(p) = (1 << o); \ | ||
2628 | } while (0) | ||
2629 | |||
2630 | #define __gpio_as_func1(n) \ | ||
2631 | do { \ | ||
2632 | unsigned int p, o; \ | ||
2633 | p = (n) / 32; \ | ||
2634 | o = (n) % 32; \ | ||
2635 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
2636 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
2637 | } while (0) | ||
2638 | |||
2639 | /* | ||
2640 | * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, | ||
2641 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# | ||
2642 | */ | ||
2643 | #define __gpio_as_sdram_32bit() \ | ||
2644 | do { \ | ||
2645 | REG_GPIO_PXFUNS(0) = 0xffffffff; \ | ||
2646 | REG_GPIO_PXSELC(0) = 0xffffffff; \ | ||
2647 | REG_GPIO_PXPES(0) = 0xffffffff; \ | ||
2648 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ | ||
2649 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ | ||
2650 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ | ||
2651 | REG_GPIO_PXFUNS(2) = 0x07000000; \ | ||
2652 | REG_GPIO_PXSELC(2) = 0x07000000; \ | ||
2653 | REG_GPIO_PXPES(2) = 0x07000000; \ | ||
2654 | } while (0) | ||
2655 | |||
2656 | //#ifdef JZ4740_PAVO | ||
2657 | #ifdef JZ4740_4740 | ||
2658 | /* | ||
2659 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, | ||
2660 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# | ||
2661 | */ | ||
2662 | #define __gpio_as_sdram_16bit() \ | ||
2663 | do { \ | ||
2664 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ | ||
2665 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ | ||
2666 | REG_GPIO_PXPES(0) = 0x0000ffff; \ | ||
2667 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ | ||
2668 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ | ||
2669 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ | ||
2670 | REG_GPIO_PXFUNS(2) = 0x07000000; \ | ||
2671 | REG_GPIO_PXSELC(2) = 0x07000000; \ | ||
2672 | REG_GPIO_PXPES(2) = 0x07000000; \ | ||
2673 | } while (0) | ||
2674 | |||
2675 | #endif | ||
2676 | |||
2677 | //#ifdef JZ4740_VIRGO | ||
2678 | #ifdef JZ4740_4720 | ||
2679 | /* | ||
2680 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, | ||
2681 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# | ||
2682 | */ | ||
2683 | #define __gpio_as_sdram_16bit() \ | ||
2684 | do { \ | ||
2685 | REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ | ||
2686 | REG_GPIO_PXSELC(0) = 0x5442bfaa; \ | ||
2687 | REG_GPIO_PXPES(0) = 0x5442bfaa; \ | ||
2688 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ | ||
2689 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ | ||
2690 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ | ||
2691 | REG_GPIO_PXFUNS(2) = 0x01000000; \ | ||
2692 | REG_GPIO_PXSELC(2) = 0x01000000; \ | ||
2693 | REG_GPIO_PXPES(2) = 0x01000000; \ | ||
2694 | } while (0) | ||
2695 | #endif | ||
2696 | |||
2697 | |||
2698 | #ifdef JZ4740_4725 | ||
2699 | /* | ||
2700 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, | ||
2701 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# | ||
2702 | */ | ||
2703 | #define __jz4725__gpio_as_sdram_16bit() \ | ||
2704 | do { \ | ||
2705 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ | ||
2706 | REG_GPIO_PXSELC(0) = 0x0000ffff; \ | ||
2707 | REG_GPIO_PXPES(0) = 0x0000ffff; \ | ||
2708 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ | ||
2709 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ | ||
2710 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ | ||
2711 | REG_GPIO_PXFUNS(2) = 0x07000000; \ | ||
2712 | REG_GPIO_PXSELC(2) = 0x07000000; \ | ||
2713 | REG_GPIO_PXPES(2) = 0x07000000; \ | ||
2714 | } while (0) | ||
2715 | #endif | ||
2716 | /* | ||
2717 | * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# | ||
2718 | */ | ||
2719 | #define __gpio_as_nand() \ | ||
2720 | do { \ | ||
2721 | REG_GPIO_PXFUNS(1) = 0x02018000; \ | ||
2722 | REG_GPIO_PXSELC(1) = 0x02018000; \ | ||
2723 | REG_GPIO_PXPES(1) = 0x02018000; \ | ||
2724 | REG_GPIO_PXFUNS(2) = 0x30000000; \ | ||
2725 | REG_GPIO_PXSELC(2) = 0x30000000; \ | ||
2726 | REG_GPIO_PXPES(2) = 0x30000000; \ | ||
2727 | REG_GPIO_PXFUNC(2) = 0x40000000; \ | ||
2728 | REG_GPIO_PXSELC(2) = 0x40000000; \ | ||
2729 | REG_GPIO_PXDIRC(2) = 0x40000000; \ | ||
2730 | REG_GPIO_PXPES(2) = 0x40000000; \ | ||
2731 | REG_GPIO_PXFUNS(1) = 0x00400000; \ | ||
2732 | REG_GPIO_PXSELC(1) = 0x00400000; \ | ||
2733 | } while (0) | ||
2734 | |||
2735 | /* | ||
2736 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 | ||
2737 | */ | ||
2738 | #define __gpio_as_nor_8bit() \ | ||
2739 | do { \ | ||
2740 | REG_GPIO_PXFUNS(0) = 0x000000ff; \ | ||
2741 | REG_GPIO_PXSELC(0) = 0x000000ff; \ | ||
2742 | REG_GPIO_PXPES(0) = 0x000000ff; \ | ||
2743 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ | ||
2744 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ | ||
2745 | REG_GPIO_PXPES(1) = 0x7041ffff; \ | ||
2746 | REG_GPIO_PXFUNS(1) = 0x00060000; \ | ||
2747 | REG_GPIO_PXSELS(1) = 0x00060000; \ | ||
2748 | REG_GPIO_PXPES(1) = 0x00060000; \ | ||
2749 | REG_GPIO_PXFUNS(2) = 0x08000000; \ | ||
2750 | REG_GPIO_PXSELC(2) = 0x08000000; \ | ||
2751 | REG_GPIO_PXPES(2) = 0x08000000; \ | ||
2752 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ | ||
2753 | REG_GPIO_PXSELS(2) = 0x00c00000; \ | ||
2754 | REG_GPIO_PXPES(2) = 0x00c00000; \ | ||
2755 | REG_GPIO_PXFUNS(3) = 0x18000000; \ | ||
2756 | REG_GPIO_PXSELS(3) = 0x18000000; \ | ||
2757 | REG_GPIO_PXPES(3) = 0x18000000; \ | ||
2758 | } while (0) | ||
2759 | |||
2760 | /* | ||
2761 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 | ||
2762 | */ | ||
2763 | #define __gpio_as_nor_16bit() \ | ||
2764 | do { \ | ||
2765 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ | ||
2766 | REG_GPIO_PXSELC(0) = 0x0000ffff; \ | ||
2767 | REG_GPIO_PXPES(0) = 0x0000ffff; \ | ||
2768 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ | ||
2769 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ | ||
2770 | REG_GPIO_PXPES(1) = 0x7041ffff; \ | ||
2771 | REG_GPIO_PXFUNS(1) = 0x00060000; \ | ||
2772 | REG_GPIO_PXSELS(1) = 0x00060000; \ | ||
2773 | REG_GPIO_PXPES(1) = 0x00060000; \ | ||
2774 | REG_GPIO_PXFUNS(2) = 0x08000000; \ | ||
2775 | REG_GPIO_PXSELC(2) = 0x08000000; \ | ||
2776 | REG_GPIO_PXPES(2) = 0x08000000; \ | ||
2777 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ | ||
2778 | REG_GPIO_PXSELS(2) = 0x00c00000; \ | ||
2779 | REG_GPIO_PXPES(2) = 0x00c00000; \ | ||
2780 | REG_GPIO_PXFUNS(3) = 0x18000000; \ | ||
2781 | REG_GPIO_PXSELS(3) = 0x18000000; \ | ||
2782 | REG_GPIO_PXPES(3) = 0x18000000; \ | ||
2783 | } while (0) | ||
2784 | |||
2785 | /* | ||
2786 | * UART0_TxD, UART_RxD0 | ||
2787 | */ | ||
2788 | #define __gpio_as_uart0() \ | ||
2789 | do { \ | ||
2790 | REG_GPIO_PXFUNS(3) = 0x06000000; \ | ||
2791 | REG_GPIO_PXSELS(3) = 0x06000000; \ | ||
2792 | REG_GPIO_PXPES(3) = 0x06000000; \ | ||
2793 | } while (0) | ||
2794 | |||
2795 | /* | ||
2796 | * UART1_TxD, UART1_RxD1 | ||
2797 | */ | ||
2798 | #define __gpio_as_uart1() \ | ||
2799 | do { \ | ||
2800 | REG_GPIO_PXFUNS(3) = 0xc0000000; \ | ||
2801 | REG_GPIO_PXSELS(3) = 0xc0000000; \ | ||
2802 | REG_GPIO_PXPES(3) = 0xc0000000; \ | ||
2803 | } while (0) | ||
2804 | |||
2805 | /* | ||
2806 | * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
2807 | */ | ||
2808 | #define __gpio_as_lcd_16bit() \ | ||
2809 | do { \ | ||
2810 | REG_GPIO_PXFUNS(2) = 0x003cffff; \ | ||
2811 | REG_GPIO_PXSELC(2) = 0x003cffff; \ | ||
2812 | REG_GPIO_PXPES(2) = 0x003cffff; \ | ||
2813 | } while (0) | ||
2814 | |||
2815 | /* | ||
2816 | * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
2817 | */ | ||
2818 | #define __gpio_as_lcd_18bit() \ | ||
2819 | do { \ | ||
2820 | REG_GPIO_PXFUNS(2) = 0x003fffff; \ | ||
2821 | REG_GPIO_PXSELC(2) = 0x003fffff; \ | ||
2822 | REG_GPIO_PXPES(2) = 0x003fffff; \ | ||
2823 | } while (0) | ||
2824 | |||
2825 | |||
2826 | /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ | ||
2827 | #define __gpio_as_slcd_8bit() \ | ||
2828 | do { \ | ||
2829 | REG_GPIO_PXFUNS(2) = 0x001800ff; \ | ||
2830 | REG_GPIO_PXSELC(2) = 0x001800ff; \ | ||
2831 | } while (0) | ||
2832 | |||
2833 | /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ | ||
2834 | #define __gpio_as_slcd_9bit() \ | ||
2835 | do { \ | ||
2836 | REG_GPIO_PXFUNS(2) = 0x001801ff; \ | ||
2837 | REG_GPIO_PXSELC(2) = 0x001801ff; \ | ||
2838 | } while (0) | ||
2839 | |||
2840 | /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ | ||
2841 | #define __gpio_as_slcd_16bit() \ | ||
2842 | do { \ | ||
2843 | REG_GPIO_PXFUNS(2) = 0x0018ffff; \ | ||
2844 | REG_GPIO_PXSELC(2) = 0x0018ffff; \ | ||
2845 | } while (0) | ||
2846 | |||
2847 | /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ | ||
2848 | #define __gpio_as_slcd_18bit() \ | ||
2849 | do { \ | ||
2850 | REG_GPIO_PXFUNS(2) = 0x001bffff; \ | ||
2851 | REG_GPIO_PXSELC(2) = 0x001bffff; \ | ||
2852 | } while (0) | ||
2853 | |||
2854 | /* | ||
2855 | * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC | ||
2856 | */ | ||
2857 | #define __gpio_as_cim() \ | ||
2858 | do { \ | ||
2859 | REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ | ||
2860 | REG_GPIO_PXSELC(3) = 0x0003c0ff; \ | ||
2861 | REG_GPIO_PXPES(3) = 0x0003c0ff; \ | ||
2862 | } while (0) | ||
2863 | |||
2864 | /* | ||
2865 | * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET | ||
2866 | */ | ||
2867 | #define __gpio_as_aic() \ | ||
2868 | do { \ | ||
2869 | REG_GPIO_PXFUNS(3) = 0x007c0000; \ | ||
2870 | REG_GPIO_PXSELS(3) = 0x007c0000; \ | ||
2871 | REG_GPIO_PXPES(3) = 0x007c0000; \ | ||
2872 | } while (0) | ||
2873 | |||
2874 | /* | ||
2875 | * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 | ||
2876 | */ | ||
2877 | #define __gpio_as_msc() \ | ||
2878 | do { \ | ||
2879 | REG_GPIO_PXFUNS(3) = 0x00003f00; \ | ||
2880 | REG_GPIO_PXSELC(3) = 0x00003f00; \ | ||
2881 | REG_GPIO_PXPES(3) = 0x00003f00; \ | ||
2882 | } while (0) | ||
2883 | |||
2884 | /* | ||
2885 | * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR | ||
2886 | */ | ||
2887 | #define __gpio_as_ssi() \ | ||
2888 | do { \ | ||
2889 | REG_GPIO_PXFUNS(3) = 0x003c0000; \ | ||
2890 | REG_GPIO_PXSELC(3) = 0x003c0000; \ | ||
2891 | REG_GPIO_PXPES(3) = 0x003c0000; \ | ||
2892 | } while (0) | ||
2893 | |||
2894 | /* | ||
2895 | * I2C_SCK, I2C_SDA | ||
2896 | */ | ||
2897 | #define __gpio_as_i2c() \ | ||
2898 | do { \ | ||
2899 | REG_GPIO_PXFUNS(3) = 0x01800000; \ | ||
2900 | REG_GPIO_PXSELS(3) = 0x01800000; \ | ||
2901 | REG_GPIO_PXPES(3) = 0x01800000; \ | ||
2902 | } while (0) | ||
2903 | |||
2904 | /* | ||
2905 | * PWM0 | ||
2906 | */ | ||
2907 | #define __gpio_as_pwm0() \ | ||
2908 | do { \ | ||
2909 | REG_GPIO_PXFUNS(3) = 0x00800000; \ | ||
2910 | REG_GPIO_PXSELC(3) = 0x00800000; \ | ||
2911 | REG_GPIO_PXPES(3) = 0x00800000; \ | ||
2912 | } while (0) | ||
2913 | |||
2914 | /* | ||
2915 | * PWM1 | ||
2916 | */ | ||
2917 | #define __gpio_as_pwm1() \ | ||
2918 | do { \ | ||
2919 | REG_GPIO_PXFUNS(3) = 0x01000000; \ | ||
2920 | REG_GPIO_PXSELC(3) = 0x01000000; \ | ||
2921 | REG_GPIO_PXPES(3) = 0x01000000; \ | ||
2922 | } while (0) | ||
2923 | |||
2924 | /* | ||
2925 | * PWM2 | ||
2926 | */ | ||
2927 | #define __gpio_as_pwm2() \ | ||
2928 | do { \ | ||
2929 | REG_GPIO_PXFUNS(3) = 0x02000000; \ | ||
2930 | REG_GPIO_PXSELC(3) = 0x02000000; \ | ||
2931 | REG_GPIO_PXPES(3) = 0x02000000; \ | ||
2932 | } while (0) | ||
2933 | |||
2934 | /* | ||
2935 | * PWM3 | ||
2936 | */ | ||
2937 | #define __gpio_as_pwm3() \ | ||
2938 | do { \ | ||
2939 | REG_GPIO_PXFUNS(3) = 0x04000000; \ | ||
2940 | REG_GPIO_PXSELC(3) = 0x04000000; \ | ||
2941 | REG_GPIO_PXPES(3) = 0x04000000; \ | ||
2942 | } while (0) | ||
2943 | |||
2944 | /* | ||
2945 | * PWM4 | ||
2946 | */ | ||
2947 | #define __gpio_as_pwm4() \ | ||
2948 | do { \ | ||
2949 | REG_GPIO_PXFUNS(3) = 0x08000000; \ | ||
2950 | REG_GPIO_PXSELC(3) = 0x08000000; \ | ||
2951 | REG_GPIO_PXPES(3) = 0x08000000; \ | ||
2952 | } while (0) | ||
2953 | |||
2954 | /* | ||
2955 | * PWM5 | ||
2956 | */ | ||
2957 | #define __gpio_as_pwm5() \ | ||
2958 | do { \ | ||
2959 | REG_GPIO_PXFUNS(3) = 0x10000000; \ | ||
2960 | REG_GPIO_PXSELC(3) = 0x10000000; \ | ||
2961 | REG_GPIO_PXPES(3) = 0x10000000; \ | ||
2962 | } while (0) | ||
2963 | |||
2964 | /* | ||
2965 | * PWM6 | ||
2966 | */ | ||
2967 | #define __gpio_as_pwm6() \ | ||
2968 | do { \ | ||
2969 | REG_GPIO_PXFUNS(3) = 0x40000000; \ | ||
2970 | REG_GPIO_PXSELC(3) = 0x40000000; \ | ||
2971 | REG_GPIO_PXPES(3) = 0x40000000; \ | ||
2972 | } while (0) | ||
2973 | |||
2974 | /* | ||
2975 | * PWM7 | ||
2976 | */ | ||
2977 | #define __gpio_as_pwm7() \ | ||
2978 | do { \ | ||
2979 | REG_GPIO_PXFUNS(3) = 0x80000000; \ | ||
2980 | REG_GPIO_PXSELC(3) = 0x80000000; \ | ||
2981 | REG_GPIO_PXPES(3) = 0x80000000; \ | ||
2982 | } while (0) | ||
2983 | |||
2984 | /* | ||
2985 | * n = 0 ~ 7 | ||
2986 | */ | ||
2987 | #define __gpio_as_pwm(n) __gpio_as_pwm##n() | ||
2988 | |||
2989 | //------------------------------------------- | ||
2990 | // GPIO or Interrupt Mode | ||
2991 | |||
2992 | #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) | ||
2993 | |||
2994 | #define __gpio_port_as_output(p, o) \ | ||
2995 | do { \ | ||
2996 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ | ||
2997 | REG_GPIO_PXSELC(p) = (1 << (o)); \ | ||
2998 | REG_GPIO_PXDIRS(p) = (1 << (o)); \ | ||
2999 | } while (0) | ||
3000 | |||
3001 | #define __gpio_port_as_input(p, o) \ | ||
3002 | do { \ | ||
3003 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ | ||
3004 | REG_GPIO_PXSELC(p) = (1 << (o)); \ | ||
3005 | REG_GPIO_PXDIRC(p) = (1 << (o)); \ | ||
3006 | } while (0) | ||
3007 | |||
3008 | #define __gpio_as_output(n) \ | ||
3009 | do { \ | ||
3010 | unsigned int p, o; \ | ||
3011 | p = (n) / 32; \ | ||
3012 | o = (n) % 32; \ | ||
3013 | __gpio_port_as_output(p, o); \ | ||
3014 | } while (0) | ||
3015 | |||
3016 | #define __gpio_as_input(n) \ | ||
3017 | do { \ | ||
3018 | unsigned int p, o; \ | ||
3019 | p = (n) / 32; \ | ||
3020 | o = (n) % 32; \ | ||
3021 | __gpio_port_as_input(p, o); \ | ||
3022 | } while (0) | ||
3023 | |||
3024 | #define __gpio_set_pin(n) \ | ||
3025 | do { \ | ||
3026 | unsigned int p, o; \ | ||
3027 | p = (n) / 32; \ | ||
3028 | o = (n) % 32; \ | ||
3029 | REG_GPIO_PXDATS(p) = (1 << o); \ | ||
3030 | } while (0) | ||
3031 | |||
3032 | #define __gpio_clear_pin(n) \ | ||
3033 | do { \ | ||
3034 | unsigned int p, o; \ | ||
3035 | p = (n) / 32; \ | ||
3036 | o = (n) % 32; \ | ||
3037 | REG_GPIO_PXDATC(p) = (1 << o); \ | ||
3038 | } while (0) | ||
3039 | |||
3040 | #define __gpio_get_pin(n) \ | ||
3041 | ({ \ | ||
3042 | unsigned int p, o, v; \ | ||
3043 | p = (n) / 32; \ | ||
3044 | o = (n) % 32; \ | ||
3045 | if (__gpio_get_port(p) & (1 << o)) \ | ||
3046 | v = 1; \ | ||
3047 | else \ | ||
3048 | v = 0; \ | ||
3049 | v; \ | ||
3050 | }) | ||
3051 | |||
3052 | #define __gpio_as_irq_high_level(n) \ | ||
3053 | do { \ | ||
3054 | unsigned int p, o; \ | ||
3055 | p = (n) / 32; \ | ||
3056 | o = (n) % 32; \ | ||
3057 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
3058 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
3059 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
3060 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
3061 | REG_GPIO_PXDIRS(p) = (1 << o); \ | ||
3062 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
3063 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
3064 | } while (0) | ||
3065 | |||
3066 | #define __gpio_as_irq_low_level(n) \ | ||
3067 | do { \ | ||
3068 | unsigned int p, o; \ | ||
3069 | p = (n) / 32; \ | ||
3070 | o = (n) % 32; \ | ||
3071 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
3072 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
3073 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
3074 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
3075 | REG_GPIO_PXDIRC(p) = (1 << o); \ | ||
3076 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
3077 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
3078 | } while (0) | ||
3079 | |||
3080 | #define __gpio_as_irq_rise_edge(n) \ | ||
3081 | do { \ | ||
3082 | unsigned int p, o; \ | ||
3083 | p = (n) / 32; \ | ||
3084 | o = (n) % 32; \ | ||
3085 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
3086 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
3087 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
3088 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
3089 | REG_GPIO_PXDIRS(p) = (1 << o); \ | ||
3090 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
3091 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
3092 | } while (0) | ||
3093 | |||
3094 | #define __gpio_as_irq_fall_edge(n) \ | ||
3095 | do { \ | ||
3096 | unsigned int p, o; \ | ||
3097 | p = (n) / 32; \ | ||
3098 | o = (n) % 32; \ | ||
3099 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
3100 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
3101 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
3102 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
3103 | REG_GPIO_PXDIRC(p) = (1 << o); \ | ||
3104 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
3105 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
3106 | } while (0) | ||
3107 | |||
3108 | #define __gpio_mask_irq(n) \ | ||
3109 | do { \ | ||
3110 | unsigned int p, o; \ | ||
3111 | p = (n) / 32; \ | ||
3112 | o = (n) % 32; \ | ||
3113 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
3114 | } while (0) | ||
3115 | |||
3116 | #define __gpio_unmask_irq(n) \ | ||
3117 | do { \ | ||
3118 | unsigned int p, o; \ | ||
3119 | p = (n) / 32; \ | ||
3120 | o = (n) % 32; \ | ||
3121 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
3122 | } while (0) | ||
3123 | |||
3124 | #define __gpio_ack_irq(n) \ | ||
3125 | do { \ | ||
3126 | unsigned int p, o; \ | ||
3127 | p = (n) / 32; \ | ||
3128 | o = (n) % 32; \ | ||
3129 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
3130 | } while (0) | ||
3131 | |||
3132 | #define __gpio_get_irq() \ | ||
3133 | ({ \ | ||
3134 | unsigned int p, i, tmp, v = 0; \ | ||
3135 | for (p = 3; p >= 0; p--) { \ | ||
3136 | tmp = REG_GPIO_PXFLG(p); \ | ||
3137 | for (i = 0; i < 32; i++) \ | ||
3138 | if (tmp & (1 << i)) \ | ||
3139 | v = (32*p + i); \ | ||
3140 | } \ | ||
3141 | v; \ | ||
3142 | }) | ||
3143 | |||
3144 | #define __gpio_group_irq(n) \ | ||
3145 | ({ \ | ||
3146 | register int tmp, i; \ | ||
3147 | tmp = REG_GPIO_PXFLG((n)); \ | ||
3148 | for (i=31;i>=0;i--) \ | ||
3149 | if (tmp & (1 << i)) \ | ||
3150 | break; \ | ||
3151 | i; \ | ||
3152 | }) | ||
3153 | |||
3154 | #define __gpio_enable_pull(n) \ | ||
3155 | do { \ | ||
3156 | unsigned int p, o; \ | ||
3157 | p = (n) / 32; \ | ||
3158 | o = (n) % 32; \ | ||
3159 | REG_GPIO_PXPEC(p) = (1 << o); \ | ||
3160 | } while (0) | ||
3161 | |||
3162 | #define __gpio_disable_pull(n) \ | ||
3163 | do { \ | ||
3164 | unsigned int p, o; \ | ||
3165 | p = (n) / 32; \ | ||
3166 | o = (n) % 32; \ | ||
3167 | REG_GPIO_PXPES(p) = (1 << o); \ | ||
3168 | } while (0) | ||
3169 | |||
3170 | |||
3171 | /*************************************************************************** | ||
3172 | * CPM | ||
3173 | ***************************************************************************/ | ||
3174 | #define __cpm_get_pllm() \ | ||
3175 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) | ||
3176 | #define __cpm_get_plln() \ | ||
3177 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) | ||
3178 | #define __cpm_get_pllod() \ | ||
3179 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) | ||
3180 | |||
3181 | #define __cpm_get_cdiv() \ | ||
3182 | ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) | ||
3183 | #define __cpm_get_hdiv() \ | ||
3184 | ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) | ||
3185 | #define __cpm_get_pdiv() \ | ||
3186 | ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) | ||
3187 | #define __cpm_get_mdiv() \ | ||
3188 | ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) | ||
3189 | #define __cpm_get_ldiv() \ | ||
3190 | ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) | ||
3191 | #define __cpm_get_udiv() \ | ||
3192 | ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) | ||
3193 | #define __cpm_get_i2sdiv() \ | ||
3194 | ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) | ||
3195 | #define __cpm_get_pixdiv() \ | ||
3196 | ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) | ||
3197 | #define __cpm_get_mscdiv() \ | ||
3198 | ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) | ||
3199 | |||
3200 | #define __cpm_set_cdiv(v) \ | ||
3201 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) | ||
3202 | #define __cpm_set_hdiv(v) \ | ||
3203 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) | ||
3204 | #define __cpm_set_pdiv(v) \ | ||
3205 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) | ||
3206 | #define __cpm_set_mdiv(v) \ | ||
3207 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) | ||
3208 | #define __cpm_set_ldiv(v) \ | ||
3209 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) | ||
3210 | #define __cpm_set_udiv(v) \ | ||
3211 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) | ||
3212 | #define __cpm_set_i2sdiv(v) \ | ||
3213 | (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) | ||
3214 | #define __cpm_set_pixdiv(v) \ | ||
3215 | (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) | ||
3216 | #define __cpm_set_mscdiv(v) \ | ||
3217 | (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) | ||
3218 | |||
3219 | #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) | ||
3220 | #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) | ||
3221 | #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) | ||
3222 | #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) | ||
3223 | #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) | ||
3224 | #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) | ||
3225 | #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) | ||
3226 | #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) | ||
3227 | |||
3228 | #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) | ||
3229 | #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) | ||
3230 | #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) | ||
3231 | |||
3232 | #define __cpm_get_cclk_doze_duty() \ | ||
3233 | ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) | ||
3234 | #define __cpm_set_cclk_doze_duty(v) \ | ||
3235 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) | ||
3236 | |||
3237 | #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) | ||
3238 | #define __cpm_idle_mode() \ | ||
3239 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) | ||
3240 | #define __cpm_sleep_mode() \ | ||
3241 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) | ||
3242 | |||
3243 | #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) | ||
3244 | #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) | ||
3245 | #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) | ||
3246 | #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) | ||
3247 | #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) | ||
3248 | #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) | ||
3249 | #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) | ||
3250 | #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) | ||
3251 | #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) | ||
3252 | #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) | ||
3253 | #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) | ||
3254 | #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) | ||
3255 | #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) | ||
3256 | #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) | ||
3257 | #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) | ||
3258 | #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) | ||
3259 | #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) | ||
3260 | |||
3261 | #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) | ||
3262 | #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) | ||
3263 | #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) | ||
3264 | #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) | ||
3265 | #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) | ||
3266 | #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) | ||
3267 | #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) | ||
3268 | #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) | ||
3269 | #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) | ||
3270 | #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) | ||
3271 | #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) | ||
3272 | #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) | ||
3273 | #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) | ||
3274 | #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) | ||
3275 | #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) | ||
3276 | #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) | ||
3277 | #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) | ||
3278 | |||
3279 | #define __cpm_get_o1st() \ | ||
3280 | ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) | ||
3281 | #define __cpm_set_o1st(v) \ | ||
3282 | (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) | ||
3283 | #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) | ||
3284 | #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) | ||
3285 | |||
3286 | |||
3287 | #ifdef CFG_EXTAL | ||
3288 | #define JZ_EXTAL CFG_EXTAL | ||
3289 | #else | ||
3290 | #define JZ_EXTAL 3686400 | ||
3291 | #endif | ||
3292 | #define JZ_EXTAL2 32768 /* RTC clock */ | ||
3293 | |||
3294 | /* PLL output frequency */ | ||
3295 | static __inline__ unsigned int __cpm_get_pllout(void) | ||
3296 | { | ||
3297 | unsigned long m, n, no, pllout; | ||
3298 | unsigned long cppcr = REG_CPM_CPPCR; | ||
3299 | unsigned long od[4] = {1, 2, 2, 4}; | ||
3300 | if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { | ||
3301 | m = __cpm_get_pllm() + 2; | ||
3302 | n = __cpm_get_plln() + 2; | ||
3303 | no = od[__cpm_get_pllod()]; | ||
3304 | pllout = ((JZ_EXTAL) / (n * no)) * m; | ||
3305 | } else | ||
3306 | pllout = JZ_EXTAL; | ||
3307 | return pllout; | ||
3308 | } | ||
3309 | |||
3310 | /* PLL output frequency for MSC/I2S/LCD/USB */ | ||
3311 | static __inline__ unsigned int __cpm_get_pllout2(void) | ||
3312 | { | ||
3313 | if (REG_CPM_CPCCR & CPM_CPCCR_PCS) | ||
3314 | return __cpm_get_pllout(); | ||
3315 | else | ||
3316 | return __cpm_get_pllout()/2; | ||
3317 | } | ||
3318 | |||
3319 | /* CPU core clock */ | ||
3320 | static __inline__ unsigned int __cpm_get_cclk(void) | ||
3321 | { | ||
3322 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; | ||
3323 | |||
3324 | return __cpm_get_pllout() / div[__cpm_get_cdiv()]; | ||
3325 | } | ||
3326 | |||
3327 | /* AHB system bus clock */ | ||
3328 | static __inline__ unsigned int __cpm_get_hclk(void) | ||
3329 | { | ||
3330 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; | ||
3331 | |||
3332 | return __cpm_get_pllout() / div[__cpm_get_hdiv()]; | ||
3333 | } | ||
3334 | |||
3335 | /* Memory bus clock */ | ||
3336 | static __inline__ unsigned int __cpm_get_mclk(void) | ||
3337 | { | ||
3338 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; | ||
3339 | |||
3340 | return __cpm_get_pllout() / div[__cpm_get_mdiv()]; | ||
3341 | } | ||
3342 | |||
3343 | /* APB peripheral bus clock */ | ||
3344 | static __inline__ unsigned int __cpm_get_pclk(void) | ||
3345 | { | ||
3346 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; | ||
3347 | |||
3348 | return __cpm_get_pllout() / div[__cpm_get_pdiv()]; | ||
3349 | } | ||
3350 | |||
3351 | /* LCDC module clock */ | ||
3352 | static __inline__ unsigned int __cpm_get_lcdclk(void) | ||
3353 | { | ||
3354 | return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); | ||
3355 | } | ||
3356 | |||
3357 | /* LCD pixel clock */ | ||
3358 | static __inline__ unsigned int __cpm_get_pixclk(void) | ||
3359 | { | ||
3360 | return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); | ||
3361 | } | ||
3362 | |||
3363 | /* I2S clock */ | ||
3364 | static __inline__ unsigned int __cpm_get_i2sclk(void) | ||
3365 | { | ||
3366 | if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { | ||
3367 | return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); | ||
3368 | } | ||
3369 | else { | ||
3370 | return JZ_EXTAL; | ||
3371 | } | ||
3372 | } | ||
3373 | |||
3374 | /* USB clock */ | ||
3375 | static __inline__ unsigned int __cpm_get_usbclk(void) | ||
3376 | { | ||
3377 | if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { | ||
3378 | return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); | ||
3379 | } | ||
3380 | else { | ||
3381 | return JZ_EXTAL; | ||
3382 | } | ||
3383 | } | ||
3384 | |||
3385 | /* MSC clock */ | ||
3386 | static __inline__ unsigned int __cpm_get_mscclk(void) | ||
3387 | { | ||
3388 | return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); | ||
3389 | } | ||
3390 | |||
3391 | /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ | ||
3392 | static __inline__ unsigned int __cpm_get_extalclk(void) | ||
3393 | { | ||
3394 | return JZ_EXTAL; | ||
3395 | } | ||
3396 | |||
3397 | /* RTC clock for CPM,INTC,RTC,TCU,WDT */ | ||
3398 | static __inline__ unsigned int __cpm_get_rtcclk(void) | ||
3399 | { | ||
3400 | return JZ_EXTAL2; | ||
3401 | } | ||
3402 | |||
3403 | /* | ||
3404 | * Output 24MHz for SD and 16MHz for MMC. | ||
3405 | */ | ||
3406 | static inline void __cpm_select_msc_clk(int sd) | ||
3407 | { | ||
3408 | unsigned int pllout2 = __cpm_get_pllout2(); | ||
3409 | unsigned int div = 0; | ||
3410 | |||
3411 | if (sd) { | ||
3412 | div = pllout2 / 24000000; | ||
3413 | } | ||
3414 | else { | ||
3415 | div = pllout2 / 16000000; | ||
3416 | } | ||
3417 | |||
3418 | REG_CPM_MSCCDR = div - 1; | ||
3419 | } | ||
3420 | |||
3421 | /* | ||
3422 | * Output 48MHz for SD and 16MHz for MMC. | ||
3423 | */ | ||
3424 | static inline void __cpm_select_msc_hs_clk(int sd) | ||
3425 | { | ||
3426 | unsigned int pllout2 = __cpm_get_pllout2(); | ||
3427 | unsigned int div = 0; | ||
3428 | |||
3429 | if (sd) { | ||
3430 | div = pllout2 / 48000000; | ||
3431 | } | ||
3432 | else { | ||
3433 | div = pllout2 / 16000000; | ||
3434 | } | ||
3435 | REG_CPM_MSCCDR = div - 1; | ||
3436 | } | ||
3437 | |||
3438 | /*************************************************************************** | ||
3439 | * TCU | ||
3440 | ***************************************************************************/ | ||
3441 | // where 'n' is the TCU channel | ||
3442 | #define __tcu_select_extalclk(n) \ | ||
3443 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) | ||
3444 | #define __tcu_select_rtcclk(n) \ | ||
3445 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) | ||
3446 | #define __tcu_select_pclk(n) \ | ||
3447 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) | ||
3448 | |||
3449 | #define __tcu_select_clk_div1(n) \ | ||
3450 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) | ||
3451 | #define __tcu_select_clk_div4(n) \ | ||
3452 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) | ||
3453 | #define __tcu_select_clk_div16(n) \ | ||
3454 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) | ||
3455 | #define __tcu_select_clk_div64(n) \ | ||
3456 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) | ||
3457 | #define __tcu_select_clk_div256(n) \ | ||
3458 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) | ||
3459 | #define __tcu_select_clk_div1024(n) \ | ||
3460 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) | ||
3461 | |||
3462 | #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) | ||
3463 | #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) | ||
3464 | |||
3465 | #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) | ||
3466 | #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) | ||
3467 | |||
3468 | #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) | ||
3469 | #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) | ||
3470 | |||
3471 | #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) | ||
3472 | #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) | ||
3473 | |||
3474 | #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) | ||
3475 | #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) | ||
3476 | #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) | ||
3477 | #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) | ||
3478 | #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) | ||
3479 | #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) | ||
3480 | #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) | ||
3481 | #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) | ||
3482 | #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) | ||
3483 | #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) | ||
3484 | |||
3485 | #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) | ||
3486 | #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) | ||
3487 | |||
3488 | #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) | ||
3489 | #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) | ||
3490 | |||
3491 | #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) | ||
3492 | #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) | ||
3493 | |||
3494 | #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) | ||
3495 | #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) | ||
3496 | #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) | ||
3497 | #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) | ||
3498 | |||
3499 | |||
3500 | /*************************************************************************** | ||
3501 | * WDT | ||
3502 | ***************************************************************************/ | ||
3503 | #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) | ||
3504 | #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) | ||
3505 | #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) | ||
3506 | #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) | ||
3507 | |||
3508 | #define __wdt_select_extalclk() \ | ||
3509 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) | ||
3510 | #define __wdt_select_rtcclk() \ | ||
3511 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) | ||
3512 | #define __wdt_select_pclk() \ | ||
3513 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) | ||
3514 | |||
3515 | #define __wdt_select_clk_div1() \ | ||
3516 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) | ||
3517 | #define __wdt_select_clk_div4() \ | ||
3518 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) | ||
3519 | #define __wdt_select_clk_div16() \ | ||
3520 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) | ||
3521 | #define __wdt_select_clk_div64() \ | ||
3522 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) | ||
3523 | #define __wdt_select_clk_div256() \ | ||
3524 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) | ||
3525 | #define __wdt_select_clk_div1024() \ | ||
3526 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) | ||
3527 | |||
3528 | |||
3529 | /*************************************************************************** | ||
3530 | * UART | ||
3531 | ***************************************************************************/ | ||
3532 | |||
3533 | #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) | ||
3534 | #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) | ||
3535 | |||
3536 | #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) | ||
3537 | #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) | ||
3538 | |||
3539 | #define __uart_enable_receive_irq() \ | ||
3540 | ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) | ||
3541 | #define __uart_disable_receive_irq() \ | ||
3542 | ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) | ||
3543 | |||
3544 | #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) | ||
3545 | #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) | ||
3546 | |||
3547 | #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) | ||
3548 | |||
3549 | #define __uart_set_baud(devclk, baud) \ | ||
3550 | do { \ | ||
3551 | REG8(UART0_LCR) |= UARTLCR_DLAB; \ | ||
3552 | REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ | ||
3553 | REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ | ||
3554 | REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ | ||
3555 | } while (0) | ||
3556 | |||
3557 | #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) | ||
3558 | #define __uart_clear_errors() \ | ||
3559 | ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) | ||
3560 | |||
3561 | #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) | ||
3562 | #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) | ||
3563 | #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) | ||
3564 | #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) | ||
3565 | #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) | ||
3566 | #define __uart_receive_char() REG8(UART0_RDR) | ||
3567 | #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) | ||
3568 | #define __uart_enable_irda() \ | ||
3569 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ | ||
3570 | ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) | ||
3571 | |||
3572 | |||
3573 | /*************************************************************************** | ||
3574 | * DMAC | ||
3575 | ***************************************************************************/ | ||
3576 | |||
3577 | /* n is the DMA channel (0 - 5) */ | ||
3578 | |||
3579 | #define __dmac_enable_module() \ | ||
3580 | ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) | ||
3581 | #define __dmac_disable_module() \ | ||
3582 | ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) | ||
3583 | |||
3584 | /* p=0,1,2,3 */ | ||
3585 | #define __dmac_set_priority(p) \ | ||
3586 | do { \ | ||
3587 | REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ | ||
3588 | REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ | ||
3589 | } while (0) | ||
3590 | |||
3591 | #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) | ||
3592 | #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) | ||
3593 | |||
3594 | #define __dmac_enable_descriptor(n) \ | ||
3595 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) | ||
3596 | #define __dmac_disable_descriptor(n) \ | ||
3597 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) | ||
3598 | |||
3599 | #define __dmac_enable_channel(n) \ | ||
3600 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) | ||
3601 | #define __dmac_disable_channel(n) \ | ||
3602 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) | ||
3603 | #define __dmac_channel_enabled(n) \ | ||
3604 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) | ||
3605 | |||
3606 | #define __dmac_channel_enable_irq(n) \ | ||
3607 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) | ||
3608 | #define __dmac_channel_disable_irq(n) \ | ||
3609 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) | ||
3610 | |||
3611 | #define __dmac_channel_transmit_halt_detected(n) \ | ||
3612 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) | ||
3613 | #define __dmac_channel_transmit_end_detected(n) \ | ||
3614 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) | ||
3615 | #define __dmac_channel_address_error_detected(n) \ | ||
3616 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) | ||
3617 | #define __dmac_channel_count_terminated_detected(n) \ | ||
3618 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) | ||
3619 | #define __dmac_channel_descriptor_invalid_detected(n) \ | ||
3620 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) | ||
3621 | |||
3622 | #define __dmac_channel_clear_transmit_halt(n) \ | ||
3623 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) | ||
3624 | #define __dmac_channel_clear_transmit_end(n) \ | ||
3625 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) | ||
3626 | #define __dmac_channel_clear_address_error(n) \ | ||
3627 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) | ||
3628 | #define __dmac_channel_clear_count_terminated(n) \ | ||
3629 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) | ||
3630 | #define __dmac_channel_clear_descriptor_invalid(n) \ | ||
3631 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) | ||
3632 | |||
3633 | #define __dmac_channel_set_single_mode(n) \ | ||
3634 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) | ||
3635 | #define __dmac_channel_set_block_mode(n) \ | ||
3636 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) | ||
3637 | |||
3638 | #define __dmac_channel_set_transfer_unit_32bit(n) \ | ||
3639 | do { \ | ||
3640 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
3641 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ | ||
3642 | } while (0) | ||
3643 | |||
3644 | #define __dmac_channel_set_transfer_unit_16bit(n) \ | ||
3645 | do { \ | ||
3646 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
3647 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ | ||
3648 | } while (0) | ||
3649 | |||
3650 | #define __dmac_channel_set_transfer_unit_8bit(n) \ | ||
3651 | do { \ | ||
3652 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
3653 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ | ||
3654 | } while (0) | ||
3655 | |||
3656 | #define __dmac_channel_set_transfer_unit_16byte(n) \ | ||
3657 | do { \ | ||
3658 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
3659 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ | ||
3660 | } while (0) | ||
3661 | |||
3662 | #define __dmac_channel_set_transfer_unit_32byte(n) \ | ||
3663 | do { \ | ||
3664 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
3665 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ | ||
3666 | } while (0) | ||
3667 | |||
3668 | /* w=8,16,32 */ | ||
3669 | #define __dmac_channel_set_dest_port_width(n,w) \ | ||
3670 | do { \ | ||
3671 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ | ||
3672 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ | ||
3673 | } while (0) | ||
3674 | |||
3675 | /* w=8,16,32 */ | ||
3676 | #define __dmac_channel_set_src_port_width(n,w) \ | ||
3677 | do { \ | ||
3678 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ | ||
3679 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ | ||
3680 | } while (0) | ||
3681 | |||
3682 | /* v=0-15 */ | ||
3683 | #define __dmac_channel_set_rdil(n,v) \ | ||
3684 | do { \ | ||
3685 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ | ||
3686 | REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \ | ||
3687 | } while (0) | ||
3688 | |||
3689 | #define __dmac_channel_dest_addr_fixed(n) \ | ||
3690 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) | ||
3691 | #define __dmac_channel_dest_addr_increment(n) \ | ||
3692 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) | ||
3693 | |||
3694 | #define __dmac_channel_src_addr_fixed(n) \ | ||
3695 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) | ||
3696 | #define __dmac_channel_src_addr_increment(n) \ | ||
3697 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) | ||
3698 | |||
3699 | #define __dmac_channel_set_doorbell(n) \ | ||
3700 | ( REG_DMAC_DMADBSR = (1 << (n)) ) | ||
3701 | |||
3702 | #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) | ||
3703 | #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) | ||
3704 | |||
3705 | static __inline__ int __dmac_get_irq(void) | ||
3706 | { | ||
3707 | int i; | ||
3708 | for (i = 0; i < MAX_DMA_NUM; i++) | ||
3709 | if (__dmac_channel_irq_detected(i)) | ||
3710 | return i; | ||
3711 | return -1; | ||
3712 | } | ||
3713 | |||
3714 | |||
3715 | /*************************************************************************** | ||
3716 | * AIC (AC'97 & I2S Controller) | ||
3717 | ***************************************************************************/ | ||
3718 | |||
3719 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) | ||
3720 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) | ||
3721 | |||
3722 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) | ||
3723 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) | ||
3724 | |||
3725 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) | ||
3726 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) | ||
3727 | #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) | ||
3728 | |||
3729 | #define __aic_reset() \ | ||
3730 | do { \ | ||
3731 | REG_AIC_FR |= AIC_FR_RST; \ | ||
3732 | } while(0) | ||
3733 | |||
3734 | |||
3735 | #define __aic_set_transmit_trigger(n) \ | ||
3736 | do { \ | ||
3737 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ | ||
3738 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ | ||
3739 | } while(0) | ||
3740 | |||
3741 | #define __aic_set_receive_trigger(n) \ | ||
3742 | do { \ | ||
3743 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ | ||
3744 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ | ||
3745 | } while(0) | ||
3746 | |||
3747 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) | ||
3748 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) | ||
3749 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) | ||
3750 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) | ||
3751 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) | ||
3752 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) | ||
3753 | |||
3754 | #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) | ||
3755 | #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) | ||
3756 | |||
3757 | #define __aic_enable_transmit_intr() \ | ||
3758 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) | ||
3759 | #define __aic_disable_transmit_intr() \ | ||
3760 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) | ||
3761 | #define __aic_enable_receive_intr() \ | ||
3762 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) | ||
3763 | #define __aic_disable_receive_intr() \ | ||
3764 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) | ||
3765 | |||
3766 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) | ||
3767 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) | ||
3768 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) | ||
3769 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) | ||
3770 | |||
3771 | #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) | ||
3772 | #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) | ||
3773 | #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) | ||
3774 | #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) | ||
3775 | #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) | ||
3776 | #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) | ||
3777 | |||
3778 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 | ||
3779 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 | ||
3780 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 | ||
3781 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 | ||
3782 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 | ||
3783 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 | ||
3784 | |||
3785 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 | ||
3786 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 | ||
3787 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 | ||
3788 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 | ||
3789 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 | ||
3790 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 | ||
3791 | |||
3792 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) | ||
3793 | #define __ac97_set_xs_mono() \ | ||
3794 | do { \ | ||
3795 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ | ||
3796 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ | ||
3797 | } while(0) | ||
3798 | #define __ac97_set_xs_stereo() \ | ||
3799 | do { \ | ||
3800 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ | ||
3801 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ | ||
3802 | } while(0) | ||
3803 | |||
3804 | /* In fact, only stereo is support now. */ | ||
3805 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) | ||
3806 | #define __ac97_set_rs_mono() \ | ||
3807 | do { \ | ||
3808 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ | ||
3809 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ | ||
3810 | } while(0) | ||
3811 | #define __ac97_set_rs_stereo() \ | ||
3812 | do { \ | ||
3813 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ | ||
3814 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ | ||
3815 | } while(0) | ||
3816 | |||
3817 | #define __ac97_warm_reset_codec() \ | ||
3818 | do { \ | ||
3819 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ | ||
3820 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ | ||
3821 | udelay(2); \ | ||
3822 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ | ||
3823 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ | ||
3824 | } while (0) | ||
3825 | |||
3826 | #define __ac97_cold_reset_codec() \ | ||
3827 | do { \ | ||
3828 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ | ||
3829 | udelay(2); \ | ||
3830 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ | ||
3831 | } while (0) | ||
3832 | |||
3833 | /* n=8,16,18,20 */ | ||
3834 | #define __ac97_set_iass(n) \ | ||
3835 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) | ||
3836 | #define __ac97_set_oass(n) \ | ||
3837 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) | ||
3838 | |||
3839 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) | ||
3840 | #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) | ||
3841 | |||
3842 | /* n=8,16,18,20,24 */ | ||
3843 | /*#define __i2s_set_sample_size(n) \ | ||
3844 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ | ||
3845 | |||
3846 | #define __i2s_set_oss_sample_size(n) \ | ||
3847 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) | ||
3848 | #define __i2s_set_iss_sample_size(n) \ | ||
3849 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) | ||
3850 | |||
3851 | #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) | ||
3852 | #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) | ||
3853 | |||
3854 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) | ||
3855 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) | ||
3856 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) | ||
3857 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) | ||
3858 | |||
3859 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) | ||
3860 | |||
3861 | #define __aic_get_transmit_resident() \ | ||
3862 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) | ||
3863 | #define __aic_get_receive_count() \ | ||
3864 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) | ||
3865 | |||
3866 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) | ||
3867 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) | ||
3868 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) | ||
3869 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) | ||
3870 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) | ||
3871 | #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) | ||
3872 | #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) | ||
3873 | |||
3874 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) | ||
3875 | |||
3876 | #define CODEC_READ_CMD (1 << 19) | ||
3877 | #define CODEC_WRITE_CMD (0 << 19) | ||
3878 | #define CODEC_REG_INDEX_BIT 12 | ||
3879 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ | ||
3880 | #define CODEC_REG_DATA_BIT 4 | ||
3881 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ | ||
3882 | |||
3883 | #define __ac97_out_rcmd_addr(reg) \ | ||
3884 | do { \ | ||
3885 | REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ | ||
3886 | } while (0) | ||
3887 | |||
3888 | #define __ac97_out_wcmd_addr(reg) \ | ||
3889 | do { \ | ||
3890 | REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ | ||
3891 | } while (0) | ||
3892 | |||
3893 | #define __ac97_out_data(value) \ | ||
3894 | do { \ | ||
3895 | REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ | ||
3896 | } while (0) | ||
3897 | |||
3898 | #define __ac97_in_data() \ | ||
3899 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) | ||
3900 | |||
3901 | #define __ac97_in_status_addr() \ | ||
3902 | ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) | ||
3903 | |||
3904 | #define __i2s_set_sample_rate(i2sclk, sync) \ | ||
3905 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) | ||
3906 | |||
3907 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) | ||
3908 | #define __aic_read_rfifo() ( REG_AIC_DR ) | ||
3909 | |||
3910 | #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) | ||
3911 | #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) | ||
3912 | |||
3913 | #define AIC_FR_LSMP (1 << 6) | ||
3914 | #define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) | ||
3915 | // | ||
3916 | // Define next ops for AC97 compatible | ||
3917 | // | ||
3918 | |||
3919 | #define AC97_ACSR AIC_ACSR | ||
3920 | |||
3921 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() | ||
3922 | #define __ac97_disable() __aic_disable() | ||
3923 | #define __ac97_reset() __aic_reset() | ||
3924 | |||
3925 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) | ||
3926 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) | ||
3927 | |||
3928 | #define __ac97_enable_record() __aic_enable_record() | ||
3929 | #define __ac97_disable_record() __aic_disable_record() | ||
3930 | #define __ac97_enable_replay() __aic_enable_replay() | ||
3931 | #define __ac97_disable_replay() __aic_disable_replay() | ||
3932 | #define __ac97_enable_loopback() __aic_enable_loopback() | ||
3933 | #define __ac97_disable_loopback() __aic_disable_loopback() | ||
3934 | |||
3935 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() | ||
3936 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() | ||
3937 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() | ||
3938 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() | ||
3939 | |||
3940 | #define __ac97_transmit_request() __aic_transmit_request() | ||
3941 | #define __ac97_receive_request() __aic_receive_request() | ||
3942 | #define __ac97_transmit_underrun() __aic_transmit_underrun() | ||
3943 | #define __ac97_receive_overrun() __aic_receive_overrun() | ||
3944 | |||
3945 | #define __ac97_clear_errors() __aic_clear_errors() | ||
3946 | |||
3947 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() | ||
3948 | #define __ac97_get_receive_count() __aic_get_receive_count() | ||
3949 | |||
3950 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() | ||
3951 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() | ||
3952 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() | ||
3953 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() | ||
3954 | |||
3955 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) | ||
3956 | #define __ac97_read_rfifo() __aic_read_rfifo() | ||
3957 | |||
3958 | // | ||
3959 | // Define next ops for I2S compatible | ||
3960 | // | ||
3961 | |||
3962 | #define I2S_ACSR AIC_I2SSR | ||
3963 | |||
3964 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() | ||
3965 | #define __i2s_disable() __aic_disable() | ||
3966 | #define __i2s_reset() __aic_reset() | ||
3967 | |||
3968 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) | ||
3969 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) | ||
3970 | |||
3971 | #define __i2s_enable_record() __aic_enable_record() | ||
3972 | #define __i2s_disable_record() __aic_disable_record() | ||
3973 | #define __i2s_enable_replay() __aic_enable_replay() | ||
3974 | #define __i2s_disable_replay() __aic_disable_replay() | ||
3975 | #define __i2s_enable_loopback() __aic_enable_loopback() | ||
3976 | #define __i2s_disable_loopback() __aic_disable_loopback() | ||
3977 | |||
3978 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() | ||
3979 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() | ||
3980 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() | ||
3981 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() | ||
3982 | |||
3983 | #define __i2s_transmit_request() __aic_transmit_request() | ||
3984 | #define __i2s_receive_request() __aic_receive_request() | ||
3985 | #define __i2s_transmit_underrun() __aic_transmit_underrun() | ||
3986 | #define __i2s_receive_overrun() __aic_receive_overrun() | ||
3987 | |||
3988 | #define __i2s_clear_errors() __aic_clear_errors() | ||
3989 | |||
3990 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() | ||
3991 | #define __i2s_get_receive_count() __aic_get_receive_count() | ||
3992 | |||
3993 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() | ||
3994 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() | ||
3995 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() | ||
3996 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() | ||
3997 | |||
3998 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) | ||
3999 | #define __i2s_read_rfifo() __aic_read_rfifo() | ||
4000 | |||
4001 | #define __i2s_reset_codec() \ | ||
4002 | do { \ | ||
4003 | } while (0) | ||
4004 | |||
4005 | |||
4006 | /*************************************************************************** | ||
4007 | * ICDC | ||
4008 | ***************************************************************************/ | ||
4009 | #define __i2s_internal_codec() __aic_internal_codec() | ||
4010 | #define __i2s_external_codec() __aic_external_codec() | ||
4011 | |||
4012 | /*************************************************************************** | ||
4013 | * INTC | ||
4014 | ***************************************************************************/ | ||
4015 | #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) | ||
4016 | #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) | ||
4017 | #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) | ||
4018 | |||
4019 | |||
4020 | /*************************************************************************** | ||
4021 | * I2C | ||
4022 | ***************************************************************************/ | ||
4023 | |||
4024 | #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) | ||
4025 | #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) | ||
4026 | |||
4027 | #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) | ||
4028 | #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) | ||
4029 | #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) | ||
4030 | #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) | ||
4031 | |||
4032 | #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) | ||
4033 | #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) | ||
4034 | #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) | ||
4035 | |||
4036 | #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) | ||
4037 | #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) | ||
4038 | #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) | ||
4039 | |||
4040 | #define __i2c_set_clk(dev_clk, i2c_clk) \ | ||
4041 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) | ||
4042 | |||
4043 | #define __i2c_read() ( REG_I2C_DR ) | ||
4044 | #define __i2c_write(val) ( REG_I2C_DR = (val) ) | ||
4045 | |||
4046 | |||
4047 | /*************************************************************************** | ||
4048 | * MSC | ||
4049 | ***************************************************************************/ | ||
4050 | |||
4051 | #define __msc_start_op() \ | ||
4052 | ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) | ||
4053 | |||
4054 | #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) | ||
4055 | #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) | ||
4056 | #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) | ||
4057 | #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) | ||
4058 | #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) | ||
4059 | #define __msc_get_nob() ( REG_MSC_NOB ) | ||
4060 | #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) | ||
4061 | #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) | ||
4062 | #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) | ||
4063 | #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) | ||
4064 | |||
4065 | #define __msc_set_cmdat_bus_width1() \ | ||
4066 | do { \ | ||
4067 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ | ||
4068 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ | ||
4069 | } while(0) | ||
4070 | |||
4071 | #define __msc_set_cmdat_bus_width4() \ | ||
4072 | do { \ | ||
4073 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ | ||
4074 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ | ||
4075 | } while(0) | ||
4076 | |||
4077 | #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) | ||
4078 | #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) | ||
4079 | #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) | ||
4080 | #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) | ||
4081 | #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) | ||
4082 | #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) | ||
4083 | #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) | ||
4084 | #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) | ||
4085 | |||
4086 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ | ||
4087 | #define __msc_set_cmdat_res_format(r) \ | ||
4088 | do { \ | ||
4089 | REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ | ||
4090 | REG_MSC_CMDAT |= (r); \ | ||
4091 | } while(0) | ||
4092 | |||
4093 | #define __msc_clear_cmdat() \ | ||
4094 | REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ | ||
4095 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ | ||
4096 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) | ||
4097 | |||
4098 | #define __msc_get_imask() ( REG_MSC_IMASK ) | ||
4099 | #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) | ||
4100 | #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) | ||
4101 | #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) | ||
4102 | #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) | ||
4103 | #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) | ||
4104 | #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) | ||
4105 | #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) | ||
4106 | #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) | ||
4107 | #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) | ||
4108 | #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) | ||
4109 | #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) | ||
4110 | #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) | ||
4111 | |||
4112 | /* n=0,1,2,3,4,5,6,7 */ | ||
4113 | #define __msc_set_clkrt(n) \ | ||
4114 | do { \ | ||
4115 | REG_MSC_CLKRT = n; \ | ||
4116 | } while(0) | ||
4117 | |||
4118 | #define __msc_get_ireg() ( REG_MSC_IREG ) | ||
4119 | #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) | ||
4120 | #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) | ||
4121 | #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) | ||
4122 | #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) | ||
4123 | #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) | ||
4124 | #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) | ||
4125 | #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) | ||
4126 | #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) | ||
4127 | |||
4128 | #define __msc_get_stat() ( REG_MSC_STAT ) | ||
4129 | #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) | ||
4130 | #define __msc_stat_crc_err() \ | ||
4131 | ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) | ||
4132 | #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) | ||
4133 | #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) | ||
4134 | #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) | ||
4135 | #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) | ||
4136 | #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) | ||
4137 | |||
4138 | #define __msc_rd_resfifo() ( REG_MSC_RES ) | ||
4139 | #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) | ||
4140 | #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) | ||
4141 | |||
4142 | #define __msc_reset() \ | ||
4143 | do { \ | ||
4144 | REG_MSC_STRPCL = MSC_STRPCL_RESET; \ | ||
4145 | while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ | ||
4146 | } while (0) | ||
4147 | |||
4148 | #define __msc_start_clk() \ | ||
4149 | do { \ | ||
4150 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ | ||
4151 | } while (0) | ||
4152 | |||
4153 | #define __msc_stop_clk() \ | ||
4154 | do { \ | ||
4155 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ | ||
4156 | } while (0) | ||
4157 | |||
4158 | #define MMC_CLK 19169200 | ||
4159 | #define SD_CLK 24576000 | ||
4160 | |||
4161 | /* msc_clk should little than pclk and little than clk retrieve from card */ | ||
4162 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ | ||
4163 | do { \ | ||
4164 | unsigned int rate, pclk, i; \ | ||
4165 | pclk = dev_clk; \ | ||
4166 | rate = type?SD_CLK:MMC_CLK; \ | ||
4167 | if (msc_clk && msc_clk < pclk) \ | ||
4168 | pclk = msc_clk; \ | ||
4169 | i = 0; \ | ||
4170 | while (pclk < rate) \ | ||
4171 | { \ | ||
4172 | i ++; \ | ||
4173 | rate >>= 1; \ | ||
4174 | } \ | ||
4175 | lv = i; \ | ||
4176 | } while(0) | ||
4177 | |||
4178 | /* divide rate to little than or equal to 400kHz */ | ||
4179 | #define __msc_calc_slow_clk_divisor(type, lv) \ | ||
4180 | do { \ | ||
4181 | unsigned int rate, i; \ | ||
4182 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ | ||
4183 | i = 0; \ | ||
4184 | while (rate > 0) \ | ||
4185 | { \ | ||
4186 | rate >>= 1; \ | ||
4187 | i ++; \ | ||
4188 | } \ | ||
4189 | lv = i; \ | ||
4190 | } while(0) | ||
4191 | |||
4192 | |||
4193 | /*************************************************************************** | ||
4194 | * SSI | ||
4195 | ***************************************************************************/ | ||
4196 | |||
4197 | #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) | ||
4198 | #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) | ||
4199 | #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) | ||
4200 | |||
4201 | #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) | ||
4202 | |||
4203 | #define __ssi_select_ce2() \ | ||
4204 | do { \ | ||
4205 | REG_SSI_CR0 |= SSI_CR0_FSEL; \ | ||
4206 | REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ | ||
4207 | } while (0) | ||
4208 | |||
4209 | #define __ssi_select_gpc() \ | ||
4210 | do { \ | ||
4211 | REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ | ||
4212 | REG_SSI_CR1 |= SSI_CR1_MULTS; \ | ||
4213 | } while (0) | ||
4214 | |||
4215 | #define __ssi_enable_tx_intr() \ | ||
4216 | ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) | ||
4217 | |||
4218 | #define __ssi_disable_tx_intr() \ | ||
4219 | ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) | ||
4220 | |||
4221 | #define __ssi_enable_rx_intr() \ | ||
4222 | ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) | ||
4223 | |||
4224 | #define __ssi_disable_rx_intr() \ | ||
4225 | ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) | ||
4226 | |||
4227 | #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) | ||
4228 | #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) | ||
4229 | |||
4230 | #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) | ||
4231 | #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) | ||
4232 | |||
4233 | #define __ssi_finish_receive() \ | ||
4234 | ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) | ||
4235 | |||
4236 | #define __ssi_disable_recvfinish() \ | ||
4237 | ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) | ||
4238 | |||
4239 | #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) | ||
4240 | #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) | ||
4241 | |||
4242 | #define __ssi_flush_fifo() \ | ||
4243 | ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) | ||
4244 | |||
4245 | #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) | ||
4246 | |||
4247 | #define __ssi_spi_format() \ | ||
4248 | do { \ | ||
4249 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ | ||
4250 | REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ | ||
4251 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ | ||
4252 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ | ||
4253 | } while (0) | ||
4254 | |||
4255 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ | ||
4256 | #define __ssi_ssp_format() \ | ||
4257 | do { \ | ||
4258 | REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ | ||
4259 | REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ | ||
4260 | } while (0) | ||
4261 | |||
4262 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ | ||
4263 | #define __ssi_microwire_format() \ | ||
4264 | do { \ | ||
4265 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ | ||
4266 | REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ | ||
4267 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ | ||
4268 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ | ||
4269 | REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ | ||
4270 | } while (0) | ||
4271 | |||
4272 | /* CE# level (FRMHL), CE# in interval time (ITFRM), | ||
4273 | clock phase and polarity (PHA POL), | ||
4274 | interval time (SSIITR), interval characters/frame (SSIICR) */ | ||
4275 | |||
4276 | /* frmhl,endian,mcom,flen,pha,pol MASK */ | ||
4277 | #define SSICR1_MISC_MASK \ | ||
4278 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ | ||
4279 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ | ||
4280 | |||
4281 | #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ | ||
4282 | do { \ | ||
4283 | REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ | ||
4284 | REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ | ||
4285 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ | ||
4286 | ((pha) << 1) | (pol); \ | ||
4287 | } while(0) | ||
4288 | |||
4289 | /* Transfer with MSB or LSB first */ | ||
4290 | #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) | ||
4291 | #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) | ||
4292 | |||
4293 | #define __ssi_set_frame_length(n) \ | ||
4294 | REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) | ||
4295 | |||
4296 | /* n = 1 - 16 */ | ||
4297 | #define __ssi_set_microwire_command_length(n) \ | ||
4298 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) | ||
4299 | |||
4300 | /* Set the clock phase for SPI */ | ||
4301 | #define __ssi_set_spi_clock_phase(n) \ | ||
4302 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) | ||
4303 | |||
4304 | /* Set the clock polarity for SPI */ | ||
4305 | #define __ssi_set_spi_clock_polarity(n) \ | ||
4306 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) | ||
4307 | |||
4308 | /* n = ix8 */ | ||
4309 | #define __ssi_set_tx_trigger(n) \ | ||
4310 | do { \ | ||
4311 | REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ | ||
4312 | REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ | ||
4313 | } while (0) | ||
4314 | |||
4315 | /* n = ix8 */ | ||
4316 | #define __ssi_set_rx_trigger(n) \ | ||
4317 | do { \ | ||
4318 | REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ | ||
4319 | REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ | ||
4320 | } while (0) | ||
4321 | |||
4322 | #define __ssi_get_txfifo_count() \ | ||
4323 | ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) | ||
4324 | |||
4325 | #define __ssi_get_rxfifo_count() \ | ||
4326 | ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) | ||
4327 | |||
4328 | #define __ssi_clear_errors() \ | ||
4329 | ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) | ||
4330 | |||
4331 | #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) | ||
4332 | #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) | ||
4333 | |||
4334 | #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) | ||
4335 | #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) | ||
4336 | #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) | ||
4337 | |||
4338 | #define __ssi_set_clk(dev_clk, ssi_clk) \ | ||
4339 | ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) | ||
4340 | |||
4341 | #define __ssi_receive_data() REG_SSI_DR | ||
4342 | #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) | ||
4343 | |||
4344 | |||
4345 | /*************************************************************************** | ||
4346 | * CIM | ||
4347 | ***************************************************************************/ | ||
4348 | |||
4349 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) | ||
4350 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) | ||
4351 | |||
4352 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) | ||
4353 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) | ||
4354 | |||
4355 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) | ||
4356 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) | ||
4357 | |||
4358 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) | ||
4359 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) | ||
4360 | |||
4361 | #define __cim_sample_data_at_pclk_falling_edge() \ | ||
4362 | ( REG_CIM_CFG |= CIM_CFG_PCP ) | ||
4363 | #define __cim_sample_data_at_pclk_rising_edge() \ | ||
4364 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) | ||
4365 | |||
4366 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) | ||
4367 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) | ||
4368 | |||
4369 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) | ||
4370 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) | ||
4371 | |||
4372 | /* n=0-7 */ | ||
4373 | #define __cim_set_data_packing_mode(n) \ | ||
4374 | do { \ | ||
4375 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ | ||
4376 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ | ||
4377 | } while (0) | ||
4378 | |||
4379 | #define __cim_enable_ccir656_progressive_mode() \ | ||
4380 | do { \ | ||
4381 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
4382 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ | ||
4383 | } while (0) | ||
4384 | |||
4385 | #define __cim_enable_ccir656_interlace_mode() \ | ||
4386 | do { \ | ||
4387 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
4388 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ | ||
4389 | } while (0) | ||
4390 | |||
4391 | #define __cim_enable_gated_clock_mode() \ | ||
4392 | do { \ | ||
4393 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
4394 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ | ||
4395 | } while (0) | ||
4396 | |||
4397 | #define __cim_enable_nongated_clock_mode() \ | ||
4398 | do { \ | ||
4399 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
4400 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ | ||
4401 | } while (0) | ||
4402 | |||
4403 | /* sclk:system bus clock | ||
4404 | * mclk: CIM master clock | ||
4405 | */ | ||
4406 | #define __cim_set_master_clk(sclk, mclk) \ | ||
4407 | do { \ | ||
4408 | REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ | ||
4409 | REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ | ||
4410 | } while (0) | ||
4411 | |||
4412 | #define __cim_enable_sof_intr() \ | ||
4413 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) | ||
4414 | #define __cim_disable_sof_intr() \ | ||
4415 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) | ||
4416 | |||
4417 | #define __cim_enable_eof_intr() \ | ||
4418 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) | ||
4419 | #define __cim_disable_eof_intr() \ | ||
4420 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) | ||
4421 | |||
4422 | #define __cim_enable_stop_intr() \ | ||
4423 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) | ||
4424 | #define __cim_disable_stop_intr() \ | ||
4425 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) | ||
4426 | |||
4427 | #define __cim_enable_trig_intr() \ | ||
4428 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) | ||
4429 | #define __cim_disable_trig_intr() \ | ||
4430 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) | ||
4431 | |||
4432 | #define __cim_enable_rxfifo_overflow_intr() \ | ||
4433 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) | ||
4434 | #define __cim_disable_rxfifo_overflow_intr() \ | ||
4435 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) | ||
4436 | |||
4437 | /* n=1-16 */ | ||
4438 | #define __cim_set_frame_rate(n) \ | ||
4439 | do { \ | ||
4440 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ | ||
4441 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ | ||
4442 | } while (0) | ||
4443 | |||
4444 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) | ||
4445 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) | ||
4446 | |||
4447 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) | ||
4448 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) | ||
4449 | |||
4450 | /* n=4,8,12,16,20,24,28,32 */ | ||
4451 | #define __cim_set_rxfifo_trigger(n) \ | ||
4452 | do { \ | ||
4453 | REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ | ||
4454 | REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ | ||
4455 | } while (0) | ||
4456 | |||
4457 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) | ||
4458 | |||
4459 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) | ||
4460 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) | ||
4461 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) | ||
4462 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) | ||
4463 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) | ||
4464 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) | ||
4465 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) | ||
4466 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) | ||
4467 | |||
4468 | #define __cim_get_iid() ( REG_CIM_IID ) | ||
4469 | #define __cim_get_image_data() ( REG_CIM_RXFIFO ) | ||
4470 | #define __cim_get_dam_cmd() ( REG_CIM_CMD ) | ||
4471 | |||
4472 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) | ||
4473 | |||
4474 | /*************************************************************************** | ||
4475 | * LCD | ||
4476 | ***************************************************************************/ | ||
4477 | #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) | ||
4478 | #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) | ||
4479 | |||
4480 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) | ||
4481 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) | ||
4482 | |||
4483 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) | ||
4484 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) | ||
4485 | |||
4486 | /* n=1,2,4,8,16 */ | ||
4487 | #define __lcd_set_bpp(n) \ | ||
4488 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) | ||
4489 | |||
4490 | /* n=4,8,16 */ | ||
4491 | #define __lcd_set_burst_length(n) \ | ||
4492 | do { \ | ||
4493 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ | ||
4494 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ | ||
4495 | } while (0) | ||
4496 | |||
4497 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) | ||
4498 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) | ||
4499 | |||
4500 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) | ||
4501 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) | ||
4502 | |||
4503 | /* n=2,4,16 */ | ||
4504 | #define __lcd_set_stn_frc(n) \ | ||
4505 | do { \ | ||
4506 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ | ||
4507 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ | ||
4508 | } while (0) | ||
4509 | |||
4510 | |||
4511 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) | ||
4512 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) | ||
4513 | |||
4514 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) | ||
4515 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) | ||
4516 | |||
4517 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) | ||
4518 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) | ||
4519 | |||
4520 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) | ||
4521 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) | ||
4522 | |||
4523 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) | ||
4524 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) | ||
4525 | |||
4526 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) | ||
4527 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) | ||
4528 | |||
4529 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) | ||
4530 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) | ||
4531 | |||
4532 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) | ||
4533 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) | ||
4534 | |||
4535 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) | ||
4536 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) | ||
4537 | |||
4538 | |||
4539 | /* LCD status register indication */ | ||
4540 | |||
4541 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) | ||
4542 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) | ||
4543 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) | ||
4544 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) | ||
4545 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) | ||
4546 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) | ||
4547 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) | ||
4548 | |||
4549 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) | ||
4550 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) | ||
4551 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) | ||
4552 | |||
4553 | #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE ) | ||
4554 | #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE ) | ||
4555 | |||
4556 | /* n=1,2,4,8 for single mono-STN | ||
4557 | * n=4,8 for dual mono-STN | ||
4558 | */ | ||
4559 | #define __lcd_set_panel_datawidth(n) \ | ||
4560 | do { \ | ||
4561 | REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ | ||
4562 | REG_LCD_CFG |= LCD_CFG_PDW_n##; \ | ||
4563 | } while (0) | ||
4564 | |||
4565 | /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */ | ||
4566 | #define __lcd_set_panel_mode(m) \ | ||
4567 | do { \ | ||
4568 | REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ | ||
4569 | REG_LCD_CFG |= (m); \ | ||
4570 | } while(0) | ||
4571 | |||
4572 | /* n = 0-255 */ | ||
4573 | #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) | ||
4574 | #define __lcd_set_ac_bias(n) \ | ||
4575 | do { \ | ||
4576 | REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ | ||
4577 | REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ | ||
4578 | } while(0) | ||
4579 | |||
4580 | #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) | ||
4581 | #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) | ||
4582 | |||
4583 | #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) | ||
4584 | #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) | ||
4585 | |||
4586 | #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) | ||
4587 | #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) | ||
4588 | |||
4589 | #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) | ||
4590 | #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) | ||
4591 | |||
4592 | #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) | ||
4593 | #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) | ||
4594 | |||
4595 | #define __lcd_vsync_get_vps() \ | ||
4596 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) | ||
4597 | |||
4598 | #define __lcd_vsync_get_vpe() \ | ||
4599 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) | ||
4600 | #define __lcd_vsync_set_vpe(n) \ | ||
4601 | do { \ | ||
4602 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ | ||
4603 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ | ||
4604 | } while (0) | ||
4605 | |||
4606 | #define __lcd_hsync_get_hps() \ | ||
4607 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) | ||
4608 | #define __lcd_hsync_set_hps(n) \ | ||
4609 | do { \ | ||
4610 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ | ||
4611 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ | ||
4612 | } while (0) | ||
4613 | |||
4614 | #define __lcd_hsync_get_hpe() \ | ||
4615 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) | ||
4616 | #define __lcd_hsync_set_hpe(n) \ | ||
4617 | do { \ | ||
4618 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ | ||
4619 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ | ||
4620 | } while (0) | ||
4621 | |||
4622 | #define __lcd_vat_get_ht() \ | ||
4623 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) | ||
4624 | #define __lcd_vat_set_ht(n) \ | ||
4625 | do { \ | ||
4626 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ | ||
4627 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ | ||
4628 | } while (0) | ||
4629 | |||
4630 | #define __lcd_vat_get_vt() \ | ||
4631 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) | ||
4632 | #define __lcd_vat_set_vt(n) \ | ||
4633 | do { \ | ||
4634 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ | ||
4635 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ | ||
4636 | } while (0) | ||
4637 | |||
4638 | #define __lcd_dah_get_hds() \ | ||
4639 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) | ||
4640 | #define __lcd_dah_set_hds(n) \ | ||
4641 | do { \ | ||
4642 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ | ||
4643 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ | ||
4644 | } while (0) | ||
4645 | |||
4646 | #define __lcd_dah_get_hde() \ | ||
4647 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) | ||
4648 | #define __lcd_dah_set_hde(n) \ | ||
4649 | do { \ | ||
4650 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ | ||
4651 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ | ||
4652 | } while (0) | ||
4653 | |||
4654 | #define __lcd_dav_get_vds() \ | ||
4655 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) | ||
4656 | #define __lcd_dav_set_vds(n) \ | ||
4657 | do { \ | ||
4658 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ | ||
4659 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ | ||
4660 | } while (0) | ||
4661 | |||
4662 | #define __lcd_dav_get_vde() \ | ||
4663 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) | ||
4664 | #define __lcd_dav_set_vde(n) \ | ||
4665 | do { \ | ||
4666 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ | ||
4667 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ | ||
4668 | } while (0) | ||
4669 | |||
4670 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) | ||
4671 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) | ||
4672 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) | ||
4673 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) | ||
4674 | |||
4675 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) | ||
4676 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) | ||
4677 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) | ||
4678 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) | ||
4679 | |||
4680 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) | ||
4681 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) | ||
4682 | |||
4683 | #define __lcd_cmd0_get_len() \ | ||
4684 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) | ||
4685 | #define __lcd_cmd1_get_len() \ | ||
4686 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) | ||
4687 | |||
4688 | /*************************************************************************** | ||
4689 | * RTC ops | ||
4690 | ***************************************************************************/ | ||
4691 | |||
4692 | #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) | ||
4693 | #define __rtc_enabled() \ | ||
4694 | do{ \ | ||
4695 | while(!__rtc_write_ready()); \ | ||
4696 | REG_RTC_RCR |= RTC_RCR_RTCE ; \ | ||
4697 | }while(0) \ | ||
4698 | |||
4699 | #define __rtc_disabled() \ | ||
4700 | do{ \ | ||
4701 | while(!__rtc_write_ready()); \ | ||
4702 | REG_RTC_RCR &= ~RTC_RCR_RTCE; \ | ||
4703 | }while(0) | ||
4704 | #define __rtc_enable_alarm() \ | ||
4705 | do{ \ | ||
4706 | while(!__rtc_write_ready()); \ | ||
4707 | REG_RTC_RCR |= RTC_RCR_AE; \ | ||
4708 | }while(0) | ||
4709 | |||
4710 | #define __rtc_disable_alarm() \ | ||
4711 | do{ \ | ||
4712 | while(!__rtc_write_ready()); \ | ||
4713 | REG_RTC_RCR &= ~RTC_RCR_AE; \ | ||
4714 | }while(0) | ||
4715 | |||
4716 | #define __rtc_enable_alarm_irq() \ | ||
4717 | do{ \ | ||
4718 | while(!__rtc_write_ready()); \ | ||
4719 | REG_RTC_RCR |= RTC_RCR_AIE; \ | ||
4720 | }while(0) | ||
4721 | |||
4722 | #define __rtc_disable_alarm_irq() \ | ||
4723 | do{ \ | ||
4724 | while(!__rtc_write_ready()); \ | ||
4725 | REG_RTC_RCR &= ~RTC_RCR_AIE; \ | ||
4726 | }while(0) | ||
4727 | #define __rtc_enable_Hz_irq() \ | ||
4728 | do{ \ | ||
4729 | while(!__rtc_write_ready()); \ | ||
4730 | REG_RTC_RCR |= RTC_RCR_HZIE; \ | ||
4731 | }while(0) | ||
4732 | |||
4733 | #define __rtc_disable_Hz_irq() \ | ||
4734 | do{ \ | ||
4735 | while(!__rtc_write_ready()); \ | ||
4736 | REG_RTC_RCR &= ~RTC_RCR_HZIE; \ | ||
4737 | }while(0) | ||
4738 | #define __rtc_get_1Hz_flag() \ | ||
4739 | do{ \ | ||
4740 | while(!__rtc_write_ready()); \ | ||
4741 | ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ | ||
4742 | }while(0) | ||
4743 | #define __rtc_clear_1Hz_flag() \ | ||
4744 | do{ \ | ||
4745 | while(!__rtc_write_ready()); \ | ||
4746 | REG_RTC_RCR &= ~RTC_RCR_HZ; \ | ||
4747 | }while(0) | ||
4748 | #define __rtc_get_alarm_flag() \ | ||
4749 | do{ \ | ||
4750 | while(!__rtc_write_ready()); \ | ||
4751 | ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \ | ||
4752 | while(0) | ||
4753 | |||
4754 | ///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 ) | ||
4755 | |||
4756 | #define __rtc_clear_alarm_flag() \ | ||
4757 | do{ \ | ||
4758 | while(!__rtc_write_ready()); \ | ||
4759 | REG_RTC_RCR &= ~RTC_RCR_AF; \ | ||
4760 | }while(0) | ||
4761 | //do | ||
4762 | #define __rtc_get_second() \ | ||
4763 | ({ \ | ||
4764 | while(!__rtc_write_ready());\ | ||
4765 | REG_RTC_RSR; \ | ||
4766 | }) | ||
4767 | //while(0) | ||
4768 | |||
4769 | #define __rtc_set_second(v) \ | ||
4770 | do{ \ | ||
4771 | while(!__rtc_write_ready()); \ | ||
4772 | REG_RTC_RSR = v; \ | ||
4773 | while(!__rtc_write_ready());\ | ||
4774 | }while(0) | ||
4775 | |||
4776 | #define __rtc_get_alarm_second() \ | ||
4777 | do{ \ | ||
4778 | while(!__rtc_write_ready()); \ | ||
4779 | REG_RTC_RSAR; \ | ||
4780 | }while(0) | ||
4781 | |||
4782 | |||
4783 | #define __rtc_set_alarm_second(v) \ | ||
4784 | do{ \ | ||
4785 | while(!__rtc_write_ready()); \ | ||
4786 | REG_RTC_RSAR = v; \ | ||
4787 | }while(0) | ||
4788 | |||
4789 | #define __rtc_RGR_is_locked() \ | ||
4790 | ({ \ | ||
4791 | while(!__rtc_write_ready()); \ | ||
4792 | REG_RTC_RGR >> RTC_RGR_LOCK; \ | ||
4793 | }) | ||
4794 | #define __rtc_lock_RGR() \ | ||
4795 | do{ \ | ||
4796 | while(!__rtc_write_ready()); \ | ||
4797 | REG_RTC_RGR |= RTC_RGR_LOCK; \ | ||
4798 | }while(0) | ||
4799 | |||
4800 | #define __rtc_unlock_RGR() \ | ||
4801 | do{ \ | ||
4802 | while(!__rtc_write_ready()); \ | ||
4803 | REG_RTC_RGR &= ~RTC_RGR_LOCK; \ | ||
4804 | }while(0) | ||
4805 | |||
4806 | #define __rtc_get_adjc_val() \ | ||
4807 | do{ \ | ||
4808 | while(!__rtc_write_ready()); \ | ||
4809 | ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ | ||
4810 | }while(0) | ||
4811 | #define __rtc_set_adjc_val(v) \ | ||
4812 | do{ \ | ||
4813 | while(!__rtc_write_ready()); \ | ||
4814 | REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \ | ||
4815 | }while(0) | ||
4816 | |||
4817 | #define __rtc_get_nc1Hz_val() \ | ||
4818 | ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) | ||
4819 | |||
4820 | #define __rtc_set_nc1Hz_val(v) \ | ||
4821 | do{ \ | ||
4822 | while(!__rtc_write_ready()); \ | ||
4823 | REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\ | ||
4824 | }while(0) | ||
4825 | #define __rtc_power_down() \ | ||
4826 | do{ \ | ||
4827 | while(!__rtc_write_ready()); \ | ||
4828 | REG_RTC_HCR |= RTC_HCR_PD; \ | ||
4829 | }while(0) | ||
4830 | |||
4831 | #define __rtc_get_hwfcr_val() \ | ||
4832 | do{ \ | ||
4833 | while(!__rtc_write_ready()); \ | ||
4834 | REG_RTC_HWFCR & RTC_HWFCR_MASK; \ | ||
4835 | }while(0) | ||
4836 | #define __rtc_set_hwfcr_val(v) \ | ||
4837 | do{ \ | ||
4838 | while(!__rtc_write_ready()); \ | ||
4839 | REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ | ||
4840 | }while(0) | ||
4841 | |||
4842 | #define __rtc_get_hrcr_val() \ | ||
4843 | do{ \ | ||
4844 | while(!__rtc_write_ready()); \ | ||
4845 | ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ | ||
4846 | }while(0) | ||
4847 | #define __rtc_set_hrcr_val(v) \ | ||
4848 | do{ \ | ||
4849 | while(!__rtc_write_ready()); \ | ||
4850 | ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ | ||
4851 | }while(0) | ||
4852 | |||
4853 | #define __rtc_enable_alarm_wakeup() \ | ||
4854 | do{ \ | ||
4855 | while(!__rtc_write_ready()); \ | ||
4856 | ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ | ||
4857 | }while(0) | ||
4858 | |||
4859 | #define __rtc_disable_alarm_wakeup() \ | ||
4860 | do{ \ | ||
4861 | while(!__rtc_write_ready()); \ | ||
4862 | ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ | ||
4863 | }while(0) | ||
4864 | |||
4865 | #define __rtc_status_hib_reset_occur() \ | ||
4866 | ({ \ | ||
4867 | (REG_RTC_HWRSR & RTC_HWRSR_HR); \ | ||
4868 | }) | ||
4869 | #define __rtc_status_ppr_reset_occur() \ | ||
4870 | do{ \ | ||
4871 | while(!__rtc_write_ready()); \ | ||
4872 | ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \ | ||
4873 | }while(0) | ||
4874 | #define __rtc_status_wakeup_pin_waken_up() \ | ||
4875 | do{ \ | ||
4876 | while(!__rtc_write_ready()); \ | ||
4877 | ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ | ||
4878 | }while(0) | ||
4879 | #define __rtc_status_alarm_waken_up() \ | ||
4880 | do{ \ | ||
4881 | while(!__rtc_write_ready()); \ | ||
4882 | ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ | ||
4883 | }while(0) | ||
4884 | #define __rtc_clear_hib_stat_all() \ | ||
4885 | do{ \ | ||
4886 | while(!__rtc_write_ready()); \ | ||
4887 | ( REG_RTC_HWRSR = 0 ); \ | ||
4888 | }while(0) | ||
4889 | |||
4890 | #define __rtc_get_scratch_pattern() \ | ||
4891 | ({ while(!__rtc_write_ready()); \ | ||
4892 | (REG_RTC_HSPR);}) | ||
4893 | #define __rtc_set_scratch_pattern(n) \ | ||
4894 | do{ \ | ||
4895 | while(!__rtc_write_ready()); \ | ||
4896 | (REG_RTC_HSPR = n ); \ | ||
4897 | }while(0) | ||
4898 | |||
4899 | |||
4900 | #endif /* !__ASSEMBLY__ */ | ||
4901 | |||
4902 | #endif /* __JZ4740_H__ */ | ||
diff --git a/firmware/export/mips-archdefs.h b/firmware/export/mips-archdefs.h new file mode 100755 index 0000000000..37c61b87e5 --- /dev/null +++ b/firmware/export/mips-archdefs.h | |||
@@ -0,0 +1,2356 @@ | |||
1 | /************************************************************************** | ||
2 | * * | ||
3 | * PROJECT : MIPS port for uC/OS-II * | ||
4 | * * | ||
5 | * MODULE : ARCHDEFS.h * | ||
6 | * * | ||
7 | * AUTHOR : Michael Anburaj * | ||
8 | * URL : http://geocities.com/michaelanburaj/ * | ||
9 | * EMAIL: michaelanburaj@hotmail.com * | ||
10 | * * | ||
11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * | ||
12 | * * | ||
13 | * TOOL-CHAIN : SDE & Cygnus * | ||
14 | * * | ||
15 | * DESCRIPTION : * | ||
16 | * Architecture definitions. * | ||
17 | * * | ||
18 | **************************************************************************/ | ||
19 | |||
20 | |||
21 | #ifndef __ARCHDEFS_H__ | ||
22 | #define __ARCHDEFS_H__ | ||
23 | |||
24 | |||
25 | /* ********************************************************************* */ | ||
26 | /* Module configuration */ | ||
27 | |||
28 | |||
29 | /* ********************************************************************* */ | ||
30 | /* Interface macro & data definition */ | ||
31 | |||
32 | /* | ||
33 | * Utility defines for cross platform handling of 64bit constants. | ||
34 | */ | ||
35 | |||
36 | #if !defined(Append) | ||
37 | #define Append(c,s) (c##s) | ||
38 | #endif | ||
39 | |||
40 | #if !defined(__assembler) && !defined(MIPSAVPENV) | ||
41 | #if defined(NT) | ||
42 | #if !defined(UNS64Const) | ||
43 | #define UNS64Const(c) Append(c,ui64) | ||
44 | #endif | ||
45 | |||
46 | #if !defined(INT64Const) | ||
47 | #define INT64Const(c) Append(c,i64) | ||
48 | #endif | ||
49 | #else | ||
50 | #if !defined(UNS64Const) | ||
51 | #define UNS64Const(c) Append(c,ull) | ||
52 | #endif | ||
53 | |||
54 | #if !defined(INT64Const) | ||
55 | #define INT64Const(c) Append(c,ll) | ||
56 | #endif | ||
57 | #endif | ||
58 | #else /* Not C or C++ */ | ||
59 | #if !defined(UNS64Const) | ||
60 | #define UNS64Const(c) c | ||
61 | #endif | ||
62 | |||
63 | #if !defined(INT64Const) | ||
64 | #define INT64Const(c) c | ||
65 | #endif | ||
66 | #endif /* C or C++ */ | ||
67 | |||
68 | |||
69 | /* | ||
70 | ************************************************************************ | ||
71 | * I N S T R U C T I O N F O R M A T S * | ||
72 | ************************************************************************ | ||
73 | * | ||
74 | * The following definitions describe each field in an instruction. There | ||
75 | * is one diagram for each type of instruction, with field definitions | ||
76 | * following the diagram for that instruction. Note that if a field of | ||
77 | * the same name and position is defined in an earlier diagram, it is | ||
78 | * not defined again in the subsequent diagram. Only new fields are | ||
79 | * defined for each diagram. | ||
80 | * | ||
81 | * R-Type (operate) | ||
82 | * | ||
83 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
84 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
85 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
86 | * | | rs | rt | rd | sa | | | ||
87 | * | Opcode | | | Tcode | func | | ||
88 | * | | Bcode | | sel | | ||
89 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
90 | */ | ||
91 | |||
92 | #define S_InstnOpcode 26 | ||
93 | #define M_InstnOpcode (0x3f << S_InstnOpcode) | ||
94 | #define S_InstnRS 21 | ||
95 | #define M_InstnRS (0x1f << S_InstnRS) | ||
96 | #define S_InstnRT 16 | ||
97 | #define M_InstnRT (0x1f << S_InstnRT) | ||
98 | #define S_InstnRD 11 | ||
99 | #define M_InstnRD (0x1f << S_InstnRD) | ||
100 | #define S_InstnSA 6 | ||
101 | #define M_InstnSA (0x1f << S_InstnSA) | ||
102 | #define S_InstnTcode 6 | ||
103 | #define M_InstnTcode (0x3ff << S_InstnTcode) | ||
104 | #define S_InstnBcode 6 | ||
105 | #define M_InstnBcode (0xfffff << S_InstnBcode) | ||
106 | #define S_InstnFunc 0 | ||
107 | #define M_InstnFunc (0x3f << S_InstnFunc) | ||
108 | #define S_InstnSel 0 | ||
109 | #define M_InstnSel (0x7 << S_InstnSel) | ||
110 | |||
111 | /* | ||
112 | * I-Type (load, store, branch, immediate) | ||
113 | * | ||
114 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
115 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
116 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
117 | * | Opcode | rs | rt | Offset | | ||
118 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
119 | */ | ||
120 | |||
121 | #define S_InstnOffset 0 | ||
122 | #define M_InstnOffset (0xffff << S_InstnOffset) | ||
123 | |||
124 | /* | ||
125 | * I-Type (pref) | ||
126 | * | ||
127 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
128 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
129 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
130 | * | Opcode | rs | hint | Offset | | ||
131 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
132 | */ | ||
133 | |||
134 | #define S_InstnHint S_InstnRT | ||
135 | #define M_InstnHint M_InstnRT | ||
136 | |||
137 | /* | ||
138 | * J-Type (jump) | ||
139 | * | ||
140 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
141 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
142 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
143 | * | Opcode | JIndex | | ||
144 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
145 | */ | ||
146 | |||
147 | #define S_InstnJIndex 0 | ||
148 | #define M_InstnJIndex (0x03ffffff << S_InstnJIndex) | ||
149 | |||
150 | /* | ||
151 | * FP R-Type (operate) | ||
152 | * | ||
153 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
154 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
155 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
156 | * | Opcode | fmt | ft | fs | fd | func | | ||
157 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
158 | */ | ||
159 | |||
160 | #define S_InstnFmt S_InstnRS | ||
161 | #define M_InstnFmt M_InstnRS | ||
162 | #define S_InstnFT S_InstnRT | ||
163 | #define M_InstnFT M_InstnRT | ||
164 | #define S_InstnFS S_InstnRD | ||
165 | #define M_InstnFS M_InstnRD | ||
166 | #define S_InstnFD S_InstnSA | ||
167 | #define M_InstnFD M_InstnSA | ||
168 | |||
169 | /* | ||
170 | * FP R-Type (cpu <-> cpu data movement)) | ||
171 | * | ||
172 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
173 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
174 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
175 | * | Opcode | sub | rt | fs | 0 | | ||
176 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
177 | */ | ||
178 | |||
179 | #define S_InstnSub S_InstnRS | ||
180 | #define M_InstnSub M_InstnRS | ||
181 | |||
182 | /* | ||
183 | * FP R-Type (compare) | ||
184 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
185 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
186 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
187 | * | | | | | | |C| | | ||
188 | * | Opcode | fmt | ft | fs | cc |0|A| func | | ||
189 | * | | | | | | |B| | | ||
190 | * | | | | | | |S| | | ||
191 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
192 | */ | ||
193 | |||
194 | #define S_InstnCCcmp 8 | ||
195 | #define M_InstnCCcmp (0x7 << S_InstnCCcmp) | ||
196 | #define S_InstnCABS 6 | ||
197 | #define M_InstnCABS (0x1 << S_InstnCABS) | ||
198 | |||
199 | /* | ||
200 | * FP R-Type (FPR conditional move on FP cc) | ||
201 | * | ||
202 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
203 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
204 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
205 | * | Opcode | fmt | cc |n|t| fs | fd | func | | ||
206 | * | | | |d|f| | | | | ||
207 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
208 | */ | ||
209 | |||
210 | #define S_InstnCC 18 | ||
211 | #define M_InstnCC (0x7 << S_InstnCC) | ||
212 | #define S_InstnND 17 | ||
213 | #define M_InstnND (0x1 << S_InstnND) | ||
214 | #define S_InstnTF 16 | ||
215 | #define M_InstnTF (0x1 << S_InstnTF) | ||
216 | |||
217 | /* | ||
218 | * FP R-Type (3-operand operate) | ||
219 | * | ||
220 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
221 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
222 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
223 | * | Opcode | fr | ft | fs | fd | op4 | fmt3| | ||
224 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
225 | */ | ||
226 | |||
227 | #define S_InstnFR S_InstnRS | ||
228 | #define M_InstnFR M_InstnRS | ||
229 | #define S_InstnOp4 3 | ||
230 | #define M_InstnOp4 (0x7 << S_InstnOp4) | ||
231 | #define S_InstnFmt3 0 | ||
232 | #define M_InstnFmt3 (0x7 << S_InstnFmt3) | ||
233 | |||
234 | /* | ||
235 | * FP R-Type (Indexed load, store) | ||
236 | * | ||
237 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
238 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
239 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
240 | * | Opcode | rs | rt | 0 | fd | func | | ||
241 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
242 | */ | ||
243 | /* | ||
244 | * FP R-Type (prefx) | ||
245 | * | ||
246 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
247 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
248 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
249 | * | Opcode | rs | rt | hint | 0 | func | | ||
250 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
251 | */ | ||
252 | |||
253 | #define S_InstnHintX S_InstnRD | ||
254 | #define M_InstnHintX M_InstnRD | ||
255 | |||
256 | /* | ||
257 | * FP R-Type (GPR conditional move on FP cc) | ||
258 | * | ||
259 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
260 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
261 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
262 | * | Opcode | rs | cc |n|t| rd | 0 | func | | ||
263 | * | | | |d|f| | | | | ||
264 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
265 | */ | ||
266 | |||
267 | /* | ||
268 | * FP I-Type (load, store) | ||
269 | * | ||
270 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
271 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
272 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
273 | * | Opcode | rs | ft | Offset | | ||
274 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
275 | */ | ||
276 | |||
277 | /* | ||
278 | * FP I-Type (branch) | ||
279 | * | ||
280 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
281 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
282 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
283 | * | Opcode | fmt | cc |n|t| Offset | | ||
284 | * | | | |d|f| | | ||
285 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
286 | */ | ||
287 | |||
288 | |||
289 | /* | ||
290 | ************************************************************************* | ||
291 | * V I R T U A L A D D R E S S D E F I N I T I O N S * | ||
292 | ************************************************************************* | ||
293 | */ | ||
294 | |||
295 | #ifdef MIPSADDR64 | ||
296 | #define A_K0BASE UNS64Const(0xffffffff80000000) | ||
297 | #define A_K1BASE UNS64Const(0xffffffffa0000000) | ||
298 | #define A_K2BASE UNS64Const(0xffffffffc0000000) | ||
299 | #define A_K3BASE UNS64Const(0xffffffffe0000000) | ||
300 | #define A_REGION UNS64Const(0xc000000000000000) | ||
301 | #define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) | ||
302 | #else | ||
303 | #define A_K0BASE 0x80000000 | ||
304 | #define A_K1BASE 0xa0000000 | ||
305 | #define A_K2BASE 0xc0000000 | ||
306 | #define A_K3BASE 0xe0000000 | ||
307 | #endif | ||
308 | #define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ | ||
309 | |||
310 | |||
311 | #ifdef MIPS_Model64 | ||
312 | |||
313 | #define S_VMAP64 62 | ||
314 | #define M_VMAP64 UNS64Const(0xc000000000000000) | ||
315 | |||
316 | #define K_VMode11 3 | ||
317 | #define K_VMode10 2 | ||
318 | #define K_VMode01 1 | ||
319 | #define K_VMode00 0 | ||
320 | |||
321 | #define S_KSEG3 29 | ||
322 | #define M_KSEG3 (0x7 << S_KSEG3) | ||
323 | #define K_KSEG3 7 | ||
324 | |||
325 | #define S_SSEG 29 | ||
326 | #define M_SSEG (0x7 << S_KSEG3) | ||
327 | #define K_SSEG 6 | ||
328 | |||
329 | #define S_KSSEG 29 | ||
330 | #define M_KSSEG (0x7 << S_KSEG3) | ||
331 | #define K_KSSEG 6 | ||
332 | |||
333 | #define S_KSEG1 29 | ||
334 | #define M_KSEG1 (0x7 << S_KSEG3) | ||
335 | #define K_KSEG1 5 | ||
336 | |||
337 | #define S_KSEG0 29 | ||
338 | #define M_KSEG0 (0x7 << S_KSEG3) | ||
339 | #define K_KSEG0 4 | ||
340 | |||
341 | #define S_XKSEG 29 | ||
342 | #define M_XKSEG (0x7 << S_KSEG3) | ||
343 | #define K_XKSEG 3 | ||
344 | |||
345 | #define S_USEG 31 | ||
346 | #define M_USEG (0x1 << S_USEG) | ||
347 | #define K_USEG 0 | ||
348 | |||
349 | #define S_EjtagProbeMem 20 | ||
350 | #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) | ||
351 | #define K_EjtagProbeMem 0 | ||
352 | |||
353 | |||
354 | |||
355 | #else | ||
356 | |||
357 | #define S_KSEG3 29 | ||
358 | #define M_KSEG3 (0x7 << S_KSEG3) | ||
359 | #define K_KSEG3 7 | ||
360 | |||
361 | #define S_KSSEG 29 | ||
362 | #define M_KSSEG (0x7 << S_KSSEG) | ||
363 | #define K_KSSEG 6 | ||
364 | |||
365 | #define S_SSEG 29 | ||
366 | #define M_SSEG (0x7 << S_SSEG) | ||
367 | #define K_SSEG 6 | ||
368 | |||
369 | #define S_KSEG1 29 | ||
370 | #define M_KSEG1 (0x7 << S_KSEG1) | ||
371 | #define K_KSEG1 5 | ||
372 | |||
373 | #define S_KSEG0 29 | ||
374 | #define M_KSEG0 (0x7 << S_KSEG0) | ||
375 | #define K_KSEG0 4 | ||
376 | |||
377 | #define S_KUSEG 31 | ||
378 | #define M_KUSEG (0x1 << S_KUSEG) | ||
379 | #define K_KUSEG 0 | ||
380 | |||
381 | #define S_SUSEG 31 | ||
382 | #define M_SUSEG (0x1 << S_SUSEG) | ||
383 | #define K_SUSEG 0 | ||
384 | |||
385 | #define S_USEG 31 | ||
386 | #define M_USEG (0x1 << S_USEG) | ||
387 | #define K_USEG 0 | ||
388 | |||
389 | #define K_EjtagLower 0xff200000 | ||
390 | #define K_EjtagUpper 0xff3fffff | ||
391 | |||
392 | #define S_EjtagProbeMem 20 | ||
393 | #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) | ||
394 | #define K_EjtagProbeMem 0 | ||
395 | |||
396 | #endif | ||
397 | |||
398 | |||
399 | |||
400 | /* | ||
401 | ************************************************************************* | ||
402 | * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * | ||
403 | ************************************************************************* | ||
404 | */ | ||
405 | |||
406 | /* | ||
407 | * Cache encodings | ||
408 | */ | ||
409 | #define K_CachePriI 0 /* Primary Icache */ | ||
410 | #define K_CachePriD 1 /* Primary Dcache */ | ||
411 | #define K_CachePriU 1 /* Unified primary */ | ||
412 | #define K_CacheTerU 2 /* Unified Tertiary */ | ||
413 | #define K_CacheSecU 3 /* Unified secondary */ | ||
414 | |||
415 | |||
416 | /* | ||
417 | * Function encodings | ||
418 | */ | ||
419 | #define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ | ||
420 | #define K_CacheIndexInv 0 /* Index invalidate */ | ||
421 | #define K_CacheIndexWBInv 0 /* Index writeback invalidate */ | ||
422 | #define K_CacheIndexLdTag 1 /* Index load tag */ | ||
423 | #define K_CacheIndexStTag 2 /* Index store tag */ | ||
424 | #define K_CacheHitInv 4 /* Hit Invalidate */ | ||
425 | #define K_CacheFill 5 /* Fill (Icache only) */ | ||
426 | #define K_CacheHitWBInv 5 /* Hit writeback invalidate */ | ||
427 | #define K_CacheHitWB 6 /* Hit writeback */ | ||
428 | #define K_CacheFetchLock 7 /* Fetch and lock */ | ||
429 | |||
430 | #define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) | ||
431 | #define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) | ||
432 | #define DCIndexInv DCIndexWBInv | ||
433 | #define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) | ||
434 | #define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) | ||
435 | #define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) | ||
436 | #define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) | ||
437 | #define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) | ||
438 | #define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) | ||
439 | #define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) | ||
440 | #define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) | ||
441 | #define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) | ||
442 | #define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) | ||
443 | #define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) | ||
444 | |||
445 | |||
446 | /* | ||
447 | ************************************************************************* | ||
448 | * P R E F E T C H I N S T R U C T I O N H I N T S * | ||
449 | ************************************************************************* | ||
450 | */ | ||
451 | |||
452 | #define PrefLoad 0 | ||
453 | #define PrefStore 1 | ||
454 | #define PrefLoadStreamed 4 | ||
455 | #define PrefStoreStreamed 5 | ||
456 | #define PrefLoadRetained 6 | ||
457 | #define PrefStoreRetained 7 | ||
458 | #define PrefWBInval 25 | ||
459 | #define PrefNudge 25 | ||
460 | |||
461 | |||
462 | /* | ||
463 | ************************************************************************* | ||
464 | * C P U R E G I S T E R D E F I N I T I O N S * | ||
465 | ************************************************************************* | ||
466 | */ | ||
467 | |||
468 | |||
469 | /* | ||
470 | ************************************************************************* | ||
471 | * S O F T W A R E G P R N A M E S * | ||
472 | ************************************************************************* | ||
473 | */ | ||
474 | |||
475 | #define zero $0 | ||
476 | #define AT $1 | ||
477 | #define v0 $2 | ||
478 | #define v1 $3 | ||
479 | #define a0 $4 | ||
480 | #define a1 $5 | ||
481 | #define a2 $6 | ||
482 | #define a3 $7 | ||
483 | #define t0 $8 | ||
484 | #define t1 $9 | ||
485 | #define t2 $10 | ||
486 | #define t3 $11 | ||
487 | #define t4 $12 | ||
488 | #define t5 $13 | ||
489 | #define t6 $14 | ||
490 | #define t7 $15 | ||
491 | #define s0 $16 | ||
492 | #define s1 $17 | ||
493 | #define s2 $18 | ||
494 | #define s3 $19 | ||
495 | #define s4 $20 | ||
496 | #define s5 $21 | ||
497 | #define s6 $22 | ||
498 | #define s7 $23 | ||
499 | #define t8 $24 | ||
500 | #define t9 $25 | ||
501 | #define k0 $26 | ||
502 | #define k1 $27 | ||
503 | #define gp $28 | ||
504 | #define sp $29 | ||
505 | #define fp $30 | ||
506 | #define ra $31 | ||
507 | |||
508 | /* | ||
509 | * The following registers are used by the AVP environment and | ||
510 | * are not part of the normal software definitions. | ||
511 | */ | ||
512 | |||
513 | #ifdef MIPSAVPENV | ||
514 | #define repc $25 /* Expected exception PC */ | ||
515 | #define tid $30 /* Current test case address */ | ||
516 | #endif | ||
517 | |||
518 | |||
519 | /* | ||
520 | ************************************************************************* | ||
521 | * H A R D W A R E G P R N A M E S * | ||
522 | ************************************************************************* | ||
523 | * | ||
524 | * In the AVP environment, several of the `r' names are removed from the | ||
525 | * name space because they are used by the kernel for special purposes. | ||
526 | * Removing them causes assembly rather than runtime errors for tests that | ||
527 | * use the `r' names. | ||
528 | * | ||
529 | * - r25 (repc) is used as the expected PC on an exception | ||
530 | * - r26-r27 (k0, k1) are used in the exception handler | ||
531 | * - r30 (tid) is used as the current test address | ||
532 | */ | ||
533 | |||
534 | #define r0 $0 | ||
535 | #define r1 $1 | ||
536 | #define r2 $2 | ||
537 | #define r3 $3 | ||
538 | #define r4 $4 | ||
539 | #define r5 $5 | ||
540 | #define r6 $6 | ||
541 | #define r7 $7 | ||
542 | #define r8 $8 | ||
543 | #define r9 $9 | ||
544 | #define r10 $10 | ||
545 | #define r11 $11 | ||
546 | #define r12 $12 | ||
547 | #define r13 $13 | ||
548 | #define r14 $14 | ||
549 | #define r15 $15 | ||
550 | #define r16 $16 | ||
551 | #define r17 $17 | ||
552 | #define r18 $18 | ||
553 | #define r19 $19 | ||
554 | #define r20 $20 | ||
555 | #define r21 $21 | ||
556 | #define r22 $22 | ||
557 | #define r23 $23 | ||
558 | #define r24 $24 | ||
559 | #ifdef MIPSAVPENV | ||
560 | #define r25 r25_unknown | ||
561 | #define r26 r26_unknown | ||
562 | #define r27 r27_unknown | ||
563 | #else | ||
564 | #define r25 $25 | ||
565 | #define r26 $26 | ||
566 | #define r27 $27 | ||
567 | #endif | ||
568 | #define r28 $28 | ||
569 | #define r29 $29 | ||
570 | #ifdef MIPSAVPENV | ||
571 | #define r30 r30_unknown | ||
572 | #else | ||
573 | #define r30 $30 | ||
574 | #endif | ||
575 | #define r31 $31 | ||
576 | |||
577 | |||
578 | /* | ||
579 | ************************************************************************* | ||
580 | * H A R D W A R E G P R I N D I C E S * | ||
581 | ************************************************************************* | ||
582 | * | ||
583 | * These definitions provide the index (number) of the GPR, as opposed | ||
584 | * to the assembler register name ($n). | ||
585 | */ | ||
586 | |||
587 | #define R_r0 0 | ||
588 | #define R_r1 1 | ||
589 | #define R_r2 2 | ||
590 | #define R_r3 3 | ||
591 | #define R_r4 4 | ||
592 | #define R_r5 5 | ||
593 | #define R_r6 6 | ||
594 | #define R_r7 7 | ||
595 | #define R_r8 8 | ||
596 | #define R_r9 9 | ||
597 | #define R_r10 10 | ||
598 | #define R_r11 11 | ||
599 | #define R_r12 12 | ||
600 | #define R_r13 13 | ||
601 | #define R_r14 14 | ||
602 | #define R_r15 15 | ||
603 | #define R_r16 16 | ||
604 | #define R_r17 17 | ||
605 | #define R_r18 18 | ||
606 | #define R_r19 19 | ||
607 | #define R_r20 20 | ||
608 | #define R_r21 21 | ||
609 | #define R_r22 22 | ||
610 | #define R_r23 23 | ||
611 | #define R_r24 24 | ||
612 | #define R_r25 25 | ||
613 | #define R_r26 26 | ||
614 | #define R_r27 27 | ||
615 | #define R_r28 28 | ||
616 | #define R_r29 29 | ||
617 | #define R_r30 30 | ||
618 | #define R_r31 31 | ||
619 | #define R_hi 32 /* Hi register */ | ||
620 | #define R_lo 33 /* Lo register */ | ||
621 | |||
622 | |||
623 | /* | ||
624 | ************************************************************************* | ||
625 | * S O F T W A R E G P R M A S K S * | ||
626 | ************************************************************************* | ||
627 | * | ||
628 | * These definitions provide the bit mask corresponding to the GPR number | ||
629 | */ | ||
630 | |||
631 | #define M_AT (1<<1) | ||
632 | #define M_v0 (1<<2) | ||
633 | #define M_v1 (1<<3) | ||
634 | #define M_a0 (1<<4) | ||
635 | #define M_a1 (1<<5) | ||
636 | #define M_a2 (1<<6) | ||
637 | #define M_a3 (1<<7) | ||
638 | #define M_t0 (1<<8) | ||
639 | #define M_t1 (1<<9) | ||
640 | #define M_t2 (1<<10) | ||
641 | #define M_t3 (1<<11) | ||
642 | #define M_t4 (1<<12) | ||
643 | #define M_t5 (1<<13) | ||
644 | #define M_t6 (1<<14) | ||
645 | #define M_t7 (1<<15) | ||
646 | #define M_s0 (1<<16) | ||
647 | #define M_s1 (1<<17) | ||
648 | #define M_s2 (1<<18) | ||
649 | #define M_s3 (1<<19) | ||
650 | #define M_s4 (1<<20) | ||
651 | #define M_s5 (1<<21) | ||
652 | #define M_s6 (1<<22) | ||
653 | #define M_s7 (1<<23) | ||
654 | #define M_t8 (1<<24) | ||
655 | #define M_t9 (1<<25) | ||
656 | #define M_k0 (1<<26) | ||
657 | #define M_k1 (1<<27) | ||
658 | #define M_gp (1<<28) | ||
659 | #define M_sp (1<<29) | ||
660 | #define M_fp (1<<30) | ||
661 | #define M_ra (1<<31) | ||
662 | |||
663 | |||
664 | /* | ||
665 | ************************************************************************* | ||
666 | * C P 0 R E G I S T E R D E F I N I T I O N S * | ||
667 | ************************************************************************* | ||
668 | * Each register has the following definitions: | ||
669 | * | ||
670 | * C0_rrr The register number (as a $n value) | ||
671 | * R_C0_rrr The register index (as an integer corresponding | ||
672 | * to the register number) | ||
673 | * | ||
674 | * Each field in a register has the following definitions: | ||
675 | * | ||
676 | * S_rrrfff The shift count required to right-justify | ||
677 | * the field. This corresponds to the bit | ||
678 | * number of the right-most bit in the field. | ||
679 | * M_rrrfff The Mask required to isolate the field. | ||
680 | * | ||
681 | * Register diagrams included below as comments correspond to the | ||
682 | * MIPS32 and MIPS64 architecture specifications. Refer to other | ||
683 | * sources for register diagrams for older architectures. | ||
684 | */ | ||
685 | |||
686 | |||
687 | /* | ||
688 | ************************************************************************ | ||
689 | * I N D E X R E G I S T E R ( 0 ) * | ||
690 | ************************************************************************ | ||
691 | * | ||
692 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
693 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
694 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
695 | * |P| 0 | Index | Index | ||
696 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
697 | */ | ||
698 | |||
699 | #define C0_Index $0 | ||
700 | #define R_C0_Index 0 | ||
701 | #define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
702 | |||
703 | #define S_IndexP 31 /* Probe failure (R)*/ | ||
704 | #define M_IndexP (0x1 << S_IndexP) | ||
705 | |||
706 | #define S_IndexIndex 0 /* TLB index (R/W)*/ | ||
707 | #define M_IndexIndex (0x3f << S_IndexIndex) | ||
708 | |||
709 | #define M_Index0Fields 0x7fffffc0 | ||
710 | #define M_IndexRFields 0x80000000 | ||
711 | |||
712 | |||
713 | /* | ||
714 | ************************************************************************ | ||
715 | * R A N D O M R E G I S T E R ( 1 ) * | ||
716 | ************************************************************************ | ||
717 | * | ||
718 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
719 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
720 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
721 | * | 0 | Index | Random | ||
722 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
723 | */ | ||
724 | |||
725 | #define C0_Random $1 | ||
726 | #define R_C0_Random 1 | ||
727 | #define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
728 | |||
729 | #define S_RandomIndex 0 /* TLB random index (R)*/ | ||
730 | #define M_RandomIndex (0x3f << S_RandomIndex) | ||
731 | |||
732 | #define M_Random0Fields 0xffffffc0 | ||
733 | #define M_RandomRFields 0x0000003f | ||
734 | |||
735 | |||
736 | /* | ||
737 | ************************************************************************ | ||
738 | * E N T R Y L O 0 R E G I S T E R ( 2 ) * | ||
739 | ************************************************************************ | ||
740 | * | ||
741 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
742 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
743 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
744 | * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 | ||
745 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
746 | */ | ||
747 | |||
748 | #define C0_EntryLo0 $2 | ||
749 | #define R_C0_EntryLo0 2 | ||
750 | #define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
751 | |||
752 | #define S_EntryLoPFN 6 /* PFN (R/W) */ | ||
753 | #define M_EntryLoPFN (0xffffff << S_EntryLoPFN) | ||
754 | #define S_EntryLoC 3 /* Coherency attribute (R/W) */ | ||
755 | #define M_EntryLoC (0x7 << S_EntryLoC) | ||
756 | #define S_EntryLoD 2 /* Dirty (R/W) */ | ||
757 | #define M_EntryLoD (0x1 << S_EntryLoD) | ||
758 | #define S_EntryLoV 1 /* Valid (R/W) */ | ||
759 | #define M_EntryLoV (0x1 << S_EntryLoV) | ||
760 | #define S_EntryLoG 0 /* Global (R/W) */ | ||
761 | #define M_EntryLoG (0x1 << S_EntryLoG) | ||
762 | #define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ | ||
763 | #define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ | ||
764 | #define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ | ||
765 | |||
766 | #define M_EntryLo0Fields 0x00000000 | ||
767 | #define M_EntryLoRFields 0xc0000000 | ||
768 | #define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) | ||
769 | #define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) | ||
770 | |||
771 | /* | ||
772 | * Cache attribute values in the C field of EntryLo and the | ||
773 | * K0 field of Config | ||
774 | */ | ||
775 | #define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ | ||
776 | #define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ | ||
777 | #define K_CacheAttrU 2 /* Uncached */ | ||
778 | #define K_CacheAttrC 3 /* Cacheable */ | ||
779 | #define K_CacheAttrCN 3 /* Cacheable, non-coherent */ | ||
780 | #define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ | ||
781 | #define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ | ||
782 | #define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ | ||
783 | #define K_CacheAttrUA 7 /* Uncached accelerated */ | ||
784 | |||
785 | |||
786 | /* | ||
787 | ************************************************************************ | ||
788 | * E N T R Y L O 1 R E G I S T E R ( 3 ) * | ||
789 | ************************************************************************ | ||
790 | * | ||
791 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
792 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
793 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
794 | * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 | ||
795 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
796 | */ | ||
797 | |||
798 | #define C0_EntryLo1 $3 | ||
799 | #define R_C0_EntryLo1 3 | ||
800 | #define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
801 | |||
802 | /* | ||
803 | * Field definitions are as given for EntryLo0 above | ||
804 | */ | ||
805 | |||
806 | |||
807 | /* | ||
808 | ************************************************************************ | ||
809 | * C O N T E X T R E G I S T E R ( 4 ) * | ||
810 | ************************************************************************ | ||
811 | * | ||
812 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
813 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
814 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
815 | * | // PTEBase | BadVPN<31:13> | 0 | Context | ||
816 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
817 | */ | ||
818 | |||
819 | #define C0_Context $4 | ||
820 | #define R_C0_Context 4 | ||
821 | #define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
822 | |||
823 | #define S_ContextPTEBase 23 /* PTE base (R/W) */ | ||
824 | #define M_ContextPTEBase (0x1ff << S_ContextPTEBase) | ||
825 | #define S_ContextBadVPN 4 /* BadVPN2 (R) */ | ||
826 | #define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) | ||
827 | #define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ | ||
828 | #define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ | ||
829 | |||
830 | #define M_Context0Fields 0x0000000f | ||
831 | #define M_ContextRFields 0x007ffff0 | ||
832 | #define M_Context0Fields64 UNS64Const(0x000000000000000f) | ||
833 | #define M_ContextRFields64 UNS64Const(0x00000000007ffff0) | ||
834 | |||
835 | |||
836 | /* | ||
837 | ************************************************************************ | ||
838 | * P A G E M A S K R E G I S T E R ( 5 ) * | ||
839 | ************************************************************************ | ||
840 | * | ||
841 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
842 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
843 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
844 | * | 0 | Mask | 0 | PageMask | ||
845 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
846 | */ | ||
847 | |||
848 | #define C0_PageMask $5 | ||
849 | #define R_C0_PageMask 5 /* Mask (R/W) */ | ||
850 | #define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
851 | |||
852 | #define S_PageMaskMask 13 | ||
853 | #define M_PageMaskMask (0xfff << S_PageMaskMask) | ||
854 | |||
855 | #define M_PageMask0Fields 0xfe001fff | ||
856 | #define M_PageMaskRFields 0x00000000 | ||
857 | |||
858 | /* | ||
859 | * Values in the Mask field | ||
860 | */ | ||
861 | #define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ | ||
862 | #define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ | ||
863 | #define K_PageMask64K 0x00f | ||
864 | #define K_PageMask256K 0x03f | ||
865 | #define K_PageMask1M 0x0ff | ||
866 | #define K_PageMask4M 0x3ff | ||
867 | #define K_PageMask16M 0xfff | ||
868 | |||
869 | #define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ | ||
870 | #define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ | ||
871 | #define M_PageMask64K (K_PageMask64K << S_PageMaskMask) | ||
872 | #define M_PageMask256K (K_PageMask256K << S_PageMaskMask) | ||
873 | #define M_PageMask1M (K_PageMask1M << S_PageMaskMask) | ||
874 | #define M_PageMask4M (K_PageMask4M << S_PageMaskMask) | ||
875 | #define M_PageMask16M (K_PageMask16M << S_PageMaskMask) | ||
876 | |||
877 | |||
878 | /* | ||
879 | ************************************************************************ | ||
880 | * W I R E D R E G I S T E R ( 6 ) * | ||
881 | ************************************************************************ | ||
882 | * | ||
883 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
884 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
885 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
886 | * | 0 | Index | Wired | ||
887 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
888 | */ | ||
889 | |||
890 | #define C0_Wired $6 | ||
891 | #define R_C0_Wired 6 | ||
892 | #define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
893 | |||
894 | #define S_WiredIndex 0 /* TLB wired boundary (R/W) */ | ||
895 | #define M_WiredIndex (0x3f << S_WiredIndex) | ||
896 | |||
897 | #define M_Wired0Fields 0xffffffc0 | ||
898 | #define M_WiredRFields 0x00000000 | ||
899 | |||
900 | |||
901 | /* | ||
902 | ************************************************************************ | ||
903 | * B A D V A D D R R E G I S T E R ( 8 ) * | ||
904 | ************************************************************************ | ||
905 | * | ||
906 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
907 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
908 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
909 | * | // Bad Virtual Address | BadVAddr | ||
910 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
911 | */ | ||
912 | |||
913 | #define C0_BadVAddr $8 | ||
914 | #define R_C0_BadVAddr 8 | ||
915 | #define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
916 | |||
917 | #define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ | ||
918 | |||
919 | #define M_BadVAddr0Fields 0x00000000 | ||
920 | #define M_BadVAddrRFields 0xffffffff | ||
921 | #define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) | ||
922 | #define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) | ||
923 | |||
924 | /* | ||
925 | ************************************************************************ | ||
926 | * C O U N T R E G I S T E R ( 9 ) * | ||
927 | ************************************************************************ | ||
928 | * | ||
929 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
930 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
931 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
932 | * | Count Value | Count | ||
933 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
934 | */ | ||
935 | |||
936 | #define C0_Count $9 | ||
937 | #define R_C0_Count 9 | ||
938 | #define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
939 | |||
940 | #define M_Count0Fields 0x00000000 | ||
941 | #define M_CountRFields 0x00000000 | ||
942 | |||
943 | |||
944 | /* | ||
945 | ************************************************************************ | ||
946 | * E N T R Y H I R E G I S T E R ( 1 0 ) * | ||
947 | ************************************************************************ | ||
948 | * | ||
949 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
950 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
951 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
952 | * | R | Fill // VPN2 | 0 | ASID | EntryHi | ||
953 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
954 | */ | ||
955 | |||
956 | #define C0_EntryHi $10 | ||
957 | #define R_C0_EntryHi 10 | ||
958 | #define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
959 | |||
960 | #define S_EntryHiR64 62 /* Region (R/W) */ | ||
961 | #define M_EntryHiR64 UNS64Const(0xc000000000000000) | ||
962 | #define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ | ||
963 | #define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) | ||
964 | #define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) | ||
965 | #define S_EntryHiASID 0 /* ASID (R/W) */ | ||
966 | #define M_EntryHiASID (0xff << S_EntryHiASID) | ||
967 | #define S_EntryHiVPN_Shf S_EntryHiVPN2 | ||
968 | |||
969 | #define M_EntryHi0Fields 0x00001f00 | ||
970 | #define M_EntryHiRFields 0x00000000 | ||
971 | #define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) | ||
972 | #define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) | ||
973 | |||
974 | |||
975 | /* | ||
976 | ************************************************************************ | ||
977 | * C O M P A R E R E G I S T E R ( 1 1 ) * | ||
978 | ************************************************************************ | ||
979 | * | ||
980 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
981 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
982 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
983 | * | Compare Value | Compare | ||
984 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
985 | */ | ||
986 | |||
987 | #define C0_Compare $11 | ||
988 | #define R_C0_Compare 11 | ||
989 | #define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
990 | |||
991 | #define M_Compare0Fields 0x00000000 | ||
992 | #define M_CompareRFields 0x00000000 | ||
993 | |||
994 | |||
995 | /* | ||
996 | ************************************************************************ | ||
997 | * S T A T U S R E G I S T E R ( 1 2 ) * | ||
998 | ************************************************************************ | ||
999 | * | ||
1000 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1001 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1002 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1003 | * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| | ||
1004 | * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status | ||
1005 | * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | | ||
1006 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1007 | */ | ||
1008 | |||
1009 | #define C0_Status $12 | ||
1010 | #define R_C0_Status 12 | ||
1011 | #define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1012 | |||
1013 | #define S_StatusCU 28 /* Coprocessor enable (R/W) */ | ||
1014 | #define M_StatusCU (0xf << S_StatusCU) | ||
1015 | #define S_StatusCU3 31 | ||
1016 | #define M_StatusCU3 (0x1 << S_StatusCU3) | ||
1017 | #define S_StatusCU2 30 | ||
1018 | #define M_StatusCU2 (0x1 << S_StatusCU2) | ||
1019 | #define S_StatusCU1 29 | ||
1020 | #define M_StatusCU1 (0x1 << S_StatusCU1) | ||
1021 | #define S_StatusCU0 28 | ||
1022 | #define M_StatusCU0 (0x1 << S_StatusCU0) | ||
1023 | #define S_StatusRP 27 /* Enable reduced power mode (R/W) */ | ||
1024 | #define M_StatusRP (0x1 << S_StatusRP) | ||
1025 | #define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ | ||
1026 | #define M_StatusFR (0x1 << S_StatusFR) | ||
1027 | #define S_StatusRE 25 /* Enable reverse endian (R/W) */ | ||
1028 | #define M_StatusRE (0x1 << S_StatusRE) | ||
1029 | #define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ | ||
1030 | #define M_StatusMX (0x1 << S_StatusMX) | ||
1031 | #define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ | ||
1032 | #define M_StatusPX (0x1 << S_StatusPX) | ||
1033 | #define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ | ||
1034 | #define M_StatusBEV (0x1 << S_StatusBEV) | ||
1035 | #define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ | ||
1036 | #define M_StatusTS (0x1 << S_StatusTS) | ||
1037 | #define S_StatusSR 20 /* Denote soft reset (R/W) */ | ||
1038 | #define M_StatusSR (0x1 << S_StatusSR) | ||
1039 | #define S_StatusNMI 19 | ||
1040 | #define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ | ||
1041 | #define S_StatusIM 8 /* Interrupt mask (R/W) */ | ||
1042 | #define M_StatusIM (0xff << S_StatusIM) | ||
1043 | #define S_StatusIM7 15 | ||
1044 | #define M_StatusIM7 (0x1 << S_StatusIM7) | ||
1045 | #define S_StatusIM6 14 | ||
1046 | #define M_StatusIM6 (0x1 << S_StatusIM6) | ||
1047 | #define S_StatusIM5 13 | ||
1048 | #define M_StatusIM5 (0x1 << S_StatusIM5) | ||
1049 | #define S_StatusIM4 12 | ||
1050 | #define M_StatusIM4 (0x1 << S_StatusIM4) | ||
1051 | #define S_StatusIM3 11 | ||
1052 | #define M_StatusIM3 (0x1 << S_StatusIM3) | ||
1053 | #define S_StatusIM2 10 | ||
1054 | #define M_StatusIM2 (0x1 << S_StatusIM2) | ||
1055 | #define S_StatusIM1 9 | ||
1056 | #define M_StatusIM1 (0x1 << S_StatusIM1) | ||
1057 | #define S_StatusIM0 8 | ||
1058 | #define M_StatusIM0 (0x1 << S_StatusIM0) | ||
1059 | #define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ | ||
1060 | #define M_StatusKX (0x1 << S_StatusKX) | ||
1061 | #define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ | ||
1062 | #define M_StatusSX (0x1 << S_StatusSX) | ||
1063 | #define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ | ||
1064 | #define M_StatusUX (0x1 << S_StatusUX) | ||
1065 | #define S_StatusKSU 3 /* Two-bit current mode (R/W) */ | ||
1066 | #define M_StatusKSU (0x3 << S_StatusKSU) | ||
1067 | #define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ | ||
1068 | #define M_StatusUM (0x1 << S_StatusUM) | ||
1069 | #define S_StatusSM 3 /* Supervisor mode (R/W) */ | ||
1070 | #define M_StatusSM (0x1 << S_StatusSM) | ||
1071 | #define S_StatusERL 2 /* Denotes error level (R/W) */ | ||
1072 | #define M_StatusERL (0x1 << S_StatusERL) | ||
1073 | #define S_StatusEXL 1 /* Denotes exception level (R/W) */ | ||
1074 | #define M_StatusEXL (0x1 << S_StatusEXL) | ||
1075 | #define S_StatusIE 0 /* Enables interrupts (R/W) */ | ||
1076 | #define M_StatusIE (0x1 << S_StatusIE) | ||
1077 | |||
1078 | #define M_Status0Fields 0x00040000 | ||
1079 | #define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ | ||
1080 | #define M_Status0Fields64 0x00040000 | ||
1081 | #define M_StatusRFields64 0x00000000 | ||
1082 | |||
1083 | /* | ||
1084 | * Values in the KSU field | ||
1085 | */ | ||
1086 | #define K_StatusKSU_U 2 /* User mode in KSU field */ | ||
1087 | #define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ | ||
1088 | #define K_StatusKSU_K 0 /* Kernel mode in KSU field */ | ||
1089 | |||
1090 | |||
1091 | /* | ||
1092 | ************************************************************************ | ||
1093 | * C A U S E R E G I S T E R ( 1 3 ) * | ||
1094 | ************************************************************************ | ||
1095 | * | ||
1096 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1097 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1098 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1099 | * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | | ||
1100 | * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause | ||
1101 | * | | | | | | | |7|6|5|4|3|2|1|0| | | v | | ||
1102 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1103 | */ | ||
1104 | |||
1105 | #define C0_Cause $13 | ||
1106 | #define R_C0_Cause 13 | ||
1107 | #define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1108 | |||
1109 | #define S_CauseBD 31 | ||
1110 | #define M_CauseBD (0x1 << S_CauseBD) | ||
1111 | #define S_CauseCE 28 | ||
1112 | #define M_CauseCE (0x3<< S_CauseCE) | ||
1113 | #define S_CauseIV 23 | ||
1114 | #define M_CauseIV (0x1 << S_CauseIV) | ||
1115 | #define S_CauseWP 22 | ||
1116 | #define M_CauseWP (0x1 << S_CauseWP) | ||
1117 | #define S_CauseIP 8 | ||
1118 | #define M_CauseIP (0xff << S_CauseIP) | ||
1119 | #define S_CauseIPEXT 10 | ||
1120 | #define M_CauseIPEXT (0x3f << S_CauseIPEXT) | ||
1121 | #define S_CauseIP7 15 | ||
1122 | #define M_CauseIP7 (0x1 << S_CauseIP7) | ||
1123 | #define S_CauseIP6 14 | ||
1124 | #define M_CauseIP6 (0x1 << S_CauseIP6) | ||
1125 | #define S_CauseIP5 13 | ||
1126 | #define M_CauseIP5 (0x1 << S_CauseIP5) | ||
1127 | #define S_CauseIP4 12 | ||
1128 | #define M_CauseIP4 (0x1 << S_CauseIP4) | ||
1129 | #define S_CauseIP3 11 | ||
1130 | #define M_CauseIP3 (0x1 << S_CauseIP3) | ||
1131 | #define S_CauseIP2 10 | ||
1132 | #define M_CauseIP2 (0x1 << S_CauseIP2) | ||
1133 | #define S_CauseIP1 9 | ||
1134 | #define M_CauseIP1 (0x1 << S_CauseIP1) | ||
1135 | #define S_CauseIP0 8 | ||
1136 | #define M_CauseIP0 (0x1 << S_CauseIP0) | ||
1137 | #define S_CauseExcCode 2 | ||
1138 | #define M_CauseExcCode (0x1f << S_CauseExcCode) | ||
1139 | |||
1140 | #define M_Cause0Fields 0x4f3f0083 | ||
1141 | #define M_CauseRFields 0xb000fc7c | ||
1142 | |||
1143 | /* | ||
1144 | * Values in the CE field | ||
1145 | */ | ||
1146 | #define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ | ||
1147 | #define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ | ||
1148 | #define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ | ||
1149 | #define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ | ||
1150 | |||
1151 | /* | ||
1152 | * Values in the ExcCode field | ||
1153 | */ | ||
1154 | #define EX_INT 0 /* Interrupt */ | ||
1155 | #define EXC_INT (EX_INT << S_CauseExcCode) | ||
1156 | #define EX_MOD 1 /* TLB modified */ | ||
1157 | #define EXC_MOD (EX_MOD << S_CauseExcCode) | ||
1158 | #define EX_TLBL 2 /* TLB exception (load or ifetch) */ | ||
1159 | #define EXC_TLBL (EX_TLBL << S_CauseExcCode) | ||
1160 | #define EX_TLBS 3 /* TLB exception (store) */ | ||
1161 | #define EXC_TLBS (EX_TLBS << S_CauseExcCode) | ||
1162 | #define EX_ADEL 4 /* Address error (load or ifetch) */ | ||
1163 | #define EXC_ADEL (EX_ADEL << S_CauseExcCode) | ||
1164 | #define EX_ADES 5 /* Address error (store) */ | ||
1165 | #define EXC_ADES (EX_ADES << S_CauseExcCode) | ||
1166 | #define EX_IBE 6 /* Instruction Bus Error */ | ||
1167 | #define EXC_IBE (EX_IBE << S_CauseExcCode) | ||
1168 | #define EX_DBE 7 /* Data Bus Error */ | ||
1169 | #define EXC_DBE (EX_DBE << S_CauseExcCode) | ||
1170 | #define EX_SYS 8 /* Syscall */ | ||
1171 | #define EXC_SYS (EX_SYS << S_CauseExcCode) | ||
1172 | #define EX_SYSCALL EX_SYS | ||
1173 | #define EXC_SYSCALL EXC_SYS | ||
1174 | #define EX_BP 9 /* Breakpoint */ | ||
1175 | #define EXC_BP (EX_BP << S_CauseExcCode) | ||
1176 | #define EX_BREAK EX_BP | ||
1177 | #define EXC_BREAK EXC_BP | ||
1178 | #define EX_RI 10 /* Reserved instruction */ | ||
1179 | #define EXC_RI (EX_RI << S_CauseExcCode) | ||
1180 | #define EX_CPU 11 /* CoProcessor Unusable */ | ||
1181 | #define EXC_CPU (EX_CPU << S_CauseExcCode) | ||
1182 | #define EX_OV 12 /* OVerflow */ | ||
1183 | #define EXC_OV (EX_OV << S_CauseExcCode) | ||
1184 | #define EX_TR 13 /* Trap instruction */ | ||
1185 | #define EXC_TR (EX_TR << S_CauseExcCode) | ||
1186 | #define EX_TRAP EX_TR | ||
1187 | #define EXC_TRAP EXC_TR | ||
1188 | #define EX_FPE 15 /* floating point exception */ | ||
1189 | #define EXC_FPE (EX_FPE << S_CauseExcCode) | ||
1190 | #define EX_C2E 18 /* COP2 exception */ | ||
1191 | #define EXC_C2E (EX_C2E << S_CauseExcCode) | ||
1192 | #define EX_MDMX 22 /* MDMX exception */ | ||
1193 | #define EXC_MDMX (EX_MDMX << S_CauseExcCode) | ||
1194 | #define EX_WATCH 23 /* Watch exception */ | ||
1195 | #define EXC_WATCH (EX_WATCH << S_CauseExcCode) | ||
1196 | #define EX_MCHECK 24 /* Machine check exception */ | ||
1197 | #define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) | ||
1198 | #define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ | ||
1199 | #define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) | ||
1200 | |||
1201 | |||
1202 | /* | ||
1203 | ************************************************************************ | ||
1204 | * E P C R E G I S T E R ( 1 4 ) * | ||
1205 | ************************************************************************ | ||
1206 | * | ||
1207 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1208 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1209 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1210 | * | // Exception PC | EPC | ||
1211 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1212 | */ | ||
1213 | |||
1214 | #define C0_EPC $14 | ||
1215 | #define R_C0_EPC 14 | ||
1216 | |||
1217 | #define M_EPC0Fields 0x00000000 | ||
1218 | #define M_EPCRFields 0x00000000 | ||
1219 | #define M_EPC0Fields64 UNS64Const(0x0000000000000000) | ||
1220 | #define M_EPCRFields64 UNS64Const(0x0000000000000000) | ||
1221 | |||
1222 | /* | ||
1223 | ************************************************************************ | ||
1224 | * P R I D R E G I S T E R ( 1 5 ) * | ||
1225 | ************************************************************************ | ||
1226 | * | ||
1227 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1228 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1229 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1230 | * | Company Opts | Company ID | Procesor ID | Revision | PRId | ||
1231 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1232 | */ | ||
1233 | |||
1234 | #define C0_PRId $15 | ||
1235 | #define R_C0_PRId 15 | ||
1236 | #define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1237 | |||
1238 | #define S_PRIdCoOpt 24 /* Company options (R) */ | ||
1239 | #define M_PRIdCoOpt (0xff << S_PRIdCoOpt) | ||
1240 | #define S_PRIdCoID 16 /* Company ID (R) */ | ||
1241 | #define M_PRIdCoID (0xff << S_PRIdCoID) | ||
1242 | #define S_PRIdImp 8 /* Implementation ID (R) */ | ||
1243 | #define M_PRIdImp (0xff << S_PRIdImp) | ||
1244 | #define S_PRIdRev 0 /* Revision (R) */ | ||
1245 | #define M_PRIdRev (0xff << S_PRIdRev) | ||
1246 | |||
1247 | #define M_PRId0Fields 0x00000000 | ||
1248 | #define M_PRIdRFields 0xffffffff | ||
1249 | /* | ||
1250 | * Values in the Company ID field | ||
1251 | */ | ||
1252 | #define K_PRIdCoID_MIPS 1 | ||
1253 | #define K_PRIdCoID_Broadcom 2 | ||
1254 | #define K_PRIdCoID_Alchemy 3 | ||
1255 | #define K_PRIdCoID_SiByte 4 | ||
1256 | #define K_PRIdCoID_SandCraft 5 | ||
1257 | #define K_PRIdCoID_Philips 6 | ||
1258 | #define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ | ||
1259 | |||
1260 | |||
1261 | /* | ||
1262 | * Values in the implementation number field | ||
1263 | */ | ||
1264 | #define K_PRIdImp_Jade 0x80 | ||
1265 | #define K_PRIdImp_Opal 0x81 | ||
1266 | #define K_PRIdImp_Ruby 0x82 | ||
1267 | #define K_PRIdImp_JadeLite 0x83 | ||
1268 | #define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ | ||
1269 | #define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ | ||
1270 | #define K_PRIdImp_4KSc 0x86 /* Coral */ | ||
1271 | |||
1272 | #define K_PRIdImp_R3000 0x01 | ||
1273 | #define K_PRIdImp_R4000 0x04 | ||
1274 | #define K_PRIdImp_R10000 0x09 | ||
1275 | #define K_PRIdImp_R4300 0x0b | ||
1276 | #define K_PRIdImp_R5000 0x23 | ||
1277 | #define K_PRIdImp_R5200 0x28 | ||
1278 | #define K_PRIdImp_R5400 0x54 | ||
1279 | |||
1280 | /* | ||
1281 | ************************************************************************ | ||
1282 | * C O N F I G R E G I S T E R ( 1 6 ) * | ||
1283 | ************************************************************************ | ||
1284 | * | ||
1285 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1286 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1287 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1288 | * |M| |B| A | A | | K | Config | ||
1289 | * | | Reserved for Implementations|E| T | R | Reserved | 0 | | ||
1290 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1291 | */ | ||
1292 | |||
1293 | #define C0_Config $16 | ||
1294 | #define R_C0_Config 16 | ||
1295 | #define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1296 | |||
1297 | #define S_ConfigMore 31 /* Additional config registers present (R) */ | ||
1298 | #define M_ConfigMore (0x1 << S_ConfigMore) | ||
1299 | #define S_ConfigImpl 16 /* Implementation-specific fields */ | ||
1300 | #define M_ConfigImpl (0x7fff << S_ConfigImpl) | ||
1301 | #define S_ConfigBE 15 /* Denotes big-endian operation (R) */ | ||
1302 | #define M_ConfigBE (0x1 << S_ConfigBE) | ||
1303 | #define S_ConfigAT 13 /* Architecture type (R) */ | ||
1304 | #define M_ConfigAT (0x3 << S_ConfigAT) | ||
1305 | #define S_ConfigAR 10 /* Architecture revision (R) */ | ||
1306 | #define M_ConfigAR (0x7 << S_ConfigAR) | ||
1307 | #define S_ConfigMT 7 /* MMU Type (R) */ | ||
1308 | #define M_ConfigMT (0x7 << S_ConfigMT) | ||
1309 | #define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ | ||
1310 | #define M_ConfigK0 (0x7 << S_ConfigK0) | ||
1311 | |||
1312 | /* | ||
1313 | * The following definitions are technically part of the "reserved for | ||
1314 | * implementations" field, but are the semi-standard definition used in | ||
1315 | * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 | ||
1316 | * references. For that reason, they are included here, but may be | ||
1317 | * overridden by true implementation-specific definitions | ||
1318 | */ | ||
1319 | #define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ | ||
1320 | #define M_ConfigK23 (0x7 << S_ConfigK23) | ||
1321 | #define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ | ||
1322 | #define M_ConfigKU (0x7 << S_ConfigKU) | ||
1323 | |||
1324 | #define M_Config0Fields 0x00000078 | ||
1325 | #define M_ConfigRFields 0x8000ff80 | ||
1326 | |||
1327 | /* | ||
1328 | * Values in the AT field | ||
1329 | */ | ||
1330 | #define K_ConfigAT_MIPS32 0 /* MIPS32 */ | ||
1331 | #define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ | ||
1332 | #define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ | ||
1333 | |||
1334 | /* | ||
1335 | * Values in the MT field | ||
1336 | */ | ||
1337 | #define K_ConfigMT_NoMMU 0 /* No MMU */ | ||
1338 | #define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ | ||
1339 | #define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ | ||
1340 | #define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ | ||
1341 | |||
1342 | |||
1343 | /* | ||
1344 | ************************************************************************ | ||
1345 | * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * | ||
1346 | ************************************************************************ | ||
1347 | * | ||
1348 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1349 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1350 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1351 | * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 | ||
1352 | * | | | | | | | | |2|D|C|R|A|P|P| | ||
1353 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1354 | */ | ||
1355 | |||
1356 | #define C0_Config1 $16,1 | ||
1357 | #define R_C0_Config1 16 | ||
1358 | |||
1359 | #define S_Config1More 31 /* Additional Config registers present (R) */ | ||
1360 | #define M_Config1More (0x1 << S_Config1More) | ||
1361 | #define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ | ||
1362 | #define M_Config1MMUSize (0x3f << S_Config1MMUSize) | ||
1363 | #define S_Config1IS 22 /* Icache sets per way (R) */ | ||
1364 | #define M_Config1IS (0x7 << S_Config1IS) | ||
1365 | #define S_Config1IL 19 /* Icache line size (R) */ | ||
1366 | #define M_Config1IL (0x7 << S_Config1IL) | ||
1367 | #define S_Config1IA 16 /* Icache associativity - 1 (R) */ | ||
1368 | #define M_Config1IA (0x7 << S_Config1IA) | ||
1369 | #define S_Config1DS 13 /* Dcache sets per way (R) */ | ||
1370 | #define M_Config1DS (0x7 << S_Config1DS) | ||
1371 | #define S_Config1DL 10 /* Dcache line size (R) */ | ||
1372 | #define M_Config1DL (0x7 << S_Config1DL) | ||
1373 | #define S_Config1DA 7 /* Dcache associativity (R) */ | ||
1374 | #define M_Config1DA (0x7 << S_Config1DA) | ||
1375 | #define S_Config1C2 6 /* Coprocessor 2 present (R) */ | ||
1376 | #define M_Config1C2 (0x1 << S_Config1C2) | ||
1377 | #define S_Config1MD 5 /* Denotes MDMX present (R) */ | ||
1378 | #define M_Config1MD (0x1 << S_Config1MD) | ||
1379 | #define S_Config1PC 4 /* Denotes performance counters present (R) */ | ||
1380 | #define M_Config1PC (0x1 << S_Config1PC) | ||
1381 | #define S_Config1WR 3 /* Denotes watch registers present (R) */ | ||
1382 | #define M_Config1WR (0x1 << S_Config1WR) | ||
1383 | #define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ | ||
1384 | #define M_Config1CA (0x1 << S_Config1CA) | ||
1385 | #define S_Config1EP 1 /* Denotes EJTAG present (R) */ | ||
1386 | #define M_Config1EP (0x1 << S_Config1EP) | ||
1387 | #define S_Config1FP 0 /* Denotes floating point present (R) */ | ||
1388 | #define M_Config1FP (0x1 << S_Config1FP) | ||
1389 | |||
1390 | #define M_Config10Fields 0x00000060 | ||
1391 | #define M_Config1RFields 0x7fffff9f | ||
1392 | |||
1393 | /* | ||
1394 | * The following macro generates a table that is indexed | ||
1395 | * by the Icache or Dcache sets field in Config1 and | ||
1396 | * contains the decoded value of sets per way | ||
1397 | */ | ||
1398 | #define Config1CacheSets() \ | ||
1399 | HALF(64); \ | ||
1400 | HALF(128); \ | ||
1401 | HALF(256); \ | ||
1402 | HALF(512); \ | ||
1403 | HALF(1024); \ | ||
1404 | HALF(2048); \ | ||
1405 | HALF(4096); \ | ||
1406 | HALF(8192); | ||
1407 | |||
1408 | /* | ||
1409 | * The following macro generates a table that is indexed | ||
1410 | * by the Icache or Dcache line size field in Config1 and | ||
1411 | * contains the decoded value of the cache line size, in bytes | ||
1412 | */ | ||
1413 | #define Config1CacheLineSize() \ | ||
1414 | HALF(0); \ | ||
1415 | HALF(4); \ | ||
1416 | HALF(8); \ | ||
1417 | HALF(16); \ | ||
1418 | HALF(32); \ | ||
1419 | HALF(64); \ | ||
1420 | HALF(128); \ | ||
1421 | HALF(256); | ||
1422 | |||
1423 | |||
1424 | /* | ||
1425 | ************************************************************************ | ||
1426 | * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * | ||
1427 | ************************************************************************ | ||
1428 | * | ||
1429 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1430 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1431 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1432 | * |M| | | | | | | | | | | | |S|T| Config1 | ||
1433 | * | | | | | | | | | | | | | |M|L| | ||
1434 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1435 | */ | ||
1436 | |||
1437 | #define C0_Config2 $16,2 | ||
1438 | #define R_C0_Config2 16 | ||
1439 | |||
1440 | #define S_Config2More 31 /* Additional Config registers present (R) */ | ||
1441 | #define M_Config2More (0x1 << S_Config2More) | ||
1442 | #define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ | ||
1443 | #define M_Config2SM (0x1 << S_Config2SM) | ||
1444 | #define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ | ||
1445 | #define M_Config2TL (0x1 << S_Config2TL) | ||
1446 | |||
1447 | #define M_Config20Fields 0xfffffffc | ||
1448 | #define M_Config2RFields 0x00000003 | ||
1449 | |||
1450 | /* | ||
1451 | ************************************************************************ | ||
1452 | * L L A D D R R E G I S T E R ( 1 7 ) * | ||
1453 | ************************************************************************ | ||
1454 | * | ||
1455 | * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1456 | * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1457 | * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1458 | * | // LL Physical Address | LLAddr | ||
1459 | * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1460 | */ | ||
1461 | |||
1462 | #define C0_LLAddr $17 | ||
1463 | #define R_C0_LLAddr 17 | ||
1464 | #define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1465 | |||
1466 | #define M_LLAddr0Fields 0x00000000 | ||
1467 | #define M_LLAddrRFields 0x00000000 | ||
1468 | #define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) | ||
1469 | #define M_LLAddrRFields64 UNS64Const(0x0000000000000000) | ||
1470 | |||
1471 | |||
1472 | /* | ||
1473 | ************************************************************************ | ||
1474 | * W A T C H L O R E G I S T E R ( 1 8 ) * | ||
1475 | ************************************************************************ | ||
1476 | * | ||
1477 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1478 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1479 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1480 | * | // Watch Virtual Address |I|R|W| WatchLo | ||
1481 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1482 | */ | ||
1483 | |||
1484 | #define C0_WatchLo $18 | ||
1485 | #define R_C0_WatchLo 18 | ||
1486 | #define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1487 | |||
1488 | #define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ | ||
1489 | #define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) | ||
1490 | #define S_WatchLoI 2 /* Enable Istream watch (R/W) */ | ||
1491 | #define M_WatchLoI (0x1 << S_WatchLoI) | ||
1492 | #define S_WatchLoR 1 /* Enable data read watch (R/W) */ | ||
1493 | #define M_WatchLoR (0x1 << S_WatchLoR) | ||
1494 | #define S_WatchLoW 0 /* Enable data write watch (R/W) */ | ||
1495 | #define M_WatchLoW (0x1 << S_WatchLoW) | ||
1496 | |||
1497 | #define M_WatchLo0Fields 0x00000000 | ||
1498 | #define M_WatchLoRFields 0x00000000 | ||
1499 | #define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) | ||
1500 | #define M_WatchLoRFields64 UNS64Const(0x0000000000000000) | ||
1501 | |||
1502 | #define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) | ||
1503 | |||
1504 | |||
1505 | /* | ||
1506 | ************************************************************************ | ||
1507 | * W A T C H H I R E G I S T E R ( 1 9 ) * | ||
1508 | ************************************************************************ | ||
1509 | * | ||
1510 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1511 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1512 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1513 | * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi | ||
1514 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1515 | */ | ||
1516 | |||
1517 | #define C0_WatchHi $19 | ||
1518 | #define R_C0_WatchHi 19 | ||
1519 | #define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1520 | |||
1521 | #define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ | ||
1522 | #define M_WatchHiM (0x1 << S_WatchHiM) | ||
1523 | #define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ | ||
1524 | #define M_WatchHiG (0x1 << S_WatchHiG) | ||
1525 | #define S_WatchHiASID 16 /* ASID value to match (R/W) */ | ||
1526 | #define M_WatchHiASID (0xff << S_WatchHiASID) | ||
1527 | #define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ | ||
1528 | #define M_WatchHiMask (0x1ff << S_WatchHiMask) | ||
1529 | |||
1530 | #define M_WatchHi0Fields 0x3f00f007 | ||
1531 | #define M_WatchHiRFields 0x80000000 | ||
1532 | |||
1533 | |||
1534 | /* | ||
1535 | ************************************************************************ | ||
1536 | * X C O N T E X T R E G I S T E R ( 2 0 ) * | ||
1537 | ************************************************************************ | ||
1538 | * | ||
1539 | * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1540 | * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1541 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1542 | * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext | ||
1543 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1544 | */ | ||
1545 | |||
1546 | #define C0_XContext $20 | ||
1547 | #define R_C0_XContext 20 | ||
1548 | #define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1549 | |||
1550 | #define S_XContextBadVPN2 4 /* BadVPN2 (R) */ | ||
1551 | #define S_XContextBadVPN S_XContextBadVPN2 | ||
1552 | |||
1553 | #define M_XContext0Fields 0x0000000f | ||
1554 | |||
1555 | |||
1556 | /* | ||
1557 | ************************************************************************ | ||
1558 | * D E B U G R E G I S T E R ( 2 3 ) * | ||
1559 | ************************************************************************ | ||
1560 | * | ||
1561 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1562 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1563 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1564 | * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| | ||
1565 | * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| | ||
1566 | * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| | ||
1567 | * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug | ||
1568 | * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | | ||
1569 | * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | | ||
1570 | * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | | ||
1571 | * | | | | | | | | | | | | |r|r| | | | | | | | | | | | | ||
1572 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1573 | */ | ||
1574 | |||
1575 | #define C0_Debug $23 /* EJTAG */ | ||
1576 | #define R_C0_Debug 23 | ||
1577 | |||
1578 | #define S_DebugDBD 31 /* Debug branch delay (R) */ | ||
1579 | #define M_DebugDBD (0x1 << S_DebugDBD) | ||
1580 | #define S_DebugDM 30 /* Debug mode (R) */ | ||
1581 | #define M_DebugDM (0x1 << S_DebugDM) | ||
1582 | #define S_DebugNoDCR 29 /* No debug control register present (R) */ | ||
1583 | #define M_DebugNoDCR (0x1 << S_DebugNoDCR) | ||
1584 | #define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ | ||
1585 | #define M_DebugLSNM (0x1 << S_DebugLSNM) | ||
1586 | #define S_DebugDoze 27 /* Doze (R) */ | ||
1587 | #define M_DebugDoze (0x1 << S_DebugDoze) | ||
1588 | #define S_DebugHalt 26 /* Halt (R) */ | ||
1589 | #define M_DebugHalt (0x1 << S_DebugHalt) | ||
1590 | #define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ | ||
1591 | #define M_DebugCountDM (0x1 << S_DebugCountDM) | ||
1592 | #define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ | ||
1593 | #define M_DebugIBusEP (0x1 << S_DebugIBusEP) | ||
1594 | #define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ | ||
1595 | #define M_DebugMCheckP (0x1 << S_DebugMCheckP) | ||
1596 | #define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ | ||
1597 | #define M_DebugCacheEP (0x1 << S_DebugCacheEP) | ||
1598 | #define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ | ||
1599 | #define M_DebugDBusEP (0x1 << S_DebugDBusEP) | ||
1600 | #define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ | ||
1601 | #define M_DebugIEXI (0x1 << S_DebugIEXI) | ||
1602 | #define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ | ||
1603 | #define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) | ||
1604 | #define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ | ||
1605 | #define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) | ||
1606 | #define S_DebugEJTAGver 15 /* EJTAG version number (R) */ | ||
1607 | #define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) | ||
1608 | #define S_DebugDExcCode 10 /* Debug exception code (R) */ | ||
1609 | #define M_DebugDExcCode (0x1f << S_DebugDExcCode) | ||
1610 | #define S_DebugNoSSt 9 /* No single step implemented (R) */ | ||
1611 | #define M_DebugNoSSt (0x1 << S_DebugNoSSt) | ||
1612 | #define S_DebugSSt 8 /* Single step enable (R/W) */ | ||
1613 | #define M_DebugSSt (0x1 << S_DebugSSt) | ||
1614 | #define S_DebugDINT 5 /* Debug interrupt (R) */ | ||
1615 | #define M_DebugDINT (0x1 << S_DebugDINT) | ||
1616 | #define S_DebugDIB 4 /* Debug instruction break (R) */ | ||
1617 | #define M_DebugDIB (0x1 << S_DebugDIB) | ||
1618 | #define S_DebugDDBS 3 /* Debug data break store (R) */ | ||
1619 | #define M_DebugDDBS (0x1 << S_DebugDDBS) | ||
1620 | #define S_DebugDDBL 2 /* Debug data break load (R) */ | ||
1621 | #define M_DebugDDBL (0x1 << S_DebugDDBL) | ||
1622 | #define S_DebugDBp 1 /* Debug breakpoint (R) */ | ||
1623 | #define M_DebugDBp (0x1 << S_DebugDBp) | ||
1624 | #define S_DebugDSS 0 /* Debug single step (R) */ | ||
1625 | #define M_DebugDSS (0x1 << S_DebugDSS) | ||
1626 | |||
1627 | #define M_Debug0Fields 0x01f000c0 | ||
1628 | #define M_DebugRFields 0xec0ffe3f | ||
1629 | |||
1630 | |||
1631 | /* | ||
1632 | ************************************************************************ | ||
1633 | * D E P C R E G I S T E R ( 2 4 ) * | ||
1634 | ************************************************************************ | ||
1635 | * | ||
1636 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1637 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1638 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1639 | * | // EJTAG Debug Exception PC | DEPC | ||
1640 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1641 | */ | ||
1642 | |||
1643 | |||
1644 | #define C0_DEPC $24 | ||
1645 | #define R_C0_DEPC 24 | ||
1646 | |||
1647 | #define M_DEEPC0Fields 0x00000000 | ||
1648 | #define M_DEEPCRFields 0x00000000 | ||
1649 | #define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) | ||
1650 | #define M_DEEPCRFields64 UNS64Const(0x0000000000000000) | ||
1651 | |||
1652 | |||
1653 | /* | ||
1654 | ************************************************************************ | ||
1655 | * P E R F C N T R E G I S T E R ( 2 5 ) * | ||
1656 | ************************************************************************ | ||
1657 | * | ||
1658 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1659 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1660 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1661 | * | | | |I| | | |E| | ||
1662 | * |M| 0 | Event |E|U|S|K|X| PerfCnt | ||
1663 | * | | | | | | | |L| | ||
1664 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1665 | * | ||
1666 | * | ||
1667 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1668 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1669 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1670 | * | Event Count | PerfCnt | ||
1671 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1672 | */ | ||
1673 | |||
1674 | #define C0_PerfCnt $25 | ||
1675 | #define R_C0_PerfCnt 25 | ||
1676 | #define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1677 | #define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1678 | |||
1679 | #define S_PerfCntM 31 /* More performance counters exist (R) */ | ||
1680 | #define M_PerfCntM (1 << S_PerfCntM) | ||
1681 | #define S_PerfCntEvent 5 /* Enabled event (R/W) */ | ||
1682 | #define M_PerfCntEvent (0x3f << S_PerfCntEvent) | ||
1683 | #define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ | ||
1684 | #define M_PerfCntIE (1 << S_PerfCntIE) | ||
1685 | #define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ | ||
1686 | #define M_PerfCntU (1 << S_PerfCntU) | ||
1687 | #define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ | ||
1688 | #define M_PerfCntS (1 << S_PerfCntS) | ||
1689 | #define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ | ||
1690 | #define M_PerfCntK (1 << S_PerfCntK) | ||
1691 | #define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ | ||
1692 | #define M_PerfCntEXL (1 << S_PerfCntEXL) | ||
1693 | |||
1694 | #define M_PerfCnt0Fields 0x7ffff800 | ||
1695 | #define M_PerfCntRFields 0x80000000 | ||
1696 | |||
1697 | |||
1698 | /* | ||
1699 | ************************************************************************ | ||
1700 | * E R R C T L R E G I S T E R ( 2 6 ) * | ||
1701 | ************************************************************************ | ||
1702 | * | ||
1703 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1704 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1705 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1706 | * | Error Control | ErrCtl | ||
1707 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1708 | */ | ||
1709 | |||
1710 | #define C0_ErrCtl $26 | ||
1711 | #define R_C0_ErrCtl 26 | ||
1712 | #define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1713 | #define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1714 | |||
1715 | #define M_ErrCtl0Fields 0x00000000 | ||
1716 | #define M_ErrCtlRFields 0x00000000 | ||
1717 | |||
1718 | |||
1719 | /* | ||
1720 | ************************************************************************ | ||
1721 | * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr | ||
1722 | ************************************************************************ | ||
1723 | * | ||
1724 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1725 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1726 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1727 | * | Cache Error Control | CacheErr | ||
1728 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1729 | */ | ||
1730 | |||
1731 | #define C0_CacheErr $27 | ||
1732 | #define R_C0_CacheErr 27 | ||
1733 | #define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1734 | |||
1735 | #define M_CacheErr0Fields 0x00000000 | ||
1736 | #define M_CachErrRFields 0x00000000 | ||
1737 | |||
1738 | |||
1739 | /* | ||
1740 | ************************************************************************ | ||
1741 | * T A G L O R E G I S T E R ( 2 8 ) * TagLo | ||
1742 | ************************************************************************ | ||
1743 | * | ||
1744 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1745 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1746 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1747 | * | TagLo | TagLo | ||
1748 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1749 | */ | ||
1750 | |||
1751 | #define C0_TagLo $28 | ||
1752 | #define R_C0_TagLo 28 | ||
1753 | #define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1754 | |||
1755 | /* | ||
1756 | * Some implementations use separate TagLo registers for the | ||
1757 | * instruction and data caches. In those cases, the following | ||
1758 | * definitions can be used in relevant code | ||
1759 | */ | ||
1760 | |||
1761 | #define C0_ITagLo $28,0 | ||
1762 | #define C0_DTagLo $28,2 | ||
1763 | |||
1764 | #define M_TagLo0Fields 0x00000000 | ||
1765 | #define M_TagLoRFields 0x00000000 | ||
1766 | |||
1767 | |||
1768 | /* | ||
1769 | ************************************************************************ | ||
1770 | * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo | ||
1771 | ************************************************************************ | ||
1772 | * | ||
1773 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1774 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1775 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1776 | * | DataLo | DataLo | ||
1777 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1778 | */ | ||
1779 | |||
1780 | #define C0_DataLo $28,1 | ||
1781 | #define R_C0_DataLo 28 | ||
1782 | |||
1783 | /* | ||
1784 | * Some implementations use separate DataLo registers for the | ||
1785 | * instruction and data caches. In those cases, the following | ||
1786 | * definitions can be used in relevant code | ||
1787 | */ | ||
1788 | |||
1789 | #define C0_IDataLo $28,1 | ||
1790 | #define C0_DDataLo $28,3 | ||
1791 | |||
1792 | #define M_DataLo0Fields 0x00000000 | ||
1793 | #define M_DataLoRFields 0xffffffff | ||
1794 | |||
1795 | |||
1796 | /* | ||
1797 | ************************************************************************ | ||
1798 | * T A G H I R E G I S T E R ( 2 9 ) * TagHi | ||
1799 | ************************************************************************ | ||
1800 | * | ||
1801 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1802 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1803 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1804 | * | TagHi | TagHi | ||
1805 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1806 | */ | ||
1807 | |||
1808 | #define C0_TagHi $29 | ||
1809 | #define R_C0_TagHi 29 | ||
1810 | #define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1811 | |||
1812 | /* | ||
1813 | * Some implementations use separate TagHi registers for the | ||
1814 | * instruction and data caches. In those cases, the following | ||
1815 | * definitions can be used in relevant code | ||
1816 | */ | ||
1817 | |||
1818 | #define C0_ITagHi $29,0 | ||
1819 | #define C0_DTagHi $29,2 | ||
1820 | |||
1821 | #define M_TagHi0Fields 0x00000000 | ||
1822 | #define M_TagHiRFields 0x00000000 | ||
1823 | |||
1824 | |||
1825 | /* | ||
1826 | ************************************************************************ | ||
1827 | * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi | ||
1828 | ************************************************************************ | ||
1829 | * | ||
1830 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1831 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1832 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1833 | * | DataHi | DataHi | ||
1834 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1835 | */ | ||
1836 | |||
1837 | #define C0_DataHi $29,1 | ||
1838 | #define R_C0_DataHi 29 | ||
1839 | |||
1840 | /* | ||
1841 | * Some implementations use separate DataHi registers for the | ||
1842 | * instruction and data caches. In those cases, the following | ||
1843 | * definitions can be used in relevant code | ||
1844 | */ | ||
1845 | |||
1846 | #define C0_IDataHi $29,1 | ||
1847 | #define C0_DDataHi $29,3 | ||
1848 | |||
1849 | #define M_DataHi0Fields 0x00000000 | ||
1850 | #define M_DataHiRFields 0xffffffff | ||
1851 | |||
1852 | |||
1853 | /* | ||
1854 | ************************************************************************ | ||
1855 | * E R R O R E P C R E G I S T E R ( 3 0 ) * | ||
1856 | ************************************************************************ | ||
1857 | * | ||
1858 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1859 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1860 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1861 | * | // Error PC | ErrorEPC | ||
1862 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1863 | */ | ||
1864 | |||
1865 | #define C0_ErrorEPC $30 | ||
1866 | #define R_C0_ErrorEPC 30 | ||
1867 | #define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1868 | |||
1869 | #define M_ErrorEPC0Fields 0x00000000 | ||
1870 | #define M_ErrorEPCRFields 0x00000000 | ||
1871 | #define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) | ||
1872 | #define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) | ||
1873 | |||
1874 | |||
1875 | /* | ||
1876 | ************************************************************************ | ||
1877 | * D E S A V E R E G I S T E R ( 3 1 ) * | ||
1878 | ************************************************************************ | ||
1879 | * | ||
1880 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1881 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1882 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1883 | * | // EJTAG Register Save Value | DESAVE | ||
1884 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1885 | */ | ||
1886 | |||
1887 | #define C0_DESAVE $31 | ||
1888 | #define R_C0_DESAVE 31 | ||
1889 | |||
1890 | #define M_DESAVE0Fields 0x00000000 | ||
1891 | #define M_DESAVERFields 0x00000000 | ||
1892 | #define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) | ||
1893 | #define M_DESAVERFields64 UNS64Const(0x0000000000000000) | ||
1894 | |||
1895 | |||
1896 | /* | ||
1897 | ************************************************************************* | ||
1898 | * C P 1 R E G I S T E R D E F I N I T I O N S * | ||
1899 | ************************************************************************* | ||
1900 | */ | ||
1901 | |||
1902 | |||
1903 | /* | ||
1904 | ************************************************************************* | ||
1905 | * H A R D W A R E F P R N A M E S * | ||
1906 | ************************************************************************* | ||
1907 | */ | ||
1908 | |||
1909 | #define fp0 $f0 | ||
1910 | #define fp1 $f1 | ||
1911 | #define fp2 $f2 | ||
1912 | #define fp3 $f3 | ||
1913 | #define fp4 $f4 | ||
1914 | #define fp5 $f5 | ||
1915 | #define fp6 $f6 | ||
1916 | #define fp7 $f7 | ||
1917 | #define fp8 $f8 | ||
1918 | #define fp9 $f9 | ||
1919 | #define fp10 $f10 | ||
1920 | #define fp11 $f11 | ||
1921 | #define fp12 $f12 | ||
1922 | #define fp13 $f13 | ||
1923 | #define fp14 $f14 | ||
1924 | #define fp15 $f15 | ||
1925 | #define fp16 $f16 | ||
1926 | #define fp17 $f17 | ||
1927 | #define fp18 $f18 | ||
1928 | #define fp19 $f19 | ||
1929 | #define fp20 $f20 | ||
1930 | #define fp21 $f21 | ||
1931 | #define fp22 $f22 | ||
1932 | #define fp23 $f23 | ||
1933 | #define fp24 $f24 | ||
1934 | #define fp25 $f25 | ||
1935 | #define fp26 $f26 | ||
1936 | #define fp27 $f27 | ||
1937 | #define fp28 $f28 | ||
1938 | #define fp29 $f29 | ||
1939 | #define fp30 $f30 | ||
1940 | #define fp31 $f31 | ||
1941 | |||
1942 | /* | ||
1943 | * The following definitions are used to convert an FPR name | ||
1944 | * into the corresponding even or odd name, respectively. | ||
1945 | * This is used in macro substitution in the AVPs. | ||
1946 | */ | ||
1947 | |||
1948 | #define fp1_even $f0 | ||
1949 | #define fp3_even $f2 | ||
1950 | #define fp5_even $f4 | ||
1951 | #define fp7_even $f6 | ||
1952 | #define fp9_even $f8 | ||
1953 | #define fp11_even $f10 | ||
1954 | #define fp13_even $f12 | ||
1955 | #define fp15_even $f14 | ||
1956 | #define fp17_even $f16 | ||
1957 | #define fp19_even $f18 | ||
1958 | #define fp21_even $f20 | ||
1959 | #define fp23_even $f22 | ||
1960 | #define fp25_even $f24 | ||
1961 | #define fp27_even $f26 | ||
1962 | #define fp29_even $f28 | ||
1963 | #define fp31_even $f30 | ||
1964 | |||
1965 | #define fp0_odd $f1 | ||
1966 | #define fp2_odd $f3 | ||
1967 | #define fp4_odd $f5 | ||
1968 | #define fp6_odd $f7 | ||
1969 | #define fp8_odd $f9 | ||
1970 | #define fp10_odd $f11 | ||
1971 | #define fp12_odd $f13 | ||
1972 | #define fp14_odd $f15 | ||
1973 | #define fp16_odd $f17 | ||
1974 | #define fp18_odd $f19 | ||
1975 | #define fp20_odd $f21 | ||
1976 | #define fp22_odd $f23 | ||
1977 | #define fp24_odd $f25 | ||
1978 | #define fp26_odd $f27 | ||
1979 | #define fp28_odd $f29 | ||
1980 | #define fp30_odd $f31 | ||
1981 | |||
1982 | |||
1983 | /* | ||
1984 | ************************************************************************* | ||
1985 | * H A R D W A R E F P R I N D I C E S * | ||
1986 | ************************************************************************* | ||
1987 | * | ||
1988 | * These definitions provide the index (number) of the FPR, as opposed | ||
1989 | * to the assembler register name ($n). | ||
1990 | */ | ||
1991 | |||
1992 | #define R_fp0 0 | ||
1993 | #define R_fp1 1 | ||
1994 | #define R_fp2 2 | ||
1995 | #define R_fp3 3 | ||
1996 | #define R_fp4 4 | ||
1997 | #define R_fp5 5 | ||
1998 | #define R_fp6 6 | ||
1999 | #define R_fp7 7 | ||
2000 | #define R_fp8 8 | ||
2001 | #define R_fp9 9 | ||
2002 | #define R_fp10 10 | ||
2003 | #define R_fp11 11 | ||
2004 | #define R_fp12 12 | ||
2005 | #define R_fp13 13 | ||
2006 | #define R_fp14 14 | ||
2007 | #define R_fp15 15 | ||
2008 | #define R_fp16 16 | ||
2009 | #define R_fp17 17 | ||
2010 | #define R_fp18 18 | ||
2011 | #define R_fp19 19 | ||
2012 | #define R_fp20 20 | ||
2013 | #define R_fp21 21 | ||
2014 | #define R_fp22 22 | ||
2015 | #define R_fp23 23 | ||
2016 | #define R_fp24 24 | ||
2017 | #define R_fp25 25 | ||
2018 | #define R_fp26 26 | ||
2019 | #define R_fp27 27 | ||
2020 | #define R_fp28 28 | ||
2021 | #define R_fp29 29 | ||
2022 | #define R_fp30 30 | ||
2023 | #define R_fp31 31 | ||
2024 | |||
2025 | |||
2026 | /* | ||
2027 | ************************************************************************* | ||
2028 | * H A R D W A R E F C R N A M E S * | ||
2029 | ************************************************************************* | ||
2030 | */ | ||
2031 | |||
2032 | #define fc0 $0 | ||
2033 | #define fc25 $25 | ||
2034 | #define fc26 $26 | ||
2035 | #define fc28 $28 | ||
2036 | #define fc31 $31 | ||
2037 | |||
2038 | |||
2039 | /* | ||
2040 | ************************************************************************* | ||
2041 | * H A R D W A R E F C R I N D I C E S * | ||
2042 | ************************************************************************* | ||
2043 | * | ||
2044 | * These definitions provide the index (number) of the FCR, as opposed | ||
2045 | * to the assembler register name ($n). | ||
2046 | */ | ||
2047 | |||
2048 | #define R_fc0 0 | ||
2049 | #define R_fc25 25 | ||
2050 | #define R_fc26 26 | ||
2051 | #define R_fc28 28 | ||
2052 | #define R_fc31 31 | ||
2053 | |||
2054 | |||
2055 | /* | ||
2056 | ************************************************************************* | ||
2057 | * H A R D W A R E F C C N A M E S * | ||
2058 | ************************************************************************* | ||
2059 | */ | ||
2060 | |||
2061 | #define cc0 $fcc0 | ||
2062 | #define cc1 $fcc1 | ||
2063 | #define cc2 $fcc2 | ||
2064 | #define cc3 $fcc3 | ||
2065 | #define cc4 $fcc4 | ||
2066 | #define cc5 $fcc5 | ||
2067 | #define cc6 $fcc6 | ||
2068 | #define cc7 $fcc7 | ||
2069 | |||
2070 | |||
2071 | /* | ||
2072 | ************************************************************************* | ||
2073 | * H A R D W A R E F C C I N D I C E S * | ||
2074 | ************************************************************************* | ||
2075 | * | ||
2076 | * These definitions provide the index (number) of the CC, as opposed | ||
2077 | * to the assembler register name ($n). | ||
2078 | */ | ||
2079 | |||
2080 | #define R_cc0 0 | ||
2081 | #define R_cc1 1 | ||
2082 | #define R_cc2 2 | ||
2083 | #define R_cc3 3 | ||
2084 | #define R_cc4 4 | ||
2085 | #define R_cc5 5 | ||
2086 | #define R_cc6 6 | ||
2087 | #define R_cc7 7 | ||
2088 | |||
2089 | |||
2090 | /* | ||
2091 | ************************************************************************ | ||
2092 | * I M P L E M E N T A T I O N R E G I S T E R * | ||
2093 | ************************************************************************ | ||
2094 | * | ||
2095 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2096 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2097 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2098 | * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR | ||
2099 | * | Configuration Bits |D|S| | | | | | ||
2100 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2101 | */ | ||
2102 | |||
2103 | #define C1_FIR $0 | ||
2104 | #define R_C1_FIR 0 | ||
2105 | |||
2106 | #define S_FIRConfigS 16 | ||
2107 | #define M_FIRConfigS (0x1 << S_FIRConfigS) | ||
2108 | #define S_FIRConfigD 17 | ||
2109 | #define M_FIRConfigD (0x1 << S_FIRConfigD) | ||
2110 | #define S_FIRConfigPS 18 | ||
2111 | #define M_FIRConfigPS (0x1 << S_FIRConfigPS) | ||
2112 | #define S_FIRConfig3D 19 | ||
2113 | #define M_FIRConfig3D (0x1 << S_FIRConfig3D) | ||
2114 | #define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) | ||
2115 | |||
2116 | #define S_FIRImp 8 | ||
2117 | #define M_FIRImp (0xff << S_FIRImp) | ||
2118 | |||
2119 | #define S_FIRRev 0 | ||
2120 | #define M_FIRRev (0xff << S_FIRRev) | ||
2121 | |||
2122 | #define M_FIR0Fields 0xfff00000 | ||
2123 | #define M_FIRRFields 0x000fffff | ||
2124 | |||
2125 | /* | ||
2126 | ************************************************************************ | ||
2127 | * C O N D I T I O N C O D E S R E G I S T E R * | ||
2128 | ************************************************************************ | ||
2129 | * | ||
2130 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2131 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2132 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2133 | * | 0 | CC | FCCR | ||
2134 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2135 | */ | ||
2136 | |||
2137 | #define C1_FCCR $25 | ||
2138 | #define R_C1_FCCR 25 | ||
2139 | |||
2140 | #define S_FCCRCC 0 | ||
2141 | #define M_FCCRCC (0xff << S_FCCRCC) | ||
2142 | #define S_FCCRCC7 7 | ||
2143 | #define M_FCCRCC7 (0x1 << S_FCCRCC7) | ||
2144 | #define S_FCCRCC6 6 | ||
2145 | #define M_FCCRCC6 (0x1 << S_FCCRCC6) | ||
2146 | #define S_FCCRCC5 5 | ||
2147 | #define M_FCCRCC5 (0x1 << S_FCCRCC5) | ||
2148 | #define S_FCCRCC4 4 | ||
2149 | #define M_FCCRCC4 (0x1 << S_FCCRCC4) | ||
2150 | #define S_FCCRCC3 3 | ||
2151 | #define M_FCCRCC3 (0x1 << S_FCCRCC3) | ||
2152 | #define S_FCCRCC2 2 | ||
2153 | #define M_FCCRCC2 (0x1 << S_FCCRCC2) | ||
2154 | #define S_FCCRCC1 1 | ||
2155 | #define M_FCCRCC1 (0x1 << S_FCCRCC1) | ||
2156 | #define S_FCCRCC0 0 | ||
2157 | #define M_FCCRCC0 (0x1 << S_FCCRCC0) | ||
2158 | |||
2159 | #define M_FCCR0Fields 0xffffff00 | ||
2160 | #define M_FCCRRFields 0x000000ff | ||
2161 | |||
2162 | |||
2163 | /* | ||
2164 | ************************************************************************ | ||
2165 | * E X C E P T I O N S R E G I S T E R * | ||
2166 | ************************************************************************ | ||
2167 | * | ||
2168 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2169 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2170 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2171 | * | 0 | Cause | 0 | Flags | 0 | FEXR | ||
2172 | * | |E|V|Z|O|U|I| |V|Z|O|U|I| | | ||
2173 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2174 | */ | ||
2175 | |||
2176 | #define C1_FEXR $26 | ||
2177 | #define R_C1_FEXR 26 | ||
2178 | |||
2179 | #define S_FEXRExc 12 | ||
2180 | #define M_FEXRExc (0x3f << S_FEXRExc) | ||
2181 | #define S_FEXRExcE 17 | ||
2182 | #define M_FEXRExcE (0x1 << S_FEXRExcE) | ||
2183 | #define S_FEXRExcV 16 | ||
2184 | #define M_FEXRExcV (0x1 << S_FEXRExcV) | ||
2185 | #define S_FEXRExcZ 15 | ||
2186 | #define M_FEXRExcZ (0x1 << S_FEXRExcZ) | ||
2187 | #define S_FEXRExcO 14 | ||
2188 | #define M_FEXRExcO (0x1 << S_FEXRExcO) | ||
2189 | #define S_FEXRExcU 13 | ||
2190 | #define M_FEXRExcU (0x1 << S_FEXRExcU) | ||
2191 | #define S_FEXRExcI 12 | ||
2192 | #define M_FEXRExcI (0x1 << S_FEXRExcI) | ||
2193 | |||
2194 | #define S_FEXRFlg 2 | ||
2195 | #define M_FEXRFlg (0x1f << S_FEXRFlg) | ||
2196 | #define S_FEXRFlgV 6 | ||
2197 | #define M_FEXRFlgV (0x1 << S_FEXRFlgV) | ||
2198 | #define S_FEXRFlgZ 5 | ||
2199 | #define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) | ||
2200 | #define S_FEXRFlgO 4 | ||
2201 | #define M_FEXRFlgO (0x1 << S_FEXRFlgO) | ||
2202 | #define S_FEXRFlgU 3 | ||
2203 | #define M_FEXRFlgU (0x1 << S_FEXRFlgU) | ||
2204 | #define S_FEXRFlgI 2 | ||
2205 | #define M_FEXRFlgI (0x1 << S_FEXRFlgI) | ||
2206 | |||
2207 | #define M_FEXR0Fields 0xfffc0f83 | ||
2208 | #define M_FEXRRFields 0x00000000 | ||
2209 | |||
2210 | |||
2211 | /* | ||
2212 | ************************************************************************ | ||
2213 | * E N A B L E S R E G I S T E R * | ||
2214 | ************************************************************************ | ||
2215 | * | ||
2216 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2217 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2218 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2219 | * | 0 | Enables | 0 |F|RM | FENR | ||
2220 | * | |V|Z|O|U|I| |S| | | ||
2221 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2222 | */ | ||
2223 | |||
2224 | #define C1_FENR $28 | ||
2225 | #define R_C1_FENR 28 | ||
2226 | |||
2227 | #define S_FENREna 7 | ||
2228 | #define M_FENREna (0x1f << S_FENREna) | ||
2229 | #define S_FENREnaV 11 | ||
2230 | #define M_FENREnaV (0x1 << S_FENREnaV) | ||
2231 | #define S_FENREnaZ 10 | ||
2232 | #define M_FENREnaZ (0x1 << S_FENREnaZ) | ||
2233 | #define S_FENREnaO 9 | ||
2234 | #define M_FENREnaO (0x1 << S_FENREnaO) | ||
2235 | #define S_FENREnaU 8 | ||
2236 | #define M_FENREnaU (0x1 << S_FENREnaU) | ||
2237 | #define S_FENREnaI 7 | ||
2238 | #define M_FENREnaI (0x1 << S_FENREnaI) | ||
2239 | |||
2240 | #define S_FENRFS 2 | ||
2241 | #define M_FENRFS (0x1 << S_FENRFS) | ||
2242 | |||
2243 | #define S_FENRRM 0 | ||
2244 | #define M_FENRRM (0x3 << S_FENRRM) | ||
2245 | |||
2246 | #define M_FENR0Fields 0xfffff078 | ||
2247 | #define M_FENRRFields 0x00000000 | ||
2248 | |||
2249 | |||
2250 | /* | ||
2251 | ************************************************************************ | ||
2252 | * C O N T R O L / S T A T U S R E G I S T E R * | ||
2253 | ************************************************************************ | ||
2254 | * | ||
2255 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2256 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2257 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2258 | * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR | ||
2259 | * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | | ||
2260 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2261 | */ | ||
2262 | |||
2263 | #define C1_FCSR $31 | ||
2264 | #define R_C1_FCSR 31 | ||
2265 | |||
2266 | #define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ | ||
2267 | #define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) | ||
2268 | #define S_FCSRCC7 31 | ||
2269 | #define M_FCSRCC7 (0x1 << S_FCSRCC7) | ||
2270 | #define S_FCSRCC6 30 | ||
2271 | #define M_FCSRCC6 (0x1 << S_FCSRCC6) | ||
2272 | #define S_FCSRCC5 29 | ||
2273 | #define M_FCSRCC5 (0x1 << S_FCSRCC5) | ||
2274 | #define S_FCSRCC4 28 | ||
2275 | #define M_FCSRCC4 (0x1 << S_FCSRCC4) | ||
2276 | #define S_FCSRCC3 27 | ||
2277 | #define M_FCSRCC3 (0x1 << S_FCSRCC3) | ||
2278 | #define S_FCSRCC2 26 | ||
2279 | #define M_FCSRCC2 (0x1 << S_FCSRCC2) | ||
2280 | #define S_FCSRCC1 25 | ||
2281 | #define M_FCSRCC1 (0x1 << S_FCSRCC1) | ||
2282 | |||
2283 | #define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ | ||
2284 | #define M_FCSRFS (0x1 << S_FCSRFS) | ||
2285 | |||
2286 | #define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ | ||
2287 | #define M_FCSRCC0 (0x1 << S_FCSRCC0) | ||
2288 | #define S_FCSRCC S_FCSRCC0 | ||
2289 | #define M_FCSRCC M_FCSRCC0 | ||
2290 | |||
2291 | #define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ | ||
2292 | #define M_FCSRImpl (0x3 << S_FCSRImpl) | ||
2293 | |||
2294 | #define S_FCSRExc 12 /* Exception cause (R/W) */ | ||
2295 | #define M_FCSRExc (0x3f << S_FCSRExc) | ||
2296 | #define S_FCSRExcE 17 | ||
2297 | #define M_FCSRExcE (0x1 << S_FCSRExcE) | ||
2298 | #define S_FCSRExcV 16 | ||
2299 | #define M_FCSRExcV (0x1 << S_FCSRExcV) | ||
2300 | #define S_FCSRExcZ 15 | ||
2301 | #define M_FCSRExcZ (0x1 << S_FCSRExcZ) | ||
2302 | #define S_FCSRExcO 14 | ||
2303 | #define M_FCSRExcO (0x1 << S_FCSRExcO) | ||
2304 | #define S_FCSRExcU 13 | ||
2305 | #define M_FCSRExcU (0x1 << S_FCSRExcU) | ||
2306 | #define S_FCSRExcI 12 | ||
2307 | #define M_FCSRExcI (0x1 << S_FCSRExcI) | ||
2308 | |||
2309 | #define S_FCSREna 7 /* Exception enable (R/W) */ | ||
2310 | #define M_FCSREna (0x1f << S_FCSREna) | ||
2311 | #define S_FCSREnaV 11 | ||
2312 | #define M_FCSREnaV (0x1 << S_FCSREnaV) | ||
2313 | #define S_FCSREnaZ 10 | ||
2314 | #define M_FCSREnaZ (0x1 << S_FCSREnaZ) | ||
2315 | #define S_FCSREnaO 9 | ||
2316 | #define M_FCSREnaO (0x1 << S_FCSREnaO) | ||
2317 | #define S_FCSREnaU 8 | ||
2318 | #define M_FCSREnaU (0x1 << S_FCSREnaU) | ||
2319 | #define S_FCSREnaI 7 | ||
2320 | #define M_FCSREnaI (0x1 << S_FCSREnaI) | ||
2321 | |||
2322 | #define S_FCSRFlg 2 /* Exception flags (R/W) */ | ||
2323 | #define M_FCSRFlg (0x1f << S_FCSRFlg) | ||
2324 | #define S_FCSRFlgV 6 | ||
2325 | #define M_FCSRFlgV (0x1 << S_FCSRFlgV) | ||
2326 | #define S_FCSRFlgZ 5 | ||
2327 | #define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) | ||
2328 | #define S_FCSRFlgO 4 | ||
2329 | #define M_FCSRFlgO (0x1 << S_FCSRFlgO) | ||
2330 | #define S_FCSRFlgU 3 | ||
2331 | #define M_FCSRFlgU (0x1 << S_FCSRFlgU) | ||
2332 | #define S_FCSRFlgI 2 | ||
2333 | #define M_FCSRFlgI (0x1 << S_FCSRFlgI) | ||
2334 | |||
2335 | #define S_FCSRRM 0 /* Rounding mode (R/W) */ | ||
2336 | #define M_FCSRRM (0x3 << S_FCSRRM) | ||
2337 | |||
2338 | #define M_FCSR0Fields 0x001c0000 | ||
2339 | #define M_FCSRRFields 0x00000000 | ||
2340 | |||
2341 | /* | ||
2342 | * Values in the rounding mode field (of both FCSR and FCCR) | ||
2343 | */ | ||
2344 | #define K_FCSRRM_RN 0 | ||
2345 | #define K_FCSRRM_RZ 1 | ||
2346 | #define K_FCSRRM_RP 2 | ||
2347 | #define K_FCSRRM_RM 3 | ||
2348 | |||
2349 | |||
2350 | /* ********************************************************************* */ | ||
2351 | /* Interface function definition */ | ||
2352 | |||
2353 | |||
2354 | /* ********************************************************************* */ | ||
2355 | |||
2356 | #endif /* __ARCHDEFS_H__ */ | ||
diff --git a/firmware/export/mips.h b/firmware/export/mips.h new file mode 100755 index 0000000000..6f73d150b2 --- /dev/null +++ b/firmware/export/mips.h | |||
@@ -0,0 +1,820 @@ | |||
1 | /************************************************************************** | ||
2 | * * | ||
3 | * PROJECT : MIPS port for uC/OS-II * | ||
4 | * * | ||
5 | * MODULE : MIPS.h * | ||
6 | * * | ||
7 | * AUTHOR : Michael Anburaj * | ||
8 | * URL : http://geocities.com/michaelanburaj/ * | ||
9 | * EMAIL: michaelanburaj@hotmail.com * | ||
10 | * * | ||
11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * | ||
12 | * * | ||
13 | * TOOL-CHAIN : SDE & Cygnus * | ||
14 | * * | ||
15 | * DESCRIPTION : * | ||
16 | * MIPS processor definitions. * | ||
17 | * The basic CPU definitions are found in the file archdefs.h, which * | ||
18 | * is included by mips.h. * | ||
19 | * * | ||
20 | * mips.h implements aliases for some of the definitions in archdefs.h * | ||
21 | * and adds various definitions. * | ||
22 | * * | ||
23 | **************************************************************************/ | ||
24 | |||
25 | |||
26 | #ifndef __MIPS_H__ | ||
27 | #define __MIPS_H__ | ||
28 | |||
29 | #include "mips-archdefs.h" | ||
30 | |||
31 | |||
32 | /* ********************************************************************* */ | ||
33 | /* Module configuration */ | ||
34 | |||
35 | |||
36 | /* ********************************************************************* */ | ||
37 | /* Interface macro & data definition */ | ||
38 | |||
39 | #ifndef MSK | ||
40 | #define MSK(n) ((1 << (n)) - 1) | ||
41 | #endif | ||
42 | |||
43 | /* CPU registers */ | ||
44 | #define SYS_CPUREG_ZERO 0 | ||
45 | #define SYS_CPUREG_AT 1 | ||
46 | #define SYS_CPUREG_V0 2 | ||
47 | #define SYS_CPUREG_V1 3 | ||
48 | #define SYS_CPUREG_A0 4 | ||
49 | #define SYS_CPUREG_A1 5 | ||
50 | #define SYS_CPUREG_A2 6 | ||
51 | #define SYS_CPUREG_A3 7 | ||
52 | #define SYS_CPUREG_T0 8 | ||
53 | #define SYS_CPUREG_T1 9 | ||
54 | #define SYS_CPUREG_T2 10 | ||
55 | #define SYS_CPUREG_T3 11 | ||
56 | #define SYS_CPUREG_T4 12 | ||
57 | #define SYS_CPUREG_T5 13 | ||
58 | #define SYS_CPUREG_T6 14 | ||
59 | #define SYS_CPUREG_T7 15 | ||
60 | #define SYS_CPUREG_S0 16 | ||
61 | #define SYS_CPUREG_S1 17 | ||
62 | #define SYS_CPUREG_S2 18 | ||
63 | #define SYS_CPUREG_S3 19 | ||
64 | #define SYS_CPUREG_S4 20 | ||
65 | #define SYS_CPUREG_S5 21 | ||
66 | #define SYS_CPUREG_S6 22 | ||
67 | #define SYS_CPUREG_S7 23 | ||
68 | #define SYS_CPUREG_T8 24 | ||
69 | #define SYS_CPUREG_T9 25 | ||
70 | #define SYS_CPUREG_K0 26 | ||
71 | #define SYS_CPUREG_K1 27 | ||
72 | #define SYS_CPUREG_GP 28 | ||
73 | #define SYS_CPUREG_SP 29 | ||
74 | #define SYS_CPUREG_S8 30 | ||
75 | #define SYS_CPUREG_FP SYS_CPUREG_S8 | ||
76 | #define SYS_CPUREG_RA 31 | ||
77 | |||
78 | |||
79 | /* CPU register fp ($30) has an alias s8 */ | ||
80 | #define s8 fp | ||
81 | |||
82 | |||
83 | /* Aliases for System Control Coprocessor (CP0) registers */ | ||
84 | #define C0_INDEX C0_Index | ||
85 | #define C0_RANDOM C0_Random | ||
86 | #define C0_ENTRYLO0 C0_EntryLo0 | ||
87 | #define C0_ENTRYLO1 C0_EntryLo1 | ||
88 | #define C0_CONTEXT C0_Context | ||
89 | #define C0_PAGEMASK C0_PageMask | ||
90 | #define C0_WIRED C0_Wired | ||
91 | #define C0_BADVADDR C0_BadVAddr | ||
92 | #define C0_COUNT C0_Count | ||
93 | #define C0_ENTRYHI C0_EntryHi | ||
94 | #define C0_COMPARE C0_Compare | ||
95 | #define C0_STATUS C0_Status | ||
96 | #define C0_CAUSE C0_Cause | ||
97 | |||
98 | #ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ | ||
99 | #undef C0_PRID | ||
100 | #endif | ||
101 | #define C0_PRID C0_PRId | ||
102 | |||
103 | #define C0_CONFIG C0_Config | ||
104 | #define C0_CONFIG1 C0_Config1 | ||
105 | #define C0_LLADDR C0_LLAddr | ||
106 | #define C0_WATCHLO C0_WatchLo | ||
107 | #define C0_WATCHHI C0_WatchHi | ||
108 | #define C0_DEBUG C0_Debug | ||
109 | #define C0_PERFCNT C0_PerfCnt | ||
110 | #define C0_ERRCTL C0_ErrCtl | ||
111 | #define C0_CACHEERR C0_CacheErr | ||
112 | #define C0_TAGLO C0_TagLo | ||
113 | #define C0_DATALO C0_DataLo | ||
114 | #define C0_TAGHI C0_TagHi | ||
115 | #define C0_DATAHI C0_DataHi | ||
116 | #define C0_ERROREPC C0_ErrorEPC | ||
117 | #if 0 | ||
118 | #define C0_DESAVE C0_DESAVE | ||
119 | #define C0_EPC C0_EPC | ||
120 | #define C0_DEPC C0_DEPC | ||
121 | #endif | ||
122 | |||
123 | /* System Control Coprocessor (CP0) registers select fields */ | ||
124 | #define C0_INDEX_SEL 0 /* TLB Index */ | ||
125 | #define C0_RANDOM_SEL 0 /* TLB Random */ | ||
126 | #define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ | ||
127 | #define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ | ||
128 | #define C0_CONTEXT_SEL 0 /* Context */ | ||
129 | #define C0_PAGEMASK_SEL 0 /* TLB PageMask */ | ||
130 | #define C0_WIRED_SEL 0 /* TLB Wired */ | ||
131 | #define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ | ||
132 | #define C0_COUNT_SEL 0 /* Count */ | ||
133 | #define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ | ||
134 | #define C0_COMPARE_SEL 0 /* Compare */ | ||
135 | #define C0_STATUS_SEL 0 /* Processor Status */ | ||
136 | #define C0_CAUSE_SEL 0 /* Exception Cause */ | ||
137 | #define C0_EPC_SEL 0 /* Exception PC */ | ||
138 | #define C0_PRID_SEL 0 /* Processor Revision Indentifier */ | ||
139 | #define C0_CONFIG_SEL 0 /* Config */ | ||
140 | #define C0_CONFIG1_SEL 1 /* Config1 */ | ||
141 | #define C0_LLADDR_SEL 0 /* LLAddr */ | ||
142 | #define C0_WATCHLO_SEL 0 /* WatchpointLo */ | ||
143 | #define C0_WATCHHI_SEL 0 /* WatchpointHi */ | ||
144 | #define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ | ||
145 | #define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ | ||
146 | #define C0_PERFCNT_SEL 0 /* Performance counter interface */ | ||
147 | #define C0_ERRCTL_SEL 0 /* ERRCTL */ | ||
148 | #define C0_CACHEERR_SEL 0 /* CacheErr */ | ||
149 | #define C0_TAGLO_SEL 0 /* TagLo */ | ||
150 | #define C0_DATALO_SEL 1 /* DataLo */ | ||
151 | #define C0_DTAGLO_SEL 2 /* DTagLo */ | ||
152 | #define C0_TAGHI_SEL 0 /* TagHi */ | ||
153 | #define C0_DATAHI_SEL 1 /* DataHi */ | ||
154 | #define C0_DTAGHI_SEL 2 /* DTagHi */ | ||
155 | #define C0_ERROREPC_SEL 0 /* ErrorEPC */ | ||
156 | #define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ | ||
157 | |||
158 | |||
159 | /* C0_CONFIG register encoding */ | ||
160 | |||
161 | #define C0_CONFIG_M_SHF S_ConfigMore | ||
162 | #define C0_CONFIG_M_MSK M_ConfigMore | ||
163 | #define C0_CONFIG_M_BIT C0_CONFIG_M_MSK | ||
164 | |||
165 | #define C0_CONFIG_BE_SHF S_ConfigBE | ||
166 | #define C0_CONFIG_BE_MSK M_ConfigBE | ||
167 | #define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK | ||
168 | |||
169 | #define C0_CONFIG_AT_SHF S_ConfigAT | ||
170 | #define C0_CONFIG_AT_MSK M_ConfigAT | ||
171 | #define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 | ||
172 | #define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S | ||
173 | #define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 | ||
174 | |||
175 | #define C0_CONFIG_AR_SHF S_ConfigAR | ||
176 | #define C0_CONFIG_AR_MSK M_ConfigAR | ||
177 | |||
178 | #define C0_CONFIG_MT_SHF S_ConfigMT | ||
179 | #define C0_CONFIG_MT_MSK M_ConfigMT | ||
180 | #define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU | ||
181 | #define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU | ||
182 | #define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU | ||
183 | #define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU | ||
184 | |||
185 | #define C0_CONFIG_K0_SHF S_ConfigK0 | ||
186 | #define C0_CONFIG_K0_MSK M_ConfigK0 | ||
187 | #define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA | ||
188 | #define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA | ||
189 | #define C0_CONFIG_K0_UNCACHED K_CacheAttrU | ||
190 | #define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN | ||
191 | #define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE | ||
192 | #define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS | ||
193 | #define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU | ||
194 | #define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA | ||
195 | |||
196 | |||
197 | /* WC field. | ||
198 | * | ||
199 | * This feature is present specifically to support configuration | ||
200 | * testing of the core in a lead vehicle, and is not supported | ||
201 | * in any other environment. Attempting to use this feature | ||
202 | * outside of the scope of a lead vehicle is a violation of the | ||
203 | * MIPS Architecture, and may cause unpredictable operation of | ||
204 | * the processor. | ||
205 | */ | ||
206 | #define C0_CONFIG_WC_SHF 19 | ||
207 | #define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) | ||
208 | #define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK | ||
209 | |||
210 | |||
211 | /* C0_CONFIG1 register encoding */ | ||
212 | |||
213 | #define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize | ||
214 | #define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize | ||
215 | |||
216 | #define C0_CONFIG1_IS_SHF S_Config1IS | ||
217 | #define C0_CONFIG1_IS_MSK M_Config1IS | ||
218 | |||
219 | #define C0_CONFIG1_IL_SHF S_Config1IL | ||
220 | #define C0_CONFIG1_IL_MSK M_Config1IL | ||
221 | |||
222 | #define C0_CONFIG1_IA_SHF S_Config1IA | ||
223 | #define C0_CONFIG1_IA_MSK M_Config1IA | ||
224 | |||
225 | #define C0_CONFIG1_DS_SHF S_Config1DS | ||
226 | #define C0_CONFIG1_DS_MSK M_Config1DS | ||
227 | |||
228 | #define C0_CONFIG1_DL_SHF S_Config1DL | ||
229 | #define C0_CONFIG1_DL_MSK M_Config1DL | ||
230 | |||
231 | #define C0_CONFIG1_DA_SHF S_Config1DA | ||
232 | #define C0_CONFIG1_DA_MSK M_Config1DA | ||
233 | |||
234 | #define C0_CONFIG1_WR_SHF S_Config1WR | ||
235 | #define C0_CONFIG1_WR_MSK M_Config1WR | ||
236 | #define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK | ||
237 | |||
238 | #define C0_CONFIG1_CA_SHF S_Config1CA | ||
239 | #define C0_CONFIG1_CA_MSK M_Config1CA | ||
240 | #define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK | ||
241 | |||
242 | #define C0_CONFIG1_EP_SHF S_Config1EP | ||
243 | #define C0_CONFIG1_EP_MSK M_Config1EP | ||
244 | #define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK | ||
245 | |||
246 | #define C0_CONFIG1_FP_SHF S_Config1FP | ||
247 | #define C0_CONFIG1_FP_MSK M_Config1FP | ||
248 | #define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK | ||
249 | |||
250 | |||
251 | /* C0_STATUS register encoding */ | ||
252 | |||
253 | #define C0_STATUS_CU3_SHF S_StatusCU3 | ||
254 | #define C0_STATUS_CU3_MSK M_StatusCU3 | ||
255 | #define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK | ||
256 | |||
257 | #define C0_STATUS_CU2_SHF S_StatusCU2 | ||
258 | #define C0_STATUS_CU2_MSK M_StatusCU2 | ||
259 | #define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK | ||
260 | |||
261 | #define C0_STATUS_CU1_SHF S_StatusCU1 | ||
262 | #define C0_STATUS_CU1_MSK M_StatusCU1 | ||
263 | #define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK | ||
264 | |||
265 | #define C0_STATUS_CU0_SHF S_StatusCU1 | ||
266 | #define C0_STATUS_CU0_MSK M_StatusCU1 | ||
267 | #define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK | ||
268 | |||
269 | #define C0_STATUS_RP_SHF S_StatusRP | ||
270 | #define C0_STATUS_RP_MSK M_StatusRP | ||
271 | #define C0_STATUS_RP_BIT C0_STATUS_RP_MSK | ||
272 | |||
273 | #define C0_STATUS_FR_SHF S_StatusFR | ||
274 | #define C0_STATUS_FR_MSK M_StatusFR | ||
275 | #define C0_STATUS_FR_BIT C0_STATUS_FR_MSK | ||
276 | |||
277 | #define C0_STATUS_RE_SHF S_StatusRE | ||
278 | #define C0_STATUS_RE_MSK M_StatusRE | ||
279 | #define C0_STATUS_RE_BIT C0_STATUS_RE_MSK | ||
280 | |||
281 | #define C0_STATUS_BEV_SHF S_StatusBEV | ||
282 | #define C0_STATUS_BEV_MSK M_StatusBEV | ||
283 | #define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK | ||
284 | |||
285 | #define C0_STATUS_TS_SHF S_StatusTS | ||
286 | #define C0_STATUS_TS_MSK M_StatusTS | ||
287 | #define C0_STATUS_TS_BIT C0_STATUS_TS_MSK | ||
288 | |||
289 | #define C0_STATUS_SR_SHF S_StatusSR | ||
290 | #define C0_STATUS_SR_MSK M_StatusSR | ||
291 | #define C0_STATUS_SR_BIT C0_STATUS_SR_MSK | ||
292 | |||
293 | #define C0_STATUS_NMI_SHF S_StatusNMI | ||
294 | #define C0_STATUS_NMI_MSK M_StatusNMI | ||
295 | #define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK | ||
296 | |||
297 | #define C0_STATUS_IM_SHF S_StatusIM | ||
298 | #define C0_STATUS_IM_MSK M_StatusIM | ||
299 | /* Note that the the definitions below indicate the interrupt number | ||
300 | * rather than the mask. | ||
301 | * (0..1 for SW interrupts and 2...7 for HW interrupts) | ||
302 | */ | ||
303 | #define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) | ||
304 | #define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) | ||
305 | #define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) | ||
306 | #define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) | ||
307 | #define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) | ||
308 | #define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) | ||
309 | #define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) | ||
310 | #define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) | ||
311 | |||
312 | /* Max interrupt code */ | ||
313 | #define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 | ||
314 | |||
315 | #define C0_STATUS_KSU_SHF S_StatusKSU | ||
316 | #define C0_STATUS_KSU_MSK M_StatusKSU | ||
317 | |||
318 | #define C0_STATUS_UM_SHF S_StatusUM | ||
319 | #define C0_STATUS_UM_MSK M_StatusUM | ||
320 | #define C0_STATUS_UM_BIT C0_STATUS_UM_MSK | ||
321 | |||
322 | #define C0_STATUS_ERL_SHF S_StatusERL | ||
323 | #define C0_STATUS_ERL_MSK M_StatusERL | ||
324 | #define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK | ||
325 | |||
326 | #define C0_STATUS_EXL_SHF S_StatusEXL | ||
327 | #define C0_STATUS_EXL_MSK M_StatusEXL | ||
328 | #define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK | ||
329 | |||
330 | #define C0_STATUS_IE_SHF S_StatusIE | ||
331 | #define C0_STATUS_IE_MSK M_StatusIE | ||
332 | #define C0_STATUS_IE_BIT C0_STATUS_IE_MSK | ||
333 | |||
334 | |||
335 | /* C0_PRID register encoding */ | ||
336 | |||
337 | #define C0_PRID_OPT_SHF S_PRIdCoOpt | ||
338 | #define C0_PRID_OPT_MSK M_PRIdCoOpt | ||
339 | |||
340 | #define C0_PRID_COMP_SHF S_PRIdCoID | ||
341 | #define C0_PRID_COMP_MSK M_PRIdCoID | ||
342 | #define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS | ||
343 | #define C0_PRID_COMP_NOT_MIPS32_64 0 | ||
344 | |||
345 | #define C0_PRID_PRID_SHF S_PRIdImp | ||
346 | #define C0_PRID_PRID_MSK M_PRIdImp | ||
347 | |||
348 | /* Jade */ | ||
349 | #define C0_PRID_PRID_4Kc K_PRIdImp_Jade | ||
350 | #define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ | ||
351 | /* Emerald */ | ||
352 | #define C0_PRID_PRID_4KEc K_PRIdImp_4KEc | ||
353 | #define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp | ||
354 | /* Coral */ | ||
355 | #define C0_PRID_PRID_4KSc K_PRIdImp_4KSc | ||
356 | /* Opal */ | ||
357 | #define C0_PRID_PRID_5K K_PRIdImp_Opal | ||
358 | /* Ruby */ | ||
359 | #define C0_PRID_PRID_20Kc K_PRIdImp_Ruby | ||
360 | /* Other CPUs */ | ||
361 | #define C0_PRID_PRID_R4000 K_PRIdImp_R4000 | ||
362 | #define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 | ||
363 | #define C0_PRID_PRID_RM70XX 0x27 | ||
364 | |||
365 | #define C0_PRID_REV_SHF S_PRIdRev | ||
366 | #define C0_PRID_REV_MSK M_PRIdRev | ||
367 | |||
368 | |||
369 | #define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ | ||
370 | C0_PRID_COMP_SHF) | \ | ||
371 | (C0_PRID_PRID_4Kc << \ | ||
372 | C0_PRID_PRID_SHF) \ | ||
373 | ) | ||
374 | |||
375 | #define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ | ||
376 | C0_PRID_COMP_SHF) | \ | ||
377 | (C0_PRID_PRID_4Kmp << \ | ||
378 | C0_PRID_PRID_SHF) \ | ||
379 | ) | ||
380 | |||
381 | #define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ | ||
382 | C0_PRID_COMP_SHF) | \ | ||
383 | (C0_PRID_PRID_4KEc << \ | ||
384 | C0_PRID_PRID_SHF) \ | ||
385 | ) | ||
386 | |||
387 | #define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ | ||
388 | C0_PRID_COMP_SHF) | \ | ||
389 | (C0_PRID_PRID_4KEmp << \ | ||
390 | C0_PRID_PRID_SHF) \ | ||
391 | ) | ||
392 | |||
393 | #define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ | ||
394 | C0_PRID_COMP_SHF) | \ | ||
395 | (C0_PRID_PRID_4KSc << \ | ||
396 | C0_PRID_PRID_SHF) \ | ||
397 | ) | ||
398 | |||
399 | #define MIPS_5K ( (C0_PRID_COMP_MIPS << \ | ||
400 | C0_PRID_COMP_SHF) | \ | ||
401 | (C0_PRID_PRID_5K << \ | ||
402 | C0_PRID_PRID_SHF) \ | ||
403 | ) | ||
404 | |||
405 | #define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ | ||
406 | C0_PRID_COMP_SHF) | \ | ||
407 | (C0_PRID_PRID_20Kc << \ | ||
408 | C0_PRID_PRID_SHF) \ | ||
409 | ) | ||
410 | |||
411 | #define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
412 | C0_PRID_COMP_SHF) | \ | ||
413 | (C0_PRID_PRID_RM52XX << \ | ||
414 | C0_PRID_PRID_SHF) \ | ||
415 | ) | ||
416 | |||
417 | #define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
418 | C0_PRID_COMP_SHF) | \ | ||
419 | (C0_PRID_PRID_RM70XX << \ | ||
420 | C0_PRID_PRID_SHF) \ | ||
421 | ) | ||
422 | |||
423 | /* C0_ENTRYHI register encoding */ | ||
424 | |||
425 | #define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 | ||
426 | #define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 | ||
427 | |||
428 | #define C0_ENTRYHI_ASID_SHF S_EntryHiASID | ||
429 | #define C0_ENTRYHI_ASID_MSK M_EntryHiASID | ||
430 | |||
431 | |||
432 | /* C0_CAUSE register encoding */ | ||
433 | |||
434 | #define C0_CAUSE_BD_SHF S_CauseBD | ||
435 | #define C0_CAUSE_BD_MSK M_CauseBD | ||
436 | #define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK | ||
437 | |||
438 | #define C0_CAUSE_CE_SHF S_CauseCE | ||
439 | #define C0_CAUSE_CE_MSK M_CauseCE | ||
440 | |||
441 | #define C0_CAUSE_IV_SHF S_CauseIV | ||
442 | #define C0_CAUSE_IV_MSK M_CauseIV | ||
443 | #define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK | ||
444 | |||
445 | #define C0_CAUSE_WP_SHF S_CauseWP | ||
446 | #define C0_CAUSE_WP_MSK M_CauseWP | ||
447 | #define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK | ||
448 | |||
449 | #define C0_CAUSE_IP_SHF S_CauseIP | ||
450 | #define C0_CAUSE_IP_MSK M_CauseIP | ||
451 | |||
452 | #define C0_CAUSE_CODE_SHF S_CauseExcCode | ||
453 | #define C0_CAUSE_CODE_MSK M_CauseExcCode | ||
454 | |||
455 | #define C0_CAUSE_CODE_INT EX_INT | ||
456 | #define C0_CAUSE_CODE_MOD EX_MOD | ||
457 | #define C0_CAUSE_CODE_TLBL EX_TLBL | ||
458 | #define C0_CAUSE_CODE_TLBS EX_TLBS | ||
459 | #define C0_CAUSE_CODE_ADEL EX_ADEL | ||
460 | #define C0_CAUSE_CODE_ADES EX_ADES | ||
461 | #define C0_CAUSE_CODE_IBE EX_IBE | ||
462 | #define C0_CAUSE_CODE_DBE EX_DBE | ||
463 | #define C0_CAUSE_CODE_SYS EX_SYS | ||
464 | #define C0_CAUSE_CODE_BP EX_BP | ||
465 | #define C0_CAUSE_CODE_RI EX_RI | ||
466 | #define C0_CAUSE_CODE_CPU EX_CPU | ||
467 | #define C0_CAUSE_CODE_OV EX_OV | ||
468 | #define C0_CAUSE_CODE_TR EV_TR | ||
469 | #define C0_CAUSE_CODE_FPE EX_FPE | ||
470 | #define C0_CAUSE_CODE_WATCH EX_WATCH | ||
471 | #define C0_CAUSE_CODE_MCHECK EX_MCHECK | ||
472 | |||
473 | /* Max cause code */ | ||
474 | #define C0_CAUSE_CODE_MAX EX_MCHECK | ||
475 | |||
476 | |||
477 | /* C0_PAGEMASK register encoding */ | ||
478 | #define C0_PAGEMASK_MASK_SHF S_PageMaskMask | ||
479 | #define C0_PAGEMASK_MASK_MSK M_PageMaskMask | ||
480 | #define C0_PAGEMASK_MASK_4K K_PageMask4K | ||
481 | #define C0_PAGEMASK_MASK_16K K_PageMask16K | ||
482 | #define C0_PAGEMASK_MASK_64K K_PageMask64K | ||
483 | #define C0_PAGEMASK_MASK_256K K_PageMask256K | ||
484 | #define C0_PAGEMASK_MASK_1M K_PageMask1M | ||
485 | #define C0_PAGEMASK_MASK_4M K_PageMask4M | ||
486 | #define C0_PAGEMASK_MASK_16M K_PageMask16M | ||
487 | |||
488 | |||
489 | /* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ | ||
490 | #define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN | ||
491 | #define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN | ||
492 | |||
493 | #define C0_ENTRYLO0_C_SHF S_EntryLoC | ||
494 | #define C0_ENTRYLO0_C_MSK M_EntryLoC | ||
495 | |||
496 | #define C0_ENTRYLO0_D_SHF S_EntryLoD | ||
497 | #define C0_ENTRYLO0_D_MSK M_EntryLoD | ||
498 | |||
499 | #define C0_ENTRYLO0_V_SHF S_EntryLoV | ||
500 | #define C0_ENTRYLO0_V_MSK M_EntryLoV | ||
501 | |||
502 | #define C0_ENTRYLO0_G_SHF S_EntryLoG | ||
503 | #define C0_ENTRYLO0_G_MSK M_EntryLoG | ||
504 | |||
505 | |||
506 | /* FPU (CP1) FIR register encoding */ | ||
507 | #define C1_FIR_3D_SHF S_FIRConfig3D | ||
508 | #define C1_FIR_3D_MSK M_FIRConfig3D | ||
509 | |||
510 | #define C1_FIR_PS_SHF S_FIRConfigPS | ||
511 | #define C1_FIR_PS_MSK M_FIRConfigPS | ||
512 | |||
513 | #define C1_FIR_D_SHF S_FIRConfigD | ||
514 | #define C1_FIR_D_MSK M_FIRConfigD | ||
515 | |||
516 | #define C1_FIR_S_SHF S_FIRConfigS | ||
517 | #define C1_FIR_S_MSK M_FIRConfigS | ||
518 | |||
519 | #define C1_FIR_PRID_SHF S_FIRImp | ||
520 | #define C1_FIR_PRID_MSK M_FIRImp | ||
521 | |||
522 | #define C1_FIR_REV_SHF S_FIRRev | ||
523 | #define C1_FIR_REV_MSK M_FIRRev | ||
524 | |||
525 | |||
526 | /* FPU (CP1) FCSR control/status register */ | ||
527 | #define C1_FCSR_FCC_SHF S_FCSRFCC7_1 | ||
528 | #define C1_FCSR_FCC_MSK M_FCSRFCC7_1 | ||
529 | |||
530 | #define C1_FCSR_FS_SHF S_FCSRFS | ||
531 | #define C1_FCSR_FS_MSK M_FCSRFS | ||
532 | #define C1_FCSR_FS_BIT C1_FCSR_FS_MSK | ||
533 | |||
534 | #define C1_FCSR_CC_SHF S_FCSRCC | ||
535 | #define C1_FCSR_CC_MSK M_FCSRCC | ||
536 | |||
537 | #define C1_FCSR_IMPL_SHF S_FCSRImpl | ||
538 | #define C1_FCSR_IMPL_MSK M_FCSRImpl | ||
539 | |||
540 | #define C1_FCSR_EXC_SHF S_FCSRExc | ||
541 | #define C1_FCSR_EXC_MSK M_FCSRExc | ||
542 | |||
543 | #define C1_FCSR_ENA_SHF S_FCSREna | ||
544 | #define C1_FCSR_ENA_MSK M_FCSREna | ||
545 | |||
546 | #define C1_FCSR_FLG_SHF S_FCSRFlg | ||
547 | #define C1_FCSR_FLG_MSK M_FCSRFlg | ||
548 | |||
549 | #define C1_FCSR_RM_SHF S_FCSRRM | ||
550 | #define C1_FCSR_RM_MSK M_FCSRRM | ||
551 | #define C1_FCSR_RM_RN K_FCSRRM_RN | ||
552 | #define C1_FCSR_RM_RZ K_FCSRRM_RZ | ||
553 | #define C1_FCSR_RM_RP K_FCSRRM_RP | ||
554 | #define C1_FCSR_RM_RM K_FCSRRM_RM | ||
555 | |||
556 | |||
557 | |||
558 | /* cache operations */ | ||
559 | |||
560 | #define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) | ||
561 | |||
562 | #define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) | ||
563 | #define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) | ||
564 | #define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) | ||
565 | #define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) | ||
566 | #define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) | ||
567 | #define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) | ||
568 | #define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) | ||
569 | |||
570 | #define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) | ||
571 | #define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) | ||
572 | #define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) | ||
573 | #define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) | ||
574 | #define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) | ||
575 | #define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) | ||
576 | #define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) | ||
577 | |||
578 | #define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) | ||
579 | |||
580 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
581 | * processors. Only relevant in early engineering samples of test | ||
582 | * chips (RTL revision <= 3.0). | ||
583 | * | ||
584 | * The bug is described in : | ||
585 | * | ||
586 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
587 | * MIPS Document No: MD00003 | ||
588 | * | ||
589 | * The bug is identified as : C16 | ||
590 | */ | ||
591 | #ifndef SET_MIPS0 | ||
592 | #define SET_MIPS0() | ||
593 | #define SET_PUSH() | ||
594 | #define SET_POP() | ||
595 | #endif | ||
596 | #define ICACHE_INVALIDATE_WORKAROUND(reg) \ | ||
597 | SET_PUSH(); \ | ||
598 | SET_MIPS0(); \ | ||
599 | la reg, 999f; \ | ||
600 | SET_POP(); \ | ||
601 | cache ICACHE_ADDR_FILL, 0(reg); \ | ||
602 | sync; \ | ||
603 | nop; nop; nop; nop; \ | ||
604 | 999: | ||
605 | |||
606 | /* EMPTY_PIPELINE is used for the below cache invalidation operations. | ||
607 | * When $I is invalidated, there will still be operations in the | ||
608 | * pipeline. We make sure these are 'nop' operations. | ||
609 | */ | ||
610 | #define EMPTY_PIPELINE nop; nop; nop; nop | ||
611 | |||
612 | #define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ | ||
613 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
614 | cache ICACHE_INDEX_INVALIDATE, 0(index); \ | ||
615 | EMPTY_PIPELINE | ||
616 | |||
617 | #define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ | ||
618 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
619 | cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ | ||
620 | EMPTY_PIPELINE | ||
621 | |||
622 | /* The sync used in the below macro is there in case we are installing | ||
623 | * a new instruction (flush $D, sync, invalidate $I sequence). | ||
624 | */ | ||
625 | #define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ | ||
626 | cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ | ||
627 | sync; \ | ||
628 | EMPTY_PIPELINE | ||
629 | |||
630 | /* Config1 cache field decoding */ | ||
631 | #define CACHE_CALC_SPW(s) ( 64 << (s) ) | ||
632 | #define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) | ||
633 | #define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) | ||
634 | #define CACHE_CALC_ASSOC(a) ( (a) + 1 ) | ||
635 | |||
636 | |||
637 | /**** Move from/to Coprocessor operations ****/ | ||
638 | |||
639 | /* We use ssnop instead of nop operations in order to handle | ||
640 | * superscalar CPUs. | ||
641 | * The "sll zero,zero,1" notation is compiler backwards compatible. | ||
642 | */ | ||
643 | #define SSNOP sll zero,zero,1 | ||
644 | #define NOPS SSNOP; SSNOP; SSNOP; SSNOP | ||
645 | |||
646 | #define MFLO(dst) \ | ||
647 | mflo dst;\ | ||
648 | NOPS | ||
649 | |||
650 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
651 | * processors. | ||
652 | * | ||
653 | * This concerns the nop instruction before mtc0 in the | ||
654 | * MTC0 macro below. | ||
655 | * | ||
656 | * The bug is described in : | ||
657 | * | ||
658 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
659 | * MIPS Document No: MD00003 | ||
660 | * | ||
661 | * The bug is identified as : C27 | ||
662 | */ | ||
663 | |||
664 | #define MTC0(src, dst) \ | ||
665 | nop; \ | ||
666 | mtc0 src,dst;\ | ||
667 | NOPS | ||
668 | |||
669 | #define DMTC0(src, dst) \ | ||
670 | nop; \ | ||
671 | dmtc0 src,dst;\ | ||
672 | NOPS | ||
673 | |||
674 | #define MFC0(dst, src) \ | ||
675 | mfc0 dst,src;\ | ||
676 | NOPS | ||
677 | |||
678 | #define DMFC0(dst, src) \ | ||
679 | dmfc0 dst,src;\ | ||
680 | NOPS | ||
681 | |||
682 | #define MFC0_SEL_OPCODE(dst, src, sel)\ | ||
683 | .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
684 | NOPS | ||
685 | |||
686 | #define MTC0_SEL_OPCODE(dst, src, sel)\ | ||
687 | .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
688 | NOPS | ||
689 | |||
690 | #define LDC1(dst, src, offs)\ | ||
691 | .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) | ||
692 | |||
693 | #define SDC1(src, dst, offs)\ | ||
694 | .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) | ||
695 | |||
696 | |||
697 | /* Instruction opcode fields */ | ||
698 | #define OPC_SPECIAL 0x0 | ||
699 | #define OPC_REGIM 0x1 | ||
700 | #define OPC_J 0x2 | ||
701 | #define OPC_JAL 0x3 | ||
702 | #define OPC_BEQ 0x4 | ||
703 | #define OPC_BNE 0x5 | ||
704 | #define OPC_BLEZ 0x6 | ||
705 | #define OPC_BGTZ 0x7 | ||
706 | #define OPC_COP1 0x11 | ||
707 | #define OPC_JALX 0x1D | ||
708 | #define OPC_BEQL 0x14 | ||
709 | #define OPC_BNEL 0x15 | ||
710 | #define OPC_BLEZL 0x16 | ||
711 | #define OPC_BGTZL 0x17 | ||
712 | |||
713 | /* Instruction function fields */ | ||
714 | #define FUNC_JR 0x8 | ||
715 | #define FUNC_JALR 0x9 | ||
716 | |||
717 | /* Instruction rt fields */ | ||
718 | #define RT_BLTZ 0x0 | ||
719 | #define RT_BGEZ 0x1 | ||
720 | #define RT_BLTZL 0x2 | ||
721 | #define RT_BGEZL 0x3 | ||
722 | #define RT_BLTZAL 0x10 | ||
723 | #define RT_BGEZAL 0x11 | ||
724 | #define RT_BLTZALL 0x12 | ||
725 | #define RT_BGEZALL 0x13 | ||
726 | |||
727 | /* Instruction rs fields */ | ||
728 | #define RS_BC1 0x08 | ||
729 | |||
730 | /* Access macros for instruction fields */ | ||
731 | #define MIPS_OPCODE( instr) ((instr) >> 26) | ||
732 | #define MIPS_FUNCTION(instr) ((instr) & MSK(6)) | ||
733 | #define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) | ||
734 | #define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) | ||
735 | #define MIPS_OFFSET(instr) ((instr) & 0xFFFF) | ||
736 | #define MIPS_TARGET(instr) ((instr) & MSK(26)) | ||
737 | |||
738 | /* Instructions */ | ||
739 | #define OPCODE_DERET 0x4200001f | ||
740 | #define OPCODE_BREAK 0x0005000d | ||
741 | #define OPCODE_NOP 0 | ||
742 | #define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) | ||
743 | |||
744 | #define DERET .##word OPCODE_DERET | ||
745 | |||
746 | /* MIPS16e opcodes and instruction field access macros */ | ||
747 | |||
748 | #define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) | ||
749 | #define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) | ||
750 | #define MIPS16E_X(inst) (((inst) >> 26) & 0x1) | ||
751 | #define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) | ||
752 | #define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) | ||
753 | #define MIPS16E_OPC_EXTEND 0x1e | ||
754 | #define MIPS16E_OPC_JAL_X 0x03 | ||
755 | #define MIPS16E_OPC_B 0x02 | ||
756 | #define MIPS16E_OPC_BEQZ 0x04 | ||
757 | #define MIPS16E_OPC_BNEZ 0x05 | ||
758 | #define MIPS16E_OPC_I8 0x0c | ||
759 | #define MIPS16E_I8_FUNC_BTEQZ 0x00 | ||
760 | #define MIPS16E_I8_FUNC_BTNEZ 0x01 | ||
761 | #define MIPS16E_X_JALX 0x01 | ||
762 | #define MIPS16E_OPC_RR 0x1d | ||
763 | #define MIPS16E_RR_FUNC_JALRC 0x00 | ||
764 | #define MIPS16E_RR_RY_JRRX 0x00 | ||
765 | #define MIPS16E_RR_RY_JRRA 0x01 | ||
766 | #define MIPS16E_RR_RY_JALR 0x02 | ||
767 | #define MIPS16E_RR_RY_JRCRX 0x04 | ||
768 | #define MIPS16E_RR_RY_JRCRA 0x05 | ||
769 | #define MIPS16E_RR_RY_JALRC 0x06 | ||
770 | |||
771 | #define MIPS16E_OPCODE_BREAK 0xE805 | ||
772 | #define MIPS16E_OPCODE_NOP 0x6500 | ||
773 | |||
774 | /* MIPS reset vector */ | ||
775 | #define MIPS_RESET_VECTOR 0x1fc00000 | ||
776 | |||
777 | /* Clock periods per count register increment */ | ||
778 | #define MIPS4K_COUNT_CLK_PER_CYCLE 2 | ||
779 | #define MIPS5K_COUNT_CLK_PER_CYCLE 2 | ||
780 | #define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 | ||
781 | |||
782 | |||
783 | /**** MIPS 4K/5K families specific fields of CONFIG register ****/ | ||
784 | |||
785 | #define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23 | ||
786 | #define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF) | ||
787 | |||
788 | #define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU | ||
789 | #define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF) | ||
790 | |||
791 | |||
792 | /**** MIPS 20Kc specific fields of CONFIG register ****/ | ||
793 | |||
794 | #define C0_CONFIG_MIPS20KC_EC_SHF 28 | ||
795 | #define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF) | ||
796 | |||
797 | #define C0_CONFIG_MIPS20KC_DD_SHF 27 | ||
798 | #define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF) | ||
799 | #define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK | ||
800 | |||
801 | #define C0_CONFIG_MIPS20KC_LP_SHF 26 | ||
802 | #define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF) | ||
803 | #define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK | ||
804 | |||
805 | #define C0_CONFIG_MIPS20KC_SP_SHF 25 | ||
806 | #define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF) | ||
807 | #define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK | ||
808 | |||
809 | #define C0_CONFIG_MIPS20KC_TI_SHF 24 | ||
810 | #define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF) | ||
811 | #define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK | ||
812 | |||
813 | |||
814 | /* ********************************************************************* */ | ||
815 | /* Interface function definition */ | ||
816 | |||
817 | |||
818 | /* ********************************************************************* */ | ||
819 | |||
820 | #endif /* #ifndef __MIPS_H__ */ | ||
diff --git a/firmware/export/mipsregs.h b/firmware/export/mipsregs.h new file mode 100755 index 0000000000..e2935e3024 --- /dev/null +++ b/firmware/export/mipsregs.h | |||
@@ -0,0 +1,985 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle | ||
7 | * Copyright (C) 2000 Silicon Graphics, Inc. | ||
8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | ||
9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | ||
10 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | ||
11 | * Copyright (C) 2003 Maciej W. Rozycki | ||
12 | */ | ||
13 | #ifndef _ASM_MIPSREGS_H | ||
14 | #define _ASM_MIPSREGS_H | ||
15 | |||
16 | //#include <linux/config.h> | ||
17 | //#include <linux/linkage.h> | ||
18 | |||
19 | /* | ||
20 | * The following macros are especially useful for __asm__ | ||
21 | * inline assembler. | ||
22 | */ | ||
23 | #ifndef __STR | ||
24 | #define __STR(x) #x | ||
25 | #endif | ||
26 | #ifndef STR | ||
27 | #define STR(x) __STR(x) | ||
28 | #endif | ||
29 | |||
30 | /* | ||
31 | * Configure language | ||
32 | */ | ||
33 | #ifdef __ASSEMBLY__ | ||
34 | #define _ULCAST_ | ||
35 | #else | ||
36 | #define _ULCAST_ (unsigned long) | ||
37 | #endif | ||
38 | |||
39 | /* | ||
40 | * Coprocessor 0 register names | ||
41 | */ | ||
42 | #define CP0_INDEX $0 | ||
43 | #define CP0_RANDOM $1 | ||
44 | #define CP0_ENTRYLO0 $2 | ||
45 | #define CP0_ENTRYLO1 $3 | ||
46 | #define CP0_CONF $3 | ||
47 | #define CP0_CONTEXT $4 | ||
48 | #define CP0_PAGEMASK $5 | ||
49 | #define CP0_WIRED $6 | ||
50 | #define CP0_INFO $7 | ||
51 | #define CP0_BADVADDR $8 | ||
52 | #define CP0_COUNT $9 | ||
53 | #define CP0_ENTRYHI $10 | ||
54 | #define CP0_COMPARE $11 | ||
55 | #define CP0_STATUS $12 | ||
56 | #define CP0_CAUSE $13 | ||
57 | #define CP0_EPC $14 | ||
58 | #define CP0_PRID $15 | ||
59 | #define CP0_CONFIG $16 | ||
60 | #define CP0_LLADDR $17 | ||
61 | #define CP0_WATCHLO $18 | ||
62 | #define CP0_WATCHHI $19 | ||
63 | #define CP0_XCONTEXT $20 | ||
64 | #define CP0_FRAMEMASK $21 | ||
65 | #define CP0_DIAGNOSTIC $22 | ||
66 | #define CP0_DEBUG $23 | ||
67 | #define CP0_DEPC $24 | ||
68 | #define CP0_PERFORMANCE $25 | ||
69 | #define CP0_ECC $26 | ||
70 | #define CP0_CACHEERR $27 | ||
71 | #define CP0_TAGLO $28 | ||
72 | #define CP0_TAGHI $29 | ||
73 | #define CP0_ERROREPC $30 | ||
74 | #define CP0_DESAVE $31 | ||
75 | |||
76 | /* | ||
77 | * R4640/R4650 cp0 register names. These registers are listed | ||
78 | * here only for completeness; without MMU these CPUs are not useable | ||
79 | * by Linux. A future ELKS port might take make Linux run on them | ||
80 | * though ... | ||
81 | */ | ||
82 | #define CP0_IBASE $0 | ||
83 | #define CP0_IBOUND $1 | ||
84 | #define CP0_DBASE $2 | ||
85 | #define CP0_DBOUND $3 | ||
86 | #define CP0_CALG $17 | ||
87 | #define CP0_IWATCH $18 | ||
88 | #define CP0_DWATCH $19 | ||
89 | |||
90 | /* | ||
91 | * Coprocessor 0 Set 1 register names | ||
92 | */ | ||
93 | #define CP0_S1_DERRADDR0 $26 | ||
94 | #define CP0_S1_DERRADDR1 $27 | ||
95 | #define CP0_S1_INTCONTROL $20 | ||
96 | |||
97 | /* | ||
98 | * TX39 Series | ||
99 | */ | ||
100 | #define CP0_TX39_CACHE $7 | ||
101 | |||
102 | /* | ||
103 | * Coprocessor 1 (FPU) register names | ||
104 | */ | ||
105 | #define CP1_REVISION $0 | ||
106 | #define CP1_STATUS $31 | ||
107 | |||
108 | /* | ||
109 | * FPU Status Register Values | ||
110 | */ | ||
111 | /* | ||
112 | * Status Register Values | ||
113 | */ | ||
114 | |||
115 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ | ||
116 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ | ||
117 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ | ||
118 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ | ||
119 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ | ||
120 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ | ||
121 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ | ||
122 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ | ||
123 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ | ||
124 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ | ||
125 | |||
126 | /* | ||
127 | * X the exception cause indicator | ||
128 | * E the exception enable | ||
129 | * S the sticky/flag bit | ||
130 | */ | ||
131 | #define FPU_CSR_ALL_X 0x0003f000 | ||
132 | #define FPU_CSR_UNI_X 0x00020000 | ||
133 | #define FPU_CSR_INV_X 0x00010000 | ||
134 | #define FPU_CSR_DIV_X 0x00008000 | ||
135 | #define FPU_CSR_OVF_X 0x00004000 | ||
136 | #define FPU_CSR_UDF_X 0x00002000 | ||
137 | #define FPU_CSR_INE_X 0x00001000 | ||
138 | |||
139 | #define FPU_CSR_ALL_E 0x00000f80 | ||
140 | #define FPU_CSR_INV_E 0x00000800 | ||
141 | #define FPU_CSR_DIV_E 0x00000400 | ||
142 | #define FPU_CSR_OVF_E 0x00000200 | ||
143 | #define FPU_CSR_UDF_E 0x00000100 | ||
144 | #define FPU_CSR_INE_E 0x00000080 | ||
145 | |||
146 | #define FPU_CSR_ALL_S 0x0000007c | ||
147 | #define FPU_CSR_INV_S 0x00000040 | ||
148 | #define FPU_CSR_DIV_S 0x00000020 | ||
149 | #define FPU_CSR_OVF_S 0x00000010 | ||
150 | #define FPU_CSR_UDF_S 0x00000008 | ||
151 | #define FPU_CSR_INE_S 0x00000004 | ||
152 | |||
153 | /* rounding mode */ | ||
154 | #define FPU_CSR_RN 0x0 /* nearest */ | ||
155 | #define FPU_CSR_RZ 0x1 /* towards zero */ | ||
156 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | ||
157 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | ||
158 | |||
159 | |||
160 | /* | ||
161 | * Values for PageMask register | ||
162 | */ | ||
163 | #ifdef CONFIG_CPU_VR41XX | ||
164 | |||
165 | /* Why doesn't stupidity hurt ... */ | ||
166 | |||
167 | #define PM_1K 0x00000000 | ||
168 | #define PM_4K 0x00001800 | ||
169 | #define PM_16K 0x00007800 | ||
170 | #define PM_64K 0x0001f800 | ||
171 | #define PM_256K 0x0007f800 | ||
172 | |||
173 | #else | ||
174 | |||
175 | #define PM_4K 0x00000000 | ||
176 | #define PM_16K 0x00006000 | ||
177 | #define PM_64K 0x0001e000 | ||
178 | #define PM_256K 0x0007e000 | ||
179 | #define PM_1M 0x001fe000 | ||
180 | #define PM_4M 0x007fe000 | ||
181 | #define PM_16M 0x01ffe000 | ||
182 | #define PM_64M 0x07ffe000 | ||
183 | #define PM_256M 0x1fffe000 | ||
184 | |||
185 | #endif | ||
186 | |||
187 | /* | ||
188 | * Values used for computation of new tlb entries | ||
189 | */ | ||
190 | #define PL_4K 12 | ||
191 | #define PL_16K 14 | ||
192 | #define PL_64K 16 | ||
193 | #define PL_256K 18 | ||
194 | #define PL_1M 20 | ||
195 | #define PL_4M 22 | ||
196 | #define PL_16M 24 | ||
197 | #define PL_64M 26 | ||
198 | #define PL_256M 28 | ||
199 | |||
200 | /* | ||
201 | * R4x00 interrupt enable / cause bits | ||
202 | */ | ||
203 | #define IE_SW0 (_ULCAST_(1) << 8) | ||
204 | #define IE_SW1 (_ULCAST_(1) << 9) | ||
205 | #define IE_IRQ0 (_ULCAST_(1) << 10) | ||
206 | #define IE_IRQ1 (_ULCAST_(1) << 11) | ||
207 | #define IE_IRQ2 (_ULCAST_(1) << 12) | ||
208 | #define IE_IRQ3 (_ULCAST_(1) << 13) | ||
209 | #define IE_IRQ4 (_ULCAST_(1) << 14) | ||
210 | #define IE_IRQ5 (_ULCAST_(1) << 15) | ||
211 | |||
212 | /* | ||
213 | * R4x00 interrupt cause bits | ||
214 | */ | ||
215 | #define C_SW0 (_ULCAST_(1) << 8) | ||
216 | #define C_SW1 (_ULCAST_(1) << 9) | ||
217 | #define C_IRQ0 (_ULCAST_(1) << 10) | ||
218 | #define C_IRQ1 (_ULCAST_(1) << 11) | ||
219 | #define C_IRQ2 (_ULCAST_(1) << 12) | ||
220 | #define C_IRQ3 (_ULCAST_(1) << 13) | ||
221 | #define C_IRQ4 (_ULCAST_(1) << 14) | ||
222 | #define C_IRQ5 (_ULCAST_(1) << 15) | ||
223 | |||
224 | /* | ||
225 | * Bitfields in the R4xx0 cp0 status register | ||
226 | */ | ||
227 | #define ST0_IE 0x00000001 | ||
228 | #define ST0_EXL 0x00000002 | ||
229 | #define ST0_ERL 0x00000004 | ||
230 | #define ST0_KSU 0x00000018 | ||
231 | # define KSU_USER 0x00000010 | ||
232 | # define KSU_SUPERVISOR 0x00000008 | ||
233 | # define KSU_KERNEL 0x00000000 | ||
234 | #define ST0_UX 0x00000020 | ||
235 | #define ST0_SX 0x00000040 | ||
236 | #define ST0_KX 0x00000080 | ||
237 | #define ST0_DE 0x00010000 | ||
238 | #define ST0_CE 0x00020000 | ||
239 | |||
240 | /* | ||
241 | * Bitfields in the R[23]000 cp0 status register. | ||
242 | */ | ||
243 | #define ST0_IEC 0x00000001 | ||
244 | #define ST0_KUC 0x00000002 | ||
245 | #define ST0_IEP 0x00000004 | ||
246 | #define ST0_KUP 0x00000008 | ||
247 | #define ST0_IEO 0x00000010 | ||
248 | #define ST0_KUO 0x00000020 | ||
249 | /* bits 6 & 7 are reserved on R[23]000 */ | ||
250 | #define ST0_ISC 0x00010000 | ||
251 | #define ST0_SWC 0x00020000 | ||
252 | #define ST0_CM 0x00080000 | ||
253 | |||
254 | /* | ||
255 | * Bits specific to the R4640/R4650 | ||
256 | */ | ||
257 | #define ST0_UM (_ULCAST_(1) << 4) | ||
258 | #define ST0_IL (_ULCAST_(1) << 23) | ||
259 | #define ST0_DL (_ULCAST_(1) << 24) | ||
260 | |||
261 | /* | ||
262 | * Bitfields in the TX39 family CP0 Configuration Register 3 | ||
263 | */ | ||
264 | #define TX39_CONF_ICS_SHIFT 19 | ||
265 | #define TX39_CONF_ICS_MASK 0x00380000 | ||
266 | #define TX39_CONF_ICS_1KB 0x00000000 | ||
267 | #define TX39_CONF_ICS_2KB 0x00080000 | ||
268 | #define TX39_CONF_ICS_4KB 0x00100000 | ||
269 | #define TX39_CONF_ICS_8KB 0x00180000 | ||
270 | #define TX39_CONF_ICS_16KB 0x00200000 | ||
271 | |||
272 | #define TX39_CONF_DCS_SHIFT 16 | ||
273 | #define TX39_CONF_DCS_MASK 0x00070000 | ||
274 | #define TX39_CONF_DCS_1KB 0x00000000 | ||
275 | #define TX39_CONF_DCS_2KB 0x00010000 | ||
276 | #define TX39_CONF_DCS_4KB 0x00020000 | ||
277 | #define TX39_CONF_DCS_8KB 0x00030000 | ||
278 | #define TX39_CONF_DCS_16KB 0x00040000 | ||
279 | |||
280 | #define TX39_CONF_CWFON 0x00004000 | ||
281 | #define TX39_CONF_WBON 0x00002000 | ||
282 | #define TX39_CONF_RF_SHIFT 10 | ||
283 | #define TX39_CONF_RF_MASK 0x00000c00 | ||
284 | #define TX39_CONF_DOZE 0x00000200 | ||
285 | #define TX39_CONF_HALT 0x00000100 | ||
286 | #define TX39_CONF_LOCK 0x00000080 | ||
287 | #define TX39_CONF_ICE 0x00000020 | ||
288 | #define TX39_CONF_DCE 0x00000010 | ||
289 | #define TX39_CONF_IRSIZE_SHIFT 2 | ||
290 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | ||
291 | #define TX39_CONF_DRSIZE_SHIFT 0 | ||
292 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | ||
293 | |||
294 | /* | ||
295 | * Status register bits available in all MIPS CPUs. | ||
296 | */ | ||
297 | #define ST0_IM 0x0000ff00 | ||
298 | #define STATUSB_IP0 8 | ||
299 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | ||
300 | #define STATUSB_IP1 9 | ||
301 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | ||
302 | #define STATUSB_IP2 10 | ||
303 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | ||
304 | #define STATUSB_IP3 11 | ||
305 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | ||
306 | #define STATUSB_IP4 12 | ||
307 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | ||
308 | #define STATUSB_IP5 13 | ||
309 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | ||
310 | #define STATUSB_IP6 14 | ||
311 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | ||
312 | #define STATUSB_IP7 15 | ||
313 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | ||
314 | #define STATUSB_IP8 0 | ||
315 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | ||
316 | #define STATUSB_IP9 1 | ||
317 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | ||
318 | #define STATUSB_IP10 2 | ||
319 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | ||
320 | #define STATUSB_IP11 3 | ||
321 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | ||
322 | #define STATUSB_IP12 4 | ||
323 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | ||
324 | #define STATUSB_IP13 5 | ||
325 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | ||
326 | #define STATUSB_IP14 6 | ||
327 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | ||
328 | #define STATUSB_IP15 7 | ||
329 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | ||
330 | #define ST0_CH 0x00040000 | ||
331 | #define ST0_SR 0x00100000 | ||
332 | #define ST0_TS 0x00200000 | ||
333 | #define ST0_BEV 0x00400000 | ||
334 | #define ST0_RE 0x02000000 | ||
335 | #define ST0_FR 0x04000000 | ||
336 | #define ST0_CU 0xf0000000 | ||
337 | #define ST0_CU0 0x10000000 | ||
338 | #define ST0_CU1 0x20000000 | ||
339 | #define ST0_CU2 0x40000000 | ||
340 | #define ST0_CU3 0x80000000 | ||
341 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | ||
342 | |||
343 | /* | ||
344 | * Bitfields and bit numbers in the coprocessor 0 cause register. | ||
345 | * | ||
346 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | ||
347 | */ | ||
348 | #define CAUSEB_EXCCODE 2 | ||
349 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | ||
350 | #define CAUSEB_IP 8 | ||
351 | #define CAUSEF_IP (_ULCAST_(255) << 8) | ||
352 | #define CAUSEB_IP0 8 | ||
353 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | ||
354 | #define CAUSEB_IP1 9 | ||
355 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | ||
356 | #define CAUSEB_IP2 10 | ||
357 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | ||
358 | #define CAUSEB_IP3 11 | ||
359 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | ||
360 | #define CAUSEB_IP4 12 | ||
361 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | ||
362 | #define CAUSEB_IP5 13 | ||
363 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | ||
364 | #define CAUSEB_IP6 14 | ||
365 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | ||
366 | #define CAUSEB_IP7 15 | ||
367 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | ||
368 | #define CAUSEB_IV 23 | ||
369 | #define CAUSEF_IV (_ULCAST_(1) << 23) | ||
370 | #define CAUSEB_CE 28 | ||
371 | #define CAUSEF_CE (_ULCAST_(3) << 28) | ||
372 | #define CAUSEB_BD 31 | ||
373 | #define CAUSEF_BD (_ULCAST_(1) << 31) | ||
374 | |||
375 | /* | ||
376 | * Bits in the coprocessor 0 config register. | ||
377 | */ | ||
378 | /* Generic bits. */ | ||
379 | #define CONF_CM_CACHABLE_NO_WA 0 | ||
380 | #define CONF_CM_CACHABLE_WA 1 | ||
381 | #define CONF_CM_UNCACHED 2 | ||
382 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | ||
383 | #define CONF_CM_CACHABLE_CE 4 | ||
384 | #define CONF_CM_CACHABLE_COW 5 | ||
385 | #define CONF_CM_CACHABLE_CUW 6 | ||
386 | #define CONF_CM_CACHABLE_ACCELERATED 7 | ||
387 | #define CONF_CM_CMASK 7 | ||
388 | #define CONF_BE (_ULCAST_(1) << 15) | ||
389 | |||
390 | /* Bits common to various processors. */ | ||
391 | #define CONF_CU (_ULCAST_(1) << 3) | ||
392 | #define CONF_DB (_ULCAST_(1) << 4) | ||
393 | #define CONF_IB (_ULCAST_(1) << 5) | ||
394 | #define CONF_DC (_ULCAST_(7) << 6) | ||
395 | #define CONF_IC (_ULCAST_(7) << 9) | ||
396 | #define CONF_EB (_ULCAST_(1) << 13) | ||
397 | #define CONF_EM (_ULCAST_(1) << 14) | ||
398 | #define CONF_SM (_ULCAST_(1) << 16) | ||
399 | #define CONF_SC (_ULCAST_(1) << 17) | ||
400 | #define CONF_EW (_ULCAST_(3) << 18) | ||
401 | #define CONF_EP (_ULCAST_(15)<< 24) | ||
402 | #define CONF_EC (_ULCAST_(7) << 28) | ||
403 | #define CONF_CM (_ULCAST_(1) << 31) | ||
404 | |||
405 | /* Bits specific to the R4xx0. */ | ||
406 | #define R4K_CONF_SW (_ULCAST_(1) << 20) | ||
407 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | ||
408 | #define R4K_CONF_SB (_ULCAST_(3) << 22) | ||
409 | |||
410 | /* Bits specific to the R5000. */ | ||
411 | #define R5K_CONF_SE (_ULCAST_(1) << 12) | ||
412 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | ||
413 | |||
414 | /* Bits specific to the R10000. */ | ||
415 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | ||
416 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | ||
417 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | ||
418 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | ||
419 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | ||
420 | #define R10K_CONF_SB (_ULCAST_(1) << 13) | ||
421 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | ||
422 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | ||
423 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | ||
424 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | ||
425 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | ||
426 | |||
427 | /* Bits specific to the VR41xx. */ | ||
428 | #define VR41_CONF_CS (_ULCAST_(1) << 12) | ||
429 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) | ||
430 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | ||
431 | |||
432 | /* Bits specific to the R30xx. */ | ||
433 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) | ||
434 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | ||
435 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | ||
436 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | ||
437 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | ||
438 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | ||
439 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | ||
440 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | ||
441 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | ||
442 | |||
443 | /* Bits specific to the TX49. */ | ||
444 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | ||
445 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | ||
446 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | ||
447 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | ||
448 | |||
449 | /* Bits specific to the MIPS32/64 PRA. */ | ||
450 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) | ||
451 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) | ||
452 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | ||
453 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | ||
454 | |||
455 | /* | ||
456 | * R10000 performance counter definitions. | ||
457 | * | ||
458 | * FIXME: The R10000 performance counter opens a nice way to implement CPU | ||
459 | * time accounting with a precission of one cycle. I don't have | ||
460 | * R10000 silicon but just a manual, so ... | ||
461 | */ | ||
462 | |||
463 | /* | ||
464 | * Events counted by counter #0 | ||
465 | */ | ||
466 | #define CE0_CYCLES 0 | ||
467 | #define CE0_INSN_ISSUED 1 | ||
468 | #define CE0_LPSC_ISSUED 2 | ||
469 | #define CE0_S_ISSUED 3 | ||
470 | #define CE0_SC_ISSUED 4 | ||
471 | #define CE0_SC_FAILED 5 | ||
472 | #define CE0_BRANCH_DECODED 6 | ||
473 | #define CE0_QW_WB_SECONDARY 7 | ||
474 | #define CE0_CORRECTED_ECC_ERRORS 8 | ||
475 | #define CE0_ICACHE_MISSES 9 | ||
476 | #define CE0_SCACHE_I_MISSES 10 | ||
477 | #define CE0_SCACHE_I_WAY_MISSPREDICTED 11 | ||
478 | #define CE0_EXT_INTERVENTIONS_REQ 12 | ||
479 | #define CE0_EXT_INVALIDATE_REQ 13 | ||
480 | #define CE0_VIRTUAL_COHERENCY_COND 14 | ||
481 | #define CE0_INSN_GRADUATED 15 | ||
482 | |||
483 | /* | ||
484 | * Events counted by counter #1 | ||
485 | */ | ||
486 | #define CE1_CYCLES 0 | ||
487 | #define CE1_INSN_GRADUATED 1 | ||
488 | #define CE1_LPSC_GRADUATED 2 | ||
489 | #define CE1_S_GRADUATED 3 | ||
490 | #define CE1_SC_GRADUATED 4 | ||
491 | #define CE1_FP_INSN_GRADUATED 5 | ||
492 | #define CE1_QW_WB_PRIMARY 6 | ||
493 | #define CE1_TLB_REFILL 7 | ||
494 | #define CE1_BRANCH_MISSPREDICTED 8 | ||
495 | #define CE1_DCACHE_MISS 9 | ||
496 | #define CE1_SCACHE_D_MISSES 10 | ||
497 | #define CE1_SCACHE_D_WAY_MISSPREDICTED 11 | ||
498 | #define CE1_EXT_INTERVENTION_HITS 12 | ||
499 | #define CE1_EXT_INVALIDATE_REQ 13 | ||
500 | #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 | ||
501 | #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 | ||
502 | |||
503 | /* | ||
504 | * These flags define in which priviledge mode the counters count events | ||
505 | */ | ||
506 | #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ | ||
507 | #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ | ||
508 | #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ | ||
509 | #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ | ||
510 | |||
511 | #ifndef __ASSEMBLY__ | ||
512 | |||
513 | #define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE) | ||
514 | #define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2)) | ||
515 | |||
516 | /* | ||
517 | * Functions to access the r10k performance counter and control registers | ||
518 | */ | ||
519 | #define read_r10k_perf_cntr(counter) \ | ||
520 | ({ unsigned int __res; \ | ||
521 | __asm__ __volatile__( \ | ||
522 | "mfpc\t%0, "STR(counter) \ | ||
523 | : "=r" (__res)); \ | ||
524 | __res;}) | ||
525 | |||
526 | #define write_r10k_perf_cntr(counter,val) \ | ||
527 | __asm__ __volatile__( \ | ||
528 | "mtpc\t%0, "STR(counter) \ | ||
529 | : : "r" (val)); | ||
530 | |||
531 | #define read_r10k_perf_cntl(counter) \ | ||
532 | ({ unsigned int __res; \ | ||
533 | __asm__ __volatile__( \ | ||
534 | "mfps\t%0, "STR(counter) \ | ||
535 | : "=r" (__res)); \ | ||
536 | __res;}) | ||
537 | |||
538 | #define write_r10k_perf_cntl(counter,val) \ | ||
539 | __asm__ __volatile__( \ | ||
540 | "mtps\t%0, "STR(counter) \ | ||
541 | : : "r" (val)); | ||
542 | |||
543 | /* | ||
544 | * Macros to access the system control coprocessor | ||
545 | */ | ||
546 | |||
547 | #define __read_32bit_c0_register(source, sel) \ | ||
548 | ({ int __res; \ | ||
549 | if (sel == 0) \ | ||
550 | __asm__ __volatile__( \ | ||
551 | "mfc0\t%0, " #source "\n\t" \ | ||
552 | : "=r" (__res)); \ | ||
553 | else \ | ||
554 | __asm__ __volatile__( \ | ||
555 | ".set\tmips32\n\t" \ | ||
556 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | ||
557 | ".set\tmips0\n\t" \ | ||
558 | : "=r" (__res)); \ | ||
559 | __res; \ | ||
560 | }) | ||
561 | |||
562 | #define __read_64bit_c0_register(source, sel) \ | ||
563 | ({ unsigned long __res; \ | ||
564 | if (sel == 0) \ | ||
565 | __asm__ __volatile__( \ | ||
566 | ".set\tmips3\n\t" \ | ||
567 | "dmfc0\t%0, " #source "\n\t" \ | ||
568 | ".set\tmips0" \ | ||
569 | : "=r" (__res)); \ | ||
570 | else \ | ||
571 | __asm__ __volatile__( \ | ||
572 | ".set\tmips64\n\t" \ | ||
573 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | ||
574 | ".set\tmips0" \ | ||
575 | : "=r" (__res)); \ | ||
576 | __res; \ | ||
577 | }) | ||
578 | |||
579 | #define __write_32bit_c0_register(register, sel, value) \ | ||
580 | do { \ | ||
581 | if (sel == 0) \ | ||
582 | __asm__ __volatile__( \ | ||
583 | "mtc0\t%z0, " #register "\n\t" \ | ||
584 | : : "Jr" (value)); \ | ||
585 | else \ | ||
586 | __asm__ __volatile__( \ | ||
587 | ".set\tmips32\n\t" \ | ||
588 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | ||
589 | ".set\tmips0" \ | ||
590 | : : "Jr" (value)); \ | ||
591 | } while (0) | ||
592 | |||
593 | #define __write_64bit_c0_register(register, sel, value) \ | ||
594 | do { \ | ||
595 | if (sel == 0) \ | ||
596 | __asm__ __volatile__( \ | ||
597 | ".set\tmips3\n\t" \ | ||
598 | "dmtc0\t%z0, " #register "\n\t" \ | ||
599 | ".set\tmips0" \ | ||
600 | : : "Jr" (value)); \ | ||
601 | else \ | ||
602 | __asm__ __volatile__( \ | ||
603 | ".set\tmips64\n\t" \ | ||
604 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | ||
605 | ".set\tmips0" \ | ||
606 | : : "Jr" (value)); \ | ||
607 | } while (0) | ||
608 | |||
609 | #define __read_ulong_c0_register(reg, sel) \ | ||
610 | ((sizeof(unsigned long) == 4) ? \ | ||
611 | __read_32bit_c0_register(reg, sel) : \ | ||
612 | __read_64bit_c0_register(reg, sel)) | ||
613 | |||
614 | #define __write_ulong_c0_register(reg, sel, val) \ | ||
615 | do { \ | ||
616 | if (sizeof(unsigned long) == 4) \ | ||
617 | __write_32bit_c0_register(reg, sel, val); \ | ||
618 | else \ | ||
619 | __write_64bit_c0_register(reg, sel, val); \ | ||
620 | } while (0) | ||
621 | |||
622 | /* | ||
623 | * These versions are only needed for systems with more than 38 bits of | ||
624 | * physical address space running the 32-bit kernel. That's none atm :-) | ||
625 | */ | ||
626 | #define __read_64bit_c0_split(source, sel) \ | ||
627 | ({ \ | ||
628 | unsigned long long val; \ | ||
629 | unsigned long flags; \ | ||
630 | \ | ||
631 | local_irq_save(flags); \ | ||
632 | if (sel == 0) \ | ||
633 | __asm__ __volatile__( \ | ||
634 | ".set\tmips64\n\t" \ | ||
635 | "dmfc0\t%M0, " #source "\n\t" \ | ||
636 | "dsll\t%L0, %M0, 32\n\t" \ | ||
637 | "dsrl\t%M0, %M0, 32\n\t" \ | ||
638 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
639 | ".set\tmips0" \ | ||
640 | : "=r" (val)); \ | ||
641 | else \ | ||
642 | __asm__ __volatile__( \ | ||
643 | ".set\tmips64\n\t" \ | ||
644 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ | ||
645 | "dsll\t%L0, %M0, 32\n\t" \ | ||
646 | "dsrl\t%M0, %M0, 32\n\t" \ | ||
647 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
648 | ".set\tmips0" \ | ||
649 | : "=r" (val)); \ | ||
650 | local_irq_restore(flags); \ | ||
651 | \ | ||
652 | val; \ | ||
653 | }) | ||
654 | |||
655 | #define __write_64bit_c0_split(source, sel, val) \ | ||
656 | do { \ | ||
657 | unsigned long flags; \ | ||
658 | \ | ||
659 | local_irq_save(flags); \ | ||
660 | if (sel == 0) \ | ||
661 | __asm__ __volatile__( \ | ||
662 | ".set\tmips64\n\t" \ | ||
663 | "dsll\t%L0, %L0, 32\n\t" \ | ||
664 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
665 | "dsll\t%M0, %M0, 32\n\t" \ | ||
666 | "or\t%L0, %L0, %M0\n\t" \ | ||
667 | "dmtc0\t%L0, " #source "\n\t" \ | ||
668 | ".set\tmips0" \ | ||
669 | : : "r" (val)); \ | ||
670 | else \ | ||
671 | __asm__ __volatile__( \ | ||
672 | ".set\tmips64\n\t" \ | ||
673 | "dsll\t%L0, %L0, 32\n\t" \ | ||
674 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
675 | "dsll\t%M0, %M0, 32\n\t" \ | ||
676 | "or\t%L0, %L0, %M0\n\t" \ | ||
677 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | ||
678 | ".set\tmips0" \ | ||
679 | : : "r" (val)); \ | ||
680 | local_irq_restore(flags); \ | ||
681 | } while (0) | ||
682 | |||
683 | #define read_c0_index() __read_32bit_c0_register($0, 0) | ||
684 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | ||
685 | |||
686 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) | ||
687 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | ||
688 | |||
689 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) | ||
690 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | ||
691 | |||
692 | #define read_c0_conf() __read_32bit_c0_register($3, 0) | ||
693 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | ||
694 | |||
695 | #define read_c0_context() __read_ulong_c0_register($4, 0) | ||
696 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | ||
697 | |||
698 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) | ||
699 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | ||
700 | |||
701 | #define read_c0_wired() __read_32bit_c0_register($6, 0) | ||
702 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | ||
703 | |||
704 | #define read_c0_info() __read_32bit_c0_register($7, 0) | ||
705 | |||
706 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ | ||
707 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) | ||
708 | |||
709 | #define read_c0_count() __read_32bit_c0_register($9, 0) | ||
710 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | ||
711 | |||
712 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) | ||
713 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | ||
714 | |||
715 | #define read_c0_compare() __read_32bit_c0_register($11, 0) | ||
716 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | ||
717 | |||
718 | #define read_c0_status() __read_32bit_c0_register($12, 0) | ||
719 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) | ||
720 | |||
721 | #define read_c0_cause() __read_32bit_c0_register($13, 0) | ||
722 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | ||
723 | |||
724 | #define read_c0_prid() __read_32bit_c0_register($15, 0) | ||
725 | |||
726 | #define read_c0_config() __read_32bit_c0_register($16, 0) | ||
727 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | ||
728 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | ||
729 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | ||
730 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) | ||
731 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | ||
732 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | ||
733 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | ||
734 | |||
735 | /* | ||
736 | * The WatchLo register. There may be upto 8 of them. | ||
737 | */ | ||
738 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | ||
739 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | ||
740 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | ||
741 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | ||
742 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | ||
743 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | ||
744 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | ||
745 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | ||
746 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | ||
747 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | ||
748 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | ||
749 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | ||
750 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | ||
751 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | ||
752 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | ||
753 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | ||
754 | |||
755 | /* | ||
756 | * The WatchHi register. There may be upto 8 of them. | ||
757 | */ | ||
758 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | ||
759 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | ||
760 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | ||
761 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | ||
762 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | ||
763 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | ||
764 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | ||
765 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | ||
766 | |||
767 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | ||
768 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | ||
769 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | ||
770 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | ||
771 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | ||
772 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | ||
773 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | ||
774 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | ||
775 | |||
776 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | ||
777 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | ||
778 | |||
779 | #define read_c0_intcontrol() __read_32bit_c0_register($20, 1) | ||
780 | #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) | ||
781 | |||
782 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | ||
783 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) | ||
784 | |||
785 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | ||
786 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | ||
787 | |||
788 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | ||
789 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | ||
790 | |||
791 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) | ||
792 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | ||
793 | |||
794 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | ||
795 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) | ||
796 | |||
797 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | ||
798 | |||
799 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | ||
800 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) | ||
801 | |||
802 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | ||
803 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | ||
804 | |||
805 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) | ||
806 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | ||
807 | |||
808 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | ||
809 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | ||
810 | |||
811 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | ||
812 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | ||
813 | |||
814 | #if 1 | ||
815 | /* | ||
816 | * Macros to access the system control coprocessor | ||
817 | */ | ||
818 | #define read_32bit_cp0_register(source) \ | ||
819 | ({ int __res; \ | ||
820 | __asm__ __volatile__( \ | ||
821 | ".set\tpush\n\t" \ | ||
822 | ".set\treorder\n\t" \ | ||
823 | "mfc0\t%0,"STR(source)"\n\t" \ | ||
824 | ".set\tpop" \ | ||
825 | : "=r" (__res)); \ | ||
826 | __res;}) | ||
827 | |||
828 | #define read_32bit_cp0_set1_register(source) \ | ||
829 | ({ int __res; \ | ||
830 | __asm__ __volatile__( \ | ||
831 | ".set\tpush\n\t" \ | ||
832 | ".set\treorder\n\t" \ | ||
833 | "cfc0\t%0,"STR(source)"\n\t" \ | ||
834 | ".set\tpop" \ | ||
835 | : "=r" (__res)); \ | ||
836 | __res;}) | ||
837 | |||
838 | /* | ||
839 | * For now use this only with interrupts disabled! | ||
840 | */ | ||
841 | #define read_64bit_cp0_register(source) \ | ||
842 | ({ int __res; \ | ||
843 | __asm__ __volatile__( \ | ||
844 | ".set\tmips3\n\t" \ | ||
845 | "dmfc0\t%0,"STR(source)"\n\t" \ | ||
846 | ".set\tmips0" \ | ||
847 | : "=r" (__res)); \ | ||
848 | __res;}) | ||
849 | |||
850 | #define write_32bit_cp0_register(register,value) \ | ||
851 | __asm__ __volatile__( \ | ||
852 | "mtc0\t%0,"STR(register)"\n\t" \ | ||
853 | "nop" \ | ||
854 | : : "r" (value)); | ||
855 | |||
856 | #define write_32bit_cp0_set1_register(register,value) \ | ||
857 | __asm__ __volatile__( \ | ||
858 | "ctc0\t%0,"STR(register)"\n\t" \ | ||
859 | "nop" \ | ||
860 | : : "r" (value)); | ||
861 | |||
862 | #define write_64bit_cp0_register(register,value) \ | ||
863 | __asm__ __volatile__( \ | ||
864 | ".set\tmips3\n\t" \ | ||
865 | "dmtc0\t%0,"STR(register)"\n\t" \ | ||
866 | ".set\tmips0" \ | ||
867 | : : "r" (value)) | ||
868 | |||
869 | /* | ||
870 | * This should be changed when we get a compiler that support the MIPS32 ISA. | ||
871 | */ | ||
872 | #define read_mips32_cp0_config1() \ | ||
873 | ({ int __res; \ | ||
874 | __asm__ __volatile__( \ | ||
875 | ".set\tnoreorder\n\t" \ | ||
876 | ".set\tnoat\n\t" \ | ||
877 | "#.set\tmips64\n\t" \ | ||
878 | "#mfc0\t$1, $16, 1\n\t" \ | ||
879 | "#.set\tmips0\n\t" \ | ||
880 | ".word\t0x40018001\n\t" \ | ||
881 | "move\t%0,$1\n\t" \ | ||
882 | ".set\tat\n\t" \ | ||
883 | ".set\treorder" \ | ||
884 | :"=r" (__res)); \ | ||
885 | __res;}) | ||
886 | |||
887 | #endif | ||
888 | /* | ||
889 | * Macros to access the floating point coprocessor control registers | ||
890 | */ | ||
891 | #define read_32bit_cp1_register(source) \ | ||
892 | ({ int __res; \ | ||
893 | __asm__ __volatile__( \ | ||
894 | ".set\tpush\n\t" \ | ||
895 | ".set\treorder\n\t" \ | ||
896 | "cfc1\t%0,"STR(source)"\n\t" \ | ||
897 | ".set\tpop" \ | ||
898 | : "=r" (__res)); \ | ||
899 | __res;}) | ||
900 | |||
901 | /* TLB operations. */ | ||
902 | static inline void tlb_probe(void) | ||
903 | { | ||
904 | __asm__ __volatile__( | ||
905 | ".set noreorder\n\t" | ||
906 | "tlbp\n\t" | ||
907 | ".set reorder"); | ||
908 | } | ||
909 | |||
910 | static inline void tlb_read(void) | ||
911 | { | ||
912 | __asm__ __volatile__( | ||
913 | ".set noreorder\n\t" | ||
914 | "tlbr\n\t" | ||
915 | ".set reorder"); | ||
916 | } | ||
917 | |||
918 | static inline void tlb_write_indexed(void) | ||
919 | { | ||
920 | __asm__ __volatile__( | ||
921 | ".set noreorder\n\t" | ||
922 | "tlbwi\n\t" | ||
923 | ".set reorder"); | ||
924 | } | ||
925 | |||
926 | static inline void tlb_write_random(void) | ||
927 | { | ||
928 | __asm__ __volatile__( | ||
929 | ".set noreorder\n\t" | ||
930 | "tlbwr\n\t" | ||
931 | ".set reorder"); | ||
932 | } | ||
933 | |||
934 | /* | ||
935 | * Manipulate bits in a c0 register. | ||
936 | */ | ||
937 | #define __BUILD_SET_C0(name,register) \ | ||
938 | static inline unsigned int \ | ||
939 | set_c0_##name(unsigned int set) \ | ||
940 | { \ | ||
941 | unsigned int res; \ | ||
942 | \ | ||
943 | res = read_c0_##name(); \ | ||
944 | res |= set; \ | ||
945 | write_c0_##name(res); \ | ||
946 | \ | ||
947 | return res; \ | ||
948 | } \ | ||
949 | \ | ||
950 | static inline unsigned int \ | ||
951 | clear_c0_##name(unsigned int clear) \ | ||
952 | { \ | ||
953 | unsigned int res; \ | ||
954 | \ | ||
955 | res = read_c0_##name(); \ | ||
956 | res &= ~clear; \ | ||
957 | write_c0_##name(res); \ | ||
958 | \ | ||
959 | return res; \ | ||
960 | } \ | ||
961 | \ | ||
962 | static inline unsigned int \ | ||
963 | change_c0_##name(unsigned int change, unsigned int new) \ | ||
964 | { \ | ||
965 | unsigned int res; \ | ||
966 | \ | ||
967 | res = read_c0_##name(); \ | ||
968 | res &= ~change; \ | ||
969 | res |= (new & change); \ | ||
970 | write_c0_##name(res); \ | ||
971 | \ | ||
972 | return res; \ | ||
973 | } | ||
974 | |||
975 | __BUILD_SET_C0(status,CP0_STATUS) | ||
976 | __BUILD_SET_C0(cause,CP0_CAUSE) | ||
977 | __BUILD_SET_C0(config,CP0_CONFIG) | ||
978 | |||
979 | #define set_cp0_status(x) set_c0_status(x) | ||
980 | #define set_cp0_cause(x) set_c0_cause(x) | ||
981 | #define set_cp0_config(x) set_c0_config(x) | ||
982 | |||
983 | #endif /* !__ASSEMBLY__ */ | ||
984 | |||
985 | #endif /* _ASM_MIPSREGS_H */ | ||
diff --git a/firmware/export/thread.h b/firmware/export/thread.h index 1d5c25c649..ecba179693 100644 --- a/firmware/export/thread.h +++ b/firmware/export/thread.h | |||
@@ -109,6 +109,14 @@ struct regs | |||
109 | uint32_t lr; /* 36 - r14 (lr) */ | 109 | uint32_t lr; /* 36 - r14 (lr) */ |
110 | uint32_t start; /* 40 - Thread start address, or NULL when started */ | 110 | uint32_t start; /* 40 - Thread start address, or NULL when started */ |
111 | }; | 111 | }; |
112 | #elif defined(CPU_MIPS) | ||
113 | struct regs | ||
114 | { | ||
115 | uint32_t r[27]; /* 0-104 - Registers $1, v0-v1, a0-a3, t0-t9, s0-s7, gp, fp */ | ||
116 | uint32_t sp; /* 108 - Stack pointer */ | ||
117 | uint32_t ra; /* 112 - Return address */ | ||
118 | uint32_t start; /* 116 - Thread start address, or NULL when started */ | ||
119 | }; | ||
112 | #endif /* CONFIG_CPU */ | 120 | #endif /* CONFIG_CPU */ |
113 | #else | 121 | #else |
114 | struct regs | 122 | struct regs |
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c new file mode 100755 index 0000000000..b907bb86df --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/ata-jz4740.c | |||
@@ -0,0 +1,40 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "ata.h" | ||
25 | |||
26 | int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf) | ||
27 | { | ||
28 | (void)start; | ||
29 | (void)count; | ||
30 | (void)buf; | ||
31 | return 0; | ||
32 | } | ||
33 | |||
34 | int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf) | ||
35 | { | ||
36 | (void)start; | ||
37 | (void)count; | ||
38 | (void)buf; | ||
39 | return 0; | ||
40 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/boot.lds b/firmware/target/mips/ingenic_jz47xx/boot.lds new file mode 100755 index 0000000000..9bc635afad --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/boot.lds | |||
@@ -0,0 +1,107 @@ | |||
1 | #include "config.h" | ||
2 | #undef mips | ||
3 | |||
4 | OUTPUT_FORMAT("elf32-tradlittlemips") | ||
5 | OUTPUT_ARCH(MIPS) | ||
6 | ENTRY(_start) | ||
7 | STARTUP(target/mips/ingenic_jz47xx/crt0.o) | ||
8 | |||
9 | #define DRAMSIZE (MEMORYSIZE * 0x100000) | ||
10 | |||
11 | #define DRAMORIG 0x80E00000 /* HACK */ | ||
12 | #define IRAMORIG 0x80000000 | ||
13 | #define IRAMSIZE 16K | ||
14 | |||
15 | MEMORY | ||
16 | { | ||
17 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | ||
18 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE | ||
19 | } | ||
20 | |||
21 | SECTIONS | ||
22 | { | ||
23 | . = DRAMORIG; | ||
24 | |||
25 | .text : { | ||
26 | loadaddress = .; | ||
27 | _loadaddress = .; | ||
28 | *(.init.text); | ||
29 | *(.text*); | ||
30 | *(.glue_7); | ||
31 | *(.glue_7t); | ||
32 | . = ALIGN(0x4); | ||
33 | } > DRAM | ||
34 | |||
35 | . = ALIGN(4); | ||
36 | |||
37 | .rodata : | ||
38 | { | ||
39 | *(.rodata); /* problems without this, dunno why */ | ||
40 | *(.rodata*); | ||
41 | *(.rodata.str1.1); | ||
42 | *(.rodata.str1.4); | ||
43 | . = ALIGN(0x4); | ||
44 | |||
45 | /* Pseudo-allocate the copies of the data sections */ | ||
46 | _datacopy = .; | ||
47 | } > DRAM | ||
48 | |||
49 | . = ALIGN(4); | ||
50 | |||
51 | .data : { | ||
52 | *(.icode); | ||
53 | *(.irodata); | ||
54 | *(.idata); | ||
55 | *(.data*); | ||
56 | *(.scommon*); | ||
57 | *(.sdata*); | ||
58 | . = ALIGN(0x4); | ||
59 | _dataend = . ; | ||
60 | } > DRAM | ||
61 | |||
62 | . = ALIGN(4); | ||
63 | |||
64 | _gp = ALIGN(16); | ||
65 | .got : { | ||
66 | *(.got*) | ||
67 | }> DRAM | ||
68 | |||
69 | . = ALIGN(4); | ||
70 | |||
71 | .stack : | ||
72 | { | ||
73 | *(.stack) | ||
74 | _stackbegin = .; | ||
75 | stackbegin = .; | ||
76 | . += 0x2000; | ||
77 | _stackend = .; | ||
78 | stackend = .; | ||
79 | } > DRAM | ||
80 | |||
81 | . = ALIGN(4); | ||
82 | |||
83 | .bss : | ||
84 | { | ||
85 | _edata = .; | ||
86 | *(.sbss*); | ||
87 | *(.bss*); | ||
88 | *(.ibss); | ||
89 | *(COMMON) | ||
90 | _end = .; | ||
91 | } > DRAM | ||
92 | |||
93 | . = ALIGN(4); | ||
94 | |||
95 | .vectors IRAMORIG : | ||
96 | { | ||
97 | _vectorsstart = .; | ||
98 | KEEP(*(.resetvectors)); | ||
99 | *(.resetvectors); | ||
100 | KEEP(*(.vectors)); | ||
101 | *(.vectors); | ||
102 | _vectorsend = .; | ||
103 | } AT > DRAM | ||
104 | _vectorscopy = LOADADDR(.vectors); | ||
105 | |||
106 | . = ALIGN(4); | ||
107 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S new file mode 100755 index 0000000000..6ac9ad71ab --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/crt0.S | |||
@@ -0,0 +1,246 @@ | |||
1 | /* | ||
2 | * init.S | ||
3 | * | ||
4 | * Initialization code for JzRISC. | ||
5 | * | ||
6 | * Author: Seeger Chin | ||
7 | * e-mail: seeger.chin@gmail.com | ||
8 | * | ||
9 | * Copyright (C) 2006 Ingenic Semiconductor Inc. | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | */ | ||
16 | |||
17 | #include "config.h" | ||
18 | #include "mips.h" | ||
19 | |||
20 | .text | ||
21 | |||
22 | .set mips3 | ||
23 | |||
24 | .extern main | ||
25 | |||
26 | .global _start | ||
27 | #ifdef BOOTLOADER | ||
28 | .section .init.text,"ax",%progbits | ||
29 | #else | ||
30 | .section .resetvectors,"ax",%progbits | ||
31 | #endif | ||
32 | .set noreorder | ||
33 | .set noat | ||
34 | |||
35 | #ifdef BOOTLOADER | ||
36 | .word 0 /* HACK */ | ||
37 | .word 0 /* HACK */ | ||
38 | #endif | ||
39 | _start: | ||
40 | la ra, _start | ||
41 | //---------------------------------------------------- | ||
42 | // init cp0 registers. | ||
43 | //---------------------------------------------------- | ||
44 | mtc0 zero, C0_WATCHLO | ||
45 | mtc0 zero, C0_WATCHHI | ||
46 | |||
47 | li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \ | ||
48 | | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \ | ||
49 | | M_StatusIM2 | M_StatusERL) | ||
50 | // BEV = Enable Boot Exception Vectors | ||
51 | // IMx = Interrupt mask | ||
52 | // ERL = Denotes error level | ||
53 | mtc0 t0, C0_STATUS | ||
54 | |||
55 | li t1, M_CauseIV | ||
56 | mtc0 t1, C0_CAUSE | ||
57 | |||
58 | //---------------------------------------------------- | ||
59 | // init caches, assumes a 4way*128set*32byte i/d cache | ||
60 | //---------------------------------------------------- | ||
61 | li t0, 3 // enable cache for kseg0 accesses | ||
62 | mtc0 t0, C0_CONFIG // CONFIG reg | ||
63 | la t0, 0x80000000 // an idx op should use a unmappable address | ||
64 | ori t1, t0, 0x4000 // 16kB cache | ||
65 | mtc0 zero, C0_TAGLO // TAGLO reg | ||
66 | mtc0 zero, C0_TAGHI // TAGHI reg | ||
67 | |||
68 | _init_cache_loop: | ||
69 | cache 0x8, 0(t0) // index store icache tag | ||
70 | cache 0x9, 0(t0) // index store dcache tag | ||
71 | bne t0, t1, _init_cache_loop | ||
72 | addiu t0, t0, 0x20 // 32 bytes per cache line | ||
73 | nop | ||
74 | |||
75 | //---------------------------------------------------- | ||
76 | // Invalidate BTB | ||
77 | //---------------------------------------------------- | ||
78 | mfc0 t0, C0_CONFIG | ||
79 | nop | ||
80 | ori t0, 2 | ||
81 | mtc0 t0, C0_CONFIG | ||
82 | nop | ||
83 | |||
84 | //---------------------------------------------------- | ||
85 | // setup stack, jump to C code | ||
86 | //---------------------------------------------------- | ||
87 | la sp, stackend | ||
88 | la t0, stackbegin | ||
89 | li t1, 0xDEADBEEF | ||
90 | |||
91 | _init_stack_loop: | ||
92 | sw t1, 0(t0) | ||
93 | bne t0, sp, _init_stack_loop | ||
94 | addiu t0, t0, 4 | ||
95 | |||
96 | la t0, main | ||
97 | jr t0 | ||
98 | nop | ||
99 | |||
100 | |||
101 | #ifndef BOOTLOADER | ||
102 | .section .vectors,"ax",%progbits | ||
103 | #endif | ||
104 | .extern exception_handler | ||
105 | .global except_common_entry | ||
106 | .type except_common_entry,@function | ||
107 | except_common_entry: | ||
108 | la k0, exception_handler | ||
109 | jr k0 | ||
110 | nop | ||
111 | nop | ||
112 | nop | ||
113 | |||
114 | .extern _int | ||
115 | .extern _exception | ||
116 | .global exception_handler | ||
117 | .type exception_handler,@function | ||
118 | .set noreorder | ||
119 | exception_handler: | ||
120 | |||
121 | |||
122 | addiu sp, -0x80 # Add Immediate Unsigned | ||
123 | sw ra, 0(sp) # Store Word | ||
124 | sw fp, 4(sp) # Store Word | ||
125 | sw gp, 8(sp) # Store Word | ||
126 | sw t9, 0xC(sp) # Store Word | ||
127 | sw t8, 0x10(sp) # Store Word | ||
128 | sw s7, 0x14(sp) # Store Word | ||
129 | sw s6, 0x18(sp) # Store Word | ||
130 | sw s5, 0x1C(sp) # Store Word | ||
131 | sw s4, 0x20(sp) # Store Word | ||
132 | sw s3, 0x24(sp) # Store Word | ||
133 | sw s2, 0x28(sp) # Store Word | ||
134 | sw s1, 0x2C(sp) # Store Word | ||
135 | sw s0, 0x30(sp) # Store Word | ||
136 | sw t7, 0x34(sp) # Store Word | ||
137 | sw t6, 0x38(sp) # Store Word | ||
138 | sw t5, 0x3C(sp) # Store Word | ||
139 | sw t4, 0x40(sp) # Store Word | ||
140 | sw t3, 0x44(sp) # Store Word | ||
141 | sw t2, 0x48(sp) # Store Word | ||
142 | sw t1, 0x4C(sp) # Store Word | ||
143 | sw t0, 0x50(sp) # Store Word | ||
144 | sw a3, 0x54(sp) # Store Word | ||
145 | sw a2, 0x58(sp) # Store Word | ||
146 | sw a1, 0x5C(sp) # Store Word | ||
147 | sw a0, 0x60(sp) # Store Word | ||
148 | sw v1, 0x64(sp) # Store Word | ||
149 | sw v0, 0x68(sp) # Store Word | ||
150 | sw $1, 0x6C(sp) # Store Word | ||
151 | mflo t0 # Move F LO | ||
152 | nop | ||
153 | sw t0, 0x70(sp) # Store Word | ||
154 | mfhi t0 # Move F HI | ||
155 | nop | ||
156 | sw t0, 0x74(sp) # Store Word | ||
157 | mfc0 t0, C0_STATUS # Status register | ||
158 | sll zero, 1 # Shift Left Logical | ||
159 | sll zero, 1 # Shift Left Logical | ||
160 | sll zero, 1 # Shift Left Logical | ||
161 | sll zero, 1 # Shift Left Logical | ||
162 | sw t0, 0x78(sp) # Store Word | ||
163 | mfc0 t0, C0_EPC # Exception Program Counter | ||
164 | sll zero, 1 # Shift Left Logical | ||
165 | sll zero, 1 # Shift Left Logical | ||
166 | sll zero, 1 # Shift Left Logical | ||
167 | sll zero, 1 # Shift Left Logical | ||
168 | sw t0, 0x7C(sp) # Store Word | ||
169 | li k1, 0x7C # Load Immediate | ||
170 | mfc0 k0, C0_CAUSE # C0_CAUSE of last exception | ||
171 | and k0, k1 # AND | ||
172 | beq zero, k0, _int # Branch on Equal | ||
173 | nop | ||
174 | la k0, _exception | ||
175 | jr k0 | ||
176 | nop | ||
177 | |||
178 | .global _int | ||
179 | .type _int,@function | ||
180 | _int: | ||
181 | jal intr_handler # Jump And Link | ||
182 | nop | ||
183 | lw ra, 0(sp) # Load Word | ||
184 | lw fp, 4(sp) # Load Word | ||
185 | sw gp, 8(sp) # Store Word | ||
186 | lw t9, 0xC(sp) # Load Word | ||
187 | lw t8, 0x10(sp) # Load Word | ||
188 | lw s7, 0x14(sp) # Load Word | ||
189 | lw s6, 0x18(sp) # Load Word | ||
190 | lw s5, 0x1C(sp) # Load Word | ||
191 | lw s4, 0x20(sp) # Load Word | ||
192 | lw s3, 0x24(sp) # Load Word | ||
193 | lw s2, 0x28(sp) # Load Word | ||
194 | lw s1, 0x2C(sp) # Load Word | ||
195 | lw s0, 0x30(sp) # Load Word | ||
196 | lw t7, 0x34(sp) # Load Word | ||
197 | lw t6, 0x38(sp) # Load Word | ||
198 | lw t5, 0x3C(sp) # Load Word | ||
199 | lw t4, 0x40(sp) # Load Word | ||
200 | lw t3, 0x44(sp) # Load Word | ||
201 | lw t2, 0x48(sp) # Load Word | ||
202 | lw t1, 0x4C(sp) # Load Word | ||
203 | lw t0, 0x50(sp) # Load Word | ||
204 | lw a3, 0x54(sp) # Load Word | ||
205 | lw a2, 0x58(sp) # Load Word | ||
206 | lw a1, 0x5C(sp) # Load Word | ||
207 | lw a0, 0x60(sp) # Load Word | ||
208 | lw v1, 0x64(sp) # Load Word | ||
209 | lw v0, 0x68(sp) # Load Word | ||
210 | lw v1, 0x6C(sp) # Load Word | ||
211 | lw k0, 0x70(sp) # Load Word | ||
212 | mtlo k0 # Move To LO | ||
213 | nop | ||
214 | lw k0, 0x74(sp) # Load Word | ||
215 | mthi k0 # Move To HI | ||
216 | nop | ||
217 | lw k0, 0x78(sp) # Load Word | ||
218 | nop | ||
219 | mtc0 k0, C0_STATUS # Status register | ||
220 | sll zero, 1 # Shift Left Logical | ||
221 | sll zero, 1 # Shift Left Logical | ||
222 | sll zero, 1 # Shift Left Logical | ||
223 | sll zero, 1 # Shift Left Logical | ||
224 | lw k0, 0x7C(sp) # Load Word | ||
225 | nop | ||
226 | mtc0 k0, C0_EPC # Exception Program Counter | ||
227 | sll zero, 1 # Shift Left Logical | ||
228 | sll zero, 1 # Shift Left Logical | ||
229 | sll zero, 1 # Shift Left Logical | ||
230 | sll zero, 1 # Shift Left Logical | ||
231 | addiu sp, 0x80 # Add Immediate Unsigned | ||
232 | eret # Exception Return | ||
233 | nop | ||
234 | |||
235 | .extern _except_handler | ||
236 | .global _exception | ||
237 | .type _exception,@function | ||
238 | _exception: | ||
239 | move a0, sp | ||
240 | mfc0 a1, C0_CAUSE # C0_CAUSE of last exception | ||
241 | mfc0 a2, C0_EPC # Exception Program Counter | ||
242 | la k0, except_handler # Load Address | ||
243 | jr k0 # Jump Register | ||
244 | nop | ||
245 | |||
246 | .set reorder | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c new file mode 100755 index 0000000000..429178aeee --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | |||
@@ -0,0 +1,94 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "lcd.h" | ||
25 | #include "lcd-target.h" | ||
26 | |||
27 | static volatile bool _lcd_on = false; | ||
28 | static volatile bool lcd_poweroff = false; | ||
29 | |||
30 | /* LCD init */ | ||
31 | void lcd_init_device(void) | ||
32 | { | ||
33 | lcd_init_controller(); | ||
34 | _lcd_on = true; | ||
35 | } | ||
36 | |||
37 | void lcd_enable(bool state) | ||
38 | { | ||
39 | if(state) | ||
40 | lcd_on(); | ||
41 | else | ||
42 | lcd_off(); | ||
43 | |||
44 | _lcd_on = state; | ||
45 | } | ||
46 | |||
47 | bool lcd_enabled(void) | ||
48 | { | ||
49 | return _lcd_on; | ||
50 | } | ||
51 | |||
52 | #define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)]) | ||
53 | #define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000) | ||
54 | |||
55 | /* Update a fraction of the display. */ | ||
56 | void lcd_update_rect(int x, int y, int width, int height) | ||
57 | { | ||
58 | /* HACKY... */ | ||
59 | x=0; y=0; width=400; height=240; | ||
60 | lcd_set_target(x, y, width-1, height-1); | ||
61 | |||
62 | REG_DMAC_DCCSR(0) = 0; | ||
63 | REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ | ||
64 | REG_DMAC_DSAR(0) = LCDADDR(x,y) & 0x1FFFFFFF; | ||
65 | #if 0 | ||
66 | REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO); | ||
67 | #else | ||
68 | REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */ | ||
69 | #endif | ||
70 | REG_DMAC_DTCR(0) = (width*height); | ||
71 | |||
72 | REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */ | ||
73 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ | ||
74 | REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ | ||
75 | |||
76 | jz_flush_icache(); | ||
77 | |||
78 | REG_DMAC_DMACR = DMAC_DMACR_DMAE; | ||
79 | |||
80 | while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) ) | ||
81 | asm("nop"); | ||
82 | |||
83 | //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT; | ||
84 | } | ||
85 | |||
86 | /* Update the display. | ||
87 | This must be called after all other LCD functions that change the display. */ | ||
88 | void lcd_update(void) | ||
89 | { | ||
90 | if (!_lcd_on) | ||
91 | return; | ||
92 | |||
93 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); | ||
94 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h new file mode 100755 index 0000000000..e74f008a3e --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef _ADC_TARGET_H_ | ||
22 | #define _ADC_TARGET_H_ | ||
23 | |||
24 | #define NUM_ADC_CHANNELS 4 | ||
25 | |||
26 | #define ADC_BUTTONS 0 | ||
27 | |||
28 | #endif /* _ADC_TARGET_H_ */ | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c new file mode 100755 index 0000000000..9deab7712a --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c | |||
@@ -0,0 +1,80 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "backlight-target.h" | ||
25 | |||
26 | #define GPIO_PWM 123 | ||
27 | #define PWM_CHN 7 | ||
28 | #define PWM_FULL 101 | ||
29 | |||
30 | static void set_backlight(int unk, int val) | ||
31 | { | ||
32 | if(val == 0) | ||
33 | __gpio_as_pwm7(); | ||
34 | else | ||
35 | { | ||
36 | REG_TCU_TCSR(7) |= 2; | ||
37 | REG_TCU_TCSR(7) &= ~0x100; | ||
38 | int tmp; | ||
39 | tmp = (unk/2 + __cpm_get_rtcclk()) / unk; | ||
40 | if(tmp > 0xFFFF) | ||
41 | tmp = 0xFFFF; | ||
42 | |||
43 | __tcu_set_half_data(7, (tmp * unk * 1374389535) >> 5); | ||
44 | __tcu_set_full_data(7, tmp); | ||
45 | |||
46 | REG_TCU_TSCR = (1 << 7); | ||
47 | REG_TCU_TESR = (1 << 7); | ||
48 | |||
49 | __tcu_enable_pwm_output(7); | ||
50 | } | ||
51 | __tcu_set_count(7, 0); | ||
52 | } | ||
53 | |||
54 | bool _backlight_init(void) | ||
55 | { | ||
56 | __gpio_as_pwm7(); | ||
57 | |||
58 | __tcu_stop_counter(7); | ||
59 | __tcu_disable_pwm_output(7); | ||
60 | |||
61 | set_backlight(300, 7); | ||
62 | |||
63 | return true; | ||
64 | } | ||
65 | void _backlight_on(void) | ||
66 | { | ||
67 | set_backlight(300, 7); | ||
68 | } | ||
69 | void _backlight_off(void) | ||
70 | { | ||
71 | set_backlight(300, 0); | ||
72 | } | ||
73 | |||
74 | #ifdef HAVE_BACKLIGHT_BRIGHTNESS | ||
75 | void _backlight_set_brightness(int brightness) | ||
76 | { | ||
77 | (void)brightness; | ||
78 | return; | ||
79 | } | ||
80 | #endif | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h new file mode 100755 index 0000000000..4170f96cc0 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef BACKLIGHT_TARGET_H | ||
22 | #define BACKLIGHT_TARGET_H | ||
23 | |||
24 | #ifdef BOOTLOADER | ||
25 | #define BACKLIGHT_DRIVER_CLOSE | ||
26 | /* Force the whole driver to be built */ | ||
27 | #define BACKLIGHT_FULL_INIT | ||
28 | #endif | ||
29 | |||
30 | #include <stdbool.h> | ||
31 | |||
32 | bool _backlight_init(void); | ||
33 | void _backlight_on(void); | ||
34 | void _backlight_off(void); | ||
35 | void _backlight_set_brightness(int brightness); | ||
36 | |||
37 | #endif /* BACKLIGHT_TARGET_H */ | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c new file mode 100755 index 0000000000..e42325bcb3 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c | |||
@@ -0,0 +1,123 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "button-target.h" | ||
25 | |||
26 | #define BTN_VOL_DOWN (1 << 27) | ||
27 | #define BTN_VOL_UP (1 << 0) | ||
28 | #define BTN_MENU (1 << 1) | ||
29 | #define BTN_OFF (1 << 29) | ||
30 | #define BTN_HOLD (1 << 16) | ||
31 | #define BTN_MASK (BTN_VOL_DOWN | BTN_VOL_UP \ | ||
32 | | BTN_MENU | BTN_OFF ) | ||
33 | |||
34 | #define SADC_CFG_INIT ( \ | ||
35 | (2 << SADC_CFG_CLKOUT_NUM_BIT) | \ | ||
36 | SADC_CFG_XYZ1Z2 | \ | ||
37 | SADC_CFG_SNUM_5 | \ | ||
38 | (1 << SADC_CFG_CLKDIV_BIT) | \ | ||
39 | SADC_CFG_PBAT_HIGH | \ | ||
40 | SADC_CFG_CMD_INT_PEN ) | ||
41 | |||
42 | bool button_hold(void) | ||
43 | { | ||
44 | return (REG_GPIO_PXPIN(3) ^ BTN_HOLD ? 1 : 0); | ||
45 | } | ||
46 | |||
47 | void button_init_device(void) | ||
48 | { | ||
49 | REG_SADC_ENA = 0; | ||
50 | REG_SADC_STATE &= (~REG_SADC_STATE); | ||
51 | REG_SADC_CTRL = 0x1f; | ||
52 | |||
53 | __cpm_start_sadc(); | ||
54 | REG_SADC_CFG = SADC_CFG_INIT; | ||
55 | |||
56 | REG_SADC_SAMETIME = 1; | ||
57 | REG_SADC_WAITTIME = 1000; //per 100 HZ | ||
58 | REG_SADC_STATE &= (~REG_SADC_STATE); | ||
59 | REG_SADC_CTRL &= (~(SADC_CTRL_PENDM | SADC_CTRL_TSRDYM)); | ||
60 | REG_SADC_ENA = SADC_ENA_TSEN; // | REG_SADC_ENA;//SADC_ENA_TSEN | SADC_ENA_PBATEN | SADC_ENA_SADCINEN; | ||
61 | } | ||
62 | |||
63 | static int touch_to_pixels(short x, short y) | ||
64 | { | ||
65 | /* X:300 -> 3800 Y:300->3900 */ | ||
66 | x -= 300; | ||
67 | y -= 300; | ||
68 | |||
69 | x /= 3200 / LCD_WIDTH; | ||
70 | y /= 3600 / LCD_HEIGHT; | ||
71 | |||
72 | return (x << 16) | y; | ||
73 | } | ||
74 | |||
75 | int button_read_device(int *data) | ||
76 | { | ||
77 | unsigned int key = ~REG_GPIO_PXPIN(3); | ||
78 | int ret = 0; | ||
79 | if(key & BTN_MASK) | ||
80 | { | ||
81 | if(key & BTN_VOL_DOWN) | ||
82 | ret |= BUTTON_VOL_DOWN; | ||
83 | if(key & BTN_VOL_UP) | ||
84 | ret |= BUTTON_VOL_UP; | ||
85 | if(key & BTN_MENU) | ||
86 | ret |= BUTTON_MENU; | ||
87 | if(key & BTN_OFF) | ||
88 | ret |= BUTTON_POWER; | ||
89 | } | ||
90 | |||
91 | if(REG_SADC_STATE & (SADC_CTRL_TSRDYM|SADC_STATE_PEND)) | ||
92 | { | ||
93 | if(REG_SADC_STATE & SADC_CTRL_PENDM) | ||
94 | { | ||
95 | REG_SADC_CTRL &= (~(SADC_CTRL_PENUM | SADC_CTRL_TSRDYM)); | ||
96 | REG_SADC_CTRL |= (SADC_CTRL_PENDM); | ||
97 | unsigned int dat; | ||
98 | unsigned short xData,yData; | ||
99 | short tsz1Data,tsz2Data; | ||
100 | |||
101 | dat = REG_SADC_TSDAT; | ||
102 | |||
103 | xData = (dat >> 0) & 0xfff; | ||
104 | yData = (dat >> 16) & 0xfff; | ||
105 | |||
106 | dat = REG_SADC_TSDAT; | ||
107 | tsz1Data = (dat >> 0) & 0xfff; | ||
108 | tsz2Data = (dat >> 16) & 0xfff; | ||
109 | |||
110 | *data = touch_to_pixels(xData, yData); | ||
111 | |||
112 | tsz1Data = tsz2Data - tsz1Data; | ||
113 | } | ||
114 | REG_SADC_STATE = 0; | ||
115 | //__intc_unmask_irq(IRQ_SADC); | ||
116 | } | ||
117 | |||
118 | return ret; | ||
119 | } | ||
120 | void button_set_touch_available(void) | ||
121 | { | ||
122 | return; | ||
123 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h new file mode 100755 index 0000000000..23ce386cb1 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef BUTTON_TARGET_H | ||
22 | #define BUTTON_TARGET_H | ||
23 | |||
24 | |||
25 | #include <stdbool.h> | ||
26 | #include "config.h" | ||
27 | |||
28 | #define HAS_BUTTON_HOLD | ||
29 | |||
30 | bool button_hold(void); | ||
31 | void button_init_device(void); | ||
32 | int button_read_device(int *data); | ||
33 | void button_set_touch_available(void); | ||
34 | |||
35 | /* Main unit's buttons */ | ||
36 | #define BUTTON_POWER 0x00000001 | ||
37 | #define BUTTON_VOL_UP 0x00000002 | ||
38 | #define BUTTON_VOL_DOWN 0x00000004 | ||
39 | #define BUTTON_MENU 0x00000008 | ||
40 | |||
41 | /* Compatibility hacks for flipping. Needs a somewhat better fix. */ | ||
42 | #define BUTTON_LEFT BUTTON_MIDLEFT | ||
43 | #define BUTTON_RIGHT BUTTON_MIDRIGHT | ||
44 | #define BUTTON_UP BUTTON_TOPMIDDLE | ||
45 | #define BUTTON_DOWN BUTTON_BOTTOMMIDDLE | ||
46 | |||
47 | /* Touchpad Screen Area Buttons */ | ||
48 | #define BUTTON_TOPLEFT 0x00000010 | ||
49 | #define BUTTON_TOPMIDDLE 0x00000020 | ||
50 | #define BUTTON_TOPRIGHT 0x00000040 | ||
51 | #define BUTTON_MIDLEFT 0x00000080 | ||
52 | #define BUTTON_CENTER 0x00000100 | ||
53 | #define BUTTON_MIDRIGHT 0x00000200 | ||
54 | #define BUTTON_BOTTOMLEFT 0x00000400 | ||
55 | #define BUTTON_BOTTOMMIDDLE 0x00000800 | ||
56 | #define BUTTON_BOTTOMRIGHT 0x00001000 | ||
57 | |||
58 | #define BUTTON_TOUCH 0x00002000 | ||
59 | |||
60 | #define BUTTON_MAIN 0x3FFF | ||
61 | |||
62 | /* No remote */ | ||
63 | #define BUTTON_REMOTE 0 | ||
64 | |||
65 | /* Software power-off */ | ||
66 | #define POWEROFF_BUTTON BUTTON_POWER | ||
67 | #define POWEROFF_COUNT 10 | ||
68 | |||
69 | #endif /* BUTTON_TARGET_H */ | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c new file mode 100755 index 0000000000..d46cee6884 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | |||
@@ -0,0 +1,201 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "lcd-target.h" | ||
25 | |||
26 | #define PIN_CS_N (32*1+17) /* Chip select */ | ||
27 | #define PIN_RESET_N (32*1+18) /* Reset */ | ||
28 | |||
29 | #define my__gpio_as_lcd_16bit() \ | ||
30 | do { \ | ||
31 | REG_GPIO_PXFUNS(2) = 0x001cffff; \ | ||
32 | REG_GPIO_PXSELC(2) = 0x001cffff; \ | ||
33 | REG_GPIO_PXPES(2) = 0x001cffff; \ | ||
34 | } while (0) | ||
35 | |||
36 | |||
37 | #define SLEEP(x) for(i=0; i<x; i++) asm("nop"); asm("nop"); | ||
38 | #define DELAY SLEEP(700000); | ||
39 | static void _display_pin_init(void) | ||
40 | { | ||
41 | int i; | ||
42 | my__gpio_as_lcd_16bit(); | ||
43 | __gpio_as_output(PIN_CS_N); | ||
44 | __gpio_as_output(PIN_RESET_N); | ||
45 | __gpio_clear_pin(PIN_CS_N); | ||
46 | |||
47 | __gpio_set_pin(PIN_RESET_N); | ||
48 | DELAY; | ||
49 | __gpio_clear_pin(PIN_RESET_N); | ||
50 | DELAY; | ||
51 | __gpio_set_pin(PIN_RESET_N); | ||
52 | DELAY; | ||
53 | } | ||
54 | |||
55 | #define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY); | ||
56 | #define SLCD_SET_DATA(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_DATA; | ||
57 | #define SLCD_SET_COMMAND(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_COMMAND; | ||
58 | #define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val); | ||
59 | static void _display_on(void) | ||
60 | { | ||
61 | int i; | ||
62 | |||
63 | SLCD_SEND_COMMAND(0x600, 1); | ||
64 | SLEEP(700000); | ||
65 | SLCD_SEND_COMMAND(0x600, 0); | ||
66 | SLEEP(700000); | ||
67 | SLCD_SEND_COMMAND(0x606, 0); | ||
68 | |||
69 | SLCD_SEND_COMMAND(1, 0x100); | ||
70 | SLCD_SEND_COMMAND(2, 0x100); | ||
71 | SLCD_SEND_COMMAND(3, 0x1028); | ||
72 | SLCD_SEND_COMMAND(8, 0x503); | ||
73 | SLCD_SEND_COMMAND(9, 1); | ||
74 | SLCD_SEND_COMMAND(0xB, 0x10); | ||
75 | SLCD_SEND_COMMAND(0xC, 0); | ||
76 | SLCD_SEND_COMMAND(0xF, 0); | ||
77 | SLCD_SEND_COMMAND(7, 1); | ||
78 | SLCD_SEND_COMMAND(0x10, 0x12); | ||
79 | SLCD_SEND_COMMAND(0x11, 0x202); | ||
80 | SLCD_SEND_COMMAND(0x12, 0x300); | ||
81 | SLCD_SEND_COMMAND(0x20, 0x21e); | ||
82 | SLCD_SEND_COMMAND(0x21, 0x202); | ||
83 | SLCD_SEND_COMMAND(0x22, 0x100); | ||
84 | SLCD_SEND_COMMAND(0x90, 0x8000); | ||
85 | SLCD_SEND_COMMAND(0x100, 0x16b0); | ||
86 | SLCD_SEND_COMMAND(0x101, 0x147); | ||
87 | SLCD_SEND_COMMAND(0x102, 0x1bd); | ||
88 | SLCD_SEND_COMMAND(0x103, 0x2f00); | ||
89 | SLCD_SEND_COMMAND(0x107, 0); | ||
90 | SLCD_SEND_COMMAND(0x110, 1); | ||
91 | SLCD_SEND_COMMAND(0x200, 0); /* set cursor at x_start */ | ||
92 | SLCD_SEND_COMMAND(0x201, 0); /* set cursor at y_start */ | ||
93 | SLCD_SEND_COMMAND(0x210, 0); /* y_start*/ | ||
94 | SLCD_SEND_COMMAND(0x211, 239); /* y_end */ | ||
95 | SLCD_SEND_COMMAND(0x212, 0); /* x_start */ | ||
96 | SLCD_SEND_COMMAND(0x213, 399); /* x_end */ | ||
97 | SLCD_SEND_COMMAND(0x280, 0); | ||
98 | SLCD_SEND_COMMAND(0x281, 6); | ||
99 | SLCD_SEND_COMMAND(0x282, 0); | ||
100 | SLCD_SEND_COMMAND(0x300, 0x101); | ||
101 | SLCD_SEND_COMMAND(0x301, 0xb27); | ||
102 | SLCD_SEND_COMMAND(0x302, 0x132a); | ||
103 | SLCD_SEND_COMMAND(0x303, 0x2a13); | ||
104 | SLCD_SEND_COMMAND(0x304, 0x270b); | ||
105 | SLCD_SEND_COMMAND(0x305, 0x101); | ||
106 | SLCD_SEND_COMMAND(0x306, 0x1205); | ||
107 | SLCD_SEND_COMMAND(0x307, 0x512); | ||
108 | SLCD_SEND_COMMAND(0x308, 5); | ||
109 | SLCD_SEND_COMMAND(0x309, 3); | ||
110 | SLCD_SEND_COMMAND(0x30a, 0xf04); | ||
111 | SLCD_SEND_COMMAND(0x30b, 0xf00); | ||
112 | SLCD_SEND_COMMAND(0x30c, 0xf); | ||
113 | SLCD_SEND_COMMAND(0x30d, 0x40f); | ||
114 | SLCD_SEND_COMMAND(0x30e, 0x300); | ||
115 | SLCD_SEND_COMMAND(0x30f, 0x500); | ||
116 | SLCD_SEND_COMMAND(0x400, 0x3100); | ||
117 | SLCD_SEND_COMMAND(0x401, 1); | ||
118 | SLCD_SEND_COMMAND(0x404, 0); | ||
119 | SLCD_SEND_COMMAND(0x500, 0); | ||
120 | SLCD_SEND_COMMAND(0x501, 0); | ||
121 | SLCD_SEND_COMMAND(0x502, 0); | ||
122 | SLCD_SEND_COMMAND(0x503, 0); | ||
123 | SLCD_SEND_COMMAND(0x504, 0); | ||
124 | SLCD_SEND_COMMAND(0x505, 0); | ||
125 | SLCD_SEND_COMMAND(0x606, 0); | ||
126 | SLCD_SEND_COMMAND(0x6f0, 0); | ||
127 | SLCD_SEND_COMMAND(0x7f0, 0x5420); | ||
128 | SLCD_SEND_COMMAND(0x7f3, 0x288a); | ||
129 | SLCD_SEND_COMMAND(0x7f4, 0x22); | ||
130 | SLCD_SEND_COMMAND(0x7f5, 1); | ||
131 | SLCD_SEND_COMMAND(0x7f0, 0); | ||
132 | |||
133 | SLCD_SEND_COMMAND(7, 0x173); | ||
134 | SLEEP(3500000); | ||
135 | SLCD_SEND_COMMAND(7, 0x171); | ||
136 | SLEEP(3500000); | ||
137 | SLCD_SEND_COMMAND(7, 0x173); | ||
138 | SLEEP(3500000); | ||
139 | } | ||
140 | |||
141 | static void _set_lcd_bus(void) | ||
142 | { | ||
143 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; | ||
144 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; | ||
145 | |||
146 | REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT | ||
147 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | ||
148 | | SLCD_CFG_TYPE_PARALLEL); | ||
149 | |||
150 | REG_SLCD_CTRL = SLCD_CTRL_DMA_EN; | ||
151 | } | ||
152 | |||
153 | static void _set_lcd_clock(void) | ||
154 | { | ||
155 | unsigned int val; | ||
156 | int pll_div; | ||
157 | |||
158 | __cpm_stop_lcd(); | ||
159 | pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ | ||
160 | pll_div = pll_div ? 1 : 2 ; | ||
161 | val = ( __cpm_get_pllout()/pll_div ) / 336000000; | ||
162 | val--; | ||
163 | if ( val > 0x1ff ) | ||
164 | { | ||
165 | //printf("CPM_LPCDR too large, set it to 0x1ff\n"); | ||
166 | val = 0x1ff; | ||
167 | } | ||
168 | __cpm_set_pixdiv(val); | ||
169 | __cpm_start_lcd(); | ||
170 | } | ||
171 | |||
172 | void lcd_init_controller(void) | ||
173 | { | ||
174 | int i; | ||
175 | _display_pin_init(); | ||
176 | _set_lcd_bus(); | ||
177 | _set_lcd_clock(); | ||
178 | SLEEP(1000); | ||
179 | _display_on(); | ||
180 | } | ||
181 | |||
182 | void lcd_set_target(short x, short y, short width, short height) | ||
183 | { | ||
184 | SLCD_SEND_COMMAND(0x210, y); /* y_start */ | ||
185 | SLCD_SEND_COMMAND(0x211, y+height); /* y_end */ | ||
186 | SLCD_SEND_COMMAND(0x212, x); /* x_start */ | ||
187 | SLCD_SEND_COMMAND(0x213, x+width); /* x_end */ | ||
188 | SLCD_SEND_COMMAND(0x200, x); /* set cursor at x_start */ | ||
189 | SLCD_SEND_COMMAND(0x201, y); /* set cursor at y_start */ | ||
190 | SLCD_SET_COMMAND(0x202); /* write data? */ | ||
191 | } | ||
192 | |||
193 | void lcd_on(void) | ||
194 | { | ||
195 | _display_on(); | ||
196 | } | ||
197 | |||
198 | void lcd_off(void) | ||
199 | { | ||
200 | return; | ||
201 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h new file mode 100755 index 0000000000..e643608d56 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef LCD_TARGET_H | ||
22 | #define LCD_TARGET_H | ||
23 | |||
24 | #include <stdbool.h> | ||
25 | |||
26 | void lcd_enable(bool state); | ||
27 | bool lcd_enabled(void); | ||
28 | void lcd_init_device(void); | ||
29 | |||
30 | |||
31 | void lcd_init_controller(void); | ||
32 | void lcd_set_target(short x, short y, short width, short height); | ||
33 | void lcd_on(void); | ||
34 | void lcd_off(void); | ||
35 | |||
36 | #endif /* LCD_TARGET_H */ | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h new file mode 100755 index 0000000000..30893aaaa3 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef USB_TARGET_H | ||
22 | #define USB_TARGET_H | ||
23 | |||
24 | void usb_init_device(void); | ||
25 | |||
26 | #endif | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c new file mode 100755 index 0000000000..4963cac517 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -0,0 +1,71 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "mipsregs.h" | ||
25 | |||
26 | void intr_handler(void) | ||
27 | { | ||
28 | return; | ||
29 | } | ||
30 | |||
31 | void except_handler(void* stack_ptr, unsigned int cause, unsigned int epc) | ||
32 | { | ||
33 | (void)stack_ptr; | ||
34 | (void)cause; | ||
35 | (void)epc; | ||
36 | REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN; | ||
37 | while(1); | ||
38 | } | ||
39 | |||
40 | void system_reboot(void) | ||
41 | { | ||
42 | while(1); | ||
43 | } | ||
44 | |||
45 | void cli(void) | ||
46 | { | ||
47 | register unsigned int t; | ||
48 | t = read_c0_status(); | ||
49 | t &= ~1; | ||
50 | write_c0_status(t); | ||
51 | } | ||
52 | |||
53 | unsigned int mips_get_sr(void) | ||
54 | { | ||
55 | unsigned int t = read_c0_status(); | ||
56 | return t; | ||
57 | } | ||
58 | |||
59 | void sti(void) | ||
60 | { | ||
61 | register unsigned int t; | ||
62 | t = read_c0_status(); | ||
63 | t |= 1; | ||
64 | t &= ~2; | ||
65 | write_c0_status(t); | ||
66 | } | ||
67 | |||
68 | void tick_start(unsigned int interval_in_ms) | ||
69 | { | ||
70 | (void)interval_in_ms; | ||
71 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h new file mode 100755 index 0000000000..2fff6423b9 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/system-target.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "jz4740.h" | ||
24 | #include "mipsregs.h" | ||
25 | |||
26 | /* Core-level interrupt masking */ | ||
27 | |||
28 | /* This one returns the old status */ | ||
29 | #define HIGHEST_IRQ_LEVEL 0 | ||
30 | |||
31 | #define set_irq_level(status) \ | ||
32 | set_interrupt_status((status), ST0_IE) | ||
33 | #define set_fiq_status(status) \ | ||
34 | set_interrupt_status((status), ST0_IE) | ||
35 | |||
36 | static inline int set_interrupt_status(int status, int mask) | ||
37 | { | ||
38 | unsigned int res, oldstatus; | ||
39 | |||
40 | res = oldstatus = read_c0_status(); | ||
41 | res &= ~mask; | ||
42 | res |= (status & mask); | ||
43 | write_c0_status(res); | ||
44 | |||
45 | return oldstatus; | ||
46 | } | ||
47 | |||
48 | static inline void enable_interrupt(void) | ||
49 | { | ||
50 | /* Set IE bit */ | ||
51 | set_c0_status(ST0_IE); | ||
52 | } | ||
53 | |||
54 | static inline void disable_interrupt(void) | ||
55 | { | ||
56 | /* Clear IE bit */ | ||
57 | clear_c0_status(ST0_IE); | ||
58 | } | ||
59 | |||
60 | #define disable_irq() \ | ||
61 | disable_interrupt() | ||
62 | |||
63 | #define enable_irq() \ | ||
64 | enable_interrupt() | ||
65 | |||
66 | #define disable_fiq() \ | ||
67 | disable_interrupt() | ||
68 | |||
69 | #define enable_fiq() \ | ||
70 | enable_interrupt() | ||
71 | |||
72 | static inline int disable_interrupt_save(int mask) | ||
73 | { | ||
74 | unsigned int oldstatus; | ||
75 | |||
76 | oldstatus = read_c0_status(); | ||
77 | write_c0_status(oldstatus | mask); | ||
78 | |||
79 | return oldstatus; | ||
80 | } | ||
81 | |||
82 | #define disable_irq_save() \ | ||
83 | disable_interrupt_save(ST0_IE) | ||
84 | |||
85 | #define disable_fiq_save() \ | ||
86 | disable_interrupt_save(ST0_IE) | ||
87 | |||
88 | static inline void restore_interrupt(int status) | ||
89 | { | ||
90 | write_c0_status(status); | ||
91 | } | ||
92 | |||
93 | #define restore_irq(cpsr) \ | ||
94 | restore_interrupt(cpsr) | ||
95 | |||
96 | #define restore_fiq(cpsr) \ | ||
97 | restore_interrupt(cpsr) | ||
98 | |||
99 | #define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff) | ||
100 | #define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff) | ||
101 | |||
102 | void sti(void); | ||
103 | void cli(void); | ||
diff --git a/firmware/thread.c b/firmware/thread.c index 4a808fb4b8..2eaa422841 100644 --- a/firmware/thread.c +++ b/firmware/thread.c | |||
@@ -985,6 +985,149 @@ static inline void core_sleep(void) | |||
985 | : : "z"(&SBYCR-GBR) : "r1"); | 985 | : : "z"(&SBYCR-GBR) : "r1"); |
986 | } | 986 | } |
987 | 987 | ||
988 | #elif CPU_MIPS == 32 | ||
989 | |||
990 | /*--------------------------------------------------------------------------- | ||
991 | * Start the thread running and terminate it if it returns | ||
992 | *--------------------------------------------------------------------------- | ||
993 | */ | ||
994 | void start_thread(void); /* Provide C access to ASM label */ | ||
995 | #if 0 | ||
996 | static void __attribute__((used)) __start_thread(void) | ||
997 | { | ||
998 | |||
999 | /* $v0 = context */ | ||
1000 | asm volatile ( | ||
1001 | ".set noreorder \n" | ||
1002 | "_start_thread: \n" /* Start here - no naked attribute */ | ||
1003 | "lw $8, (4)$2 \n" /* Fetch thread function pointer ($8 = $t0, $2 = $v0) */ | ||
1004 | "lw $29, (108)$2 \n" /* Set initial sp(=$29) */ | ||
1005 | "jalr $8 \n" /* Start the thread ($8 = $t0,)*/ | ||
1006 | "sw $0, (116)$2 \n" /* Clear start address ($2 = $v0) */ | ||
1007 | ".set reorder \n" | ||
1008 | ); | ||
1009 | thread_exit(); | ||
1010 | |||
1011 | } | ||
1012 | #else | ||
1013 | void start_thread(void) | ||
1014 | { | ||
1015 | return; | ||
1016 | } | ||
1017 | #endif | ||
1018 | |||
1019 | /* Place context pointer in $v0 slot, function pointer in $v1 slot, and | ||
1020 | * start_thread pointer in context_start */ | ||
1021 | #define THREAD_STARTUP_INIT(core, thread, function) \ | ||
1022 | ({ (thread)->context.r[0] = (uint32_t)&(thread)->context, \ | ||
1023 | (thread)->context.r[1] = (uint32_t)(function), \ | ||
1024 | (thread)->context.start = (uint32_t)start_thread; }) | ||
1025 | |||
1026 | /*--------------------------------------------------------------------------- | ||
1027 | * Store non-volatile context. | ||
1028 | *--------------------------------------------------------------------------- | ||
1029 | */ | ||
1030 | static inline void store_context(void* addr) | ||
1031 | { | ||
1032 | #if 0 | ||
1033 | asm volatile ( | ||
1034 | ".set noreorder \n" | ||
1035 | ".set noat \n" | ||
1036 | "sw $1, (0)%0 \n" | ||
1037 | "sw $2,(4)%0 \n" /* $v0 */ | ||
1038 | "sw $3,(8)%0 \n" /* $v1 */ | ||
1039 | "sw $4,(12)%0 \n" /* $a0 */ | ||
1040 | "sw $5,(16)%0 \n" /* $a1 */ | ||
1041 | "sw $6,(20)%0 \n" /* $a2 */ | ||
1042 | "sw $7,(24)%0 \n" /* $a3 */ | ||
1043 | "sw $8,(28)%0 \n" /* $t0 */ | ||
1044 | "sw $9,(32)%0 \n" /* $t1 */ | ||
1045 | "sw $10,(36)%0 \n" /* $t2 */ | ||
1046 | "sw $11,(40)%0 \n" /* $t3 */ | ||
1047 | "sw $12,(44)%0 \n" /* $t4 */ | ||
1048 | "sw $13,(48)%0 \n" /* $t5 */ | ||
1049 | "sw $14,(52)%0 \n" /* $t6 */ | ||
1050 | "sw $15,(56)%0 \n" /* $t7 */ | ||
1051 | "sw $24,(60)%0 \n" /* $t8 */ | ||
1052 | "sw $25,(64)%0 \n" /* $t9 */ | ||
1053 | "sw $16,(68)%0 \n" /* $s0 */ | ||
1054 | "sw $17,(72)%0 \n" /* $s1 */ | ||
1055 | "sw $18,(76)%0 \n" /* $s2 */ | ||
1056 | "sw $19,(80)%0 \n" /* $s3 */ | ||
1057 | "sw $20,(84)%0 \n" /* $s4 */ | ||
1058 | "sw $21,(88)%0 \n" /* $s5 */ | ||
1059 | "sw $22,(92)%0 \n" /* $s6 */ | ||
1060 | "sw $23,(96)%0 \n" /* $s7 */ | ||
1061 | "sw $28,(100)%0 \n" /* gp */ | ||
1062 | "sw $30,(104)%0 \n" /* fp */ | ||
1063 | "sw $29,(108)%0 \n" /* sp */ | ||
1064 | "sw $31,(112)%0 \n" /* ra */ | ||
1065 | ".set reorder \n" | ||
1066 | : : "r" (addr) | ||
1067 | ); | ||
1068 | #endif | ||
1069 | } | ||
1070 | |||
1071 | /*--------------------------------------------------------------------------- | ||
1072 | * Load non-volatile context. | ||
1073 | *--------------------------------------------------------------------------- | ||
1074 | */ | ||
1075 | static inline void load_context(const void* addr) | ||
1076 | { | ||
1077 | #if 0 | ||
1078 | asm volatile ( | ||
1079 | ".set noat \n" | ||
1080 | ".set noreorder \n" | ||
1081 | "lw $8, 116(%0) \n" /* Get start address ($8 = $t0) */ | ||
1082 | //"tst r0, r0 \n" | ||
1083 | "j .running \n" /* NULL -> already running */ | ||
1084 | "jr $8 \n" /* $t0 = $8 = context */ | ||
1085 | ".running: \n" | ||
1086 | "lw $1, (0)%0 \n" | ||
1087 | "lw $2,(4)%0 \n" /* $v0 */ | ||
1088 | "lw $3,(8)%0 \n" /* $v1 */ | ||
1089 | "lw $4,(12)%0 \n" /* $a0 */ | ||
1090 | "lw $5,(16)%0 \n" /* $a1 */ | ||
1091 | "lw $6,(20)%0 \n" /* $a2 */ | ||
1092 | "lw $7,(24)%0 \n" /* $a3 */ | ||
1093 | "lw $8,(28)%0 \n" /* $t0 */ | ||
1094 | "lw $9,(32)%0 \n" /* $t1 */ | ||
1095 | "lw $10,(36)%0 \n" /* $t2 */ | ||
1096 | "lw $11,(40)%0 \n" /* $t3 */ | ||
1097 | "lw $12,(44)%0 \n" /* $t4 */ | ||
1098 | "lw $13,(48)%0 \n" /* $t5 */ | ||
1099 | "lw $14,(52)%0 \n" /* $t6 */ | ||
1100 | "lw $15,(56)%0 \n" /* $t7 */ | ||
1101 | "lw $24,(60)%0 \n" /* $t8 */ | ||
1102 | "lw $25,(64)%0 \n" /* $t9 */ | ||
1103 | "lw $16,(68)%0 \n" /* $s0 */ | ||
1104 | "lw $17,(72)%0 \n" /* $s1 */ | ||
1105 | "lw $18,(76)%0 \n" /* $s2 */ | ||
1106 | "lw $19,(80)%0 \n" /* $s3 */ | ||
1107 | "lw $20,(84)%0 \n" /* $s4 */ | ||
1108 | "lw $21,(88)%0 \n" /* $s5 */ | ||
1109 | "lw $22,(92)%0 \n" /* $s6 */ | ||
1110 | "lw $23,(96)%0 \n" /* $s7 */ | ||
1111 | "lw $28,(100)%0 \n" /* gp */ | ||
1112 | "lw $30,(104)%0 \n" /* fp */ | ||
1113 | "lw $29,(108)%0 \n" /* sp */ | ||
1114 | "lw $31,(112)%0 \n" /* ra */ | ||
1115 | ".set reorder \n" | ||
1116 | : : "r" (addr) : "v0" /* only! */ | ||
1117 | ); | ||
1118 | #endif | ||
1119 | } | ||
1120 | |||
1121 | /*--------------------------------------------------------------------------- | ||
1122 | * Put core in a power-saving state. | ||
1123 | *--------------------------------------------------------------------------- | ||
1124 | */ | ||
1125 | static inline void core_sleep(void) | ||
1126 | { | ||
1127 | asm volatile("nop\n"); | ||
1128 | } | ||
1129 | |||
1130 | |||
988 | #endif /* CONFIG_CPU == */ | 1131 | #endif /* CONFIG_CPU == */ |
989 | 1132 | ||
990 | /* | 1133 | /* |
@@ -1909,6 +2052,8 @@ static inline void block_thread_on_l(struct thread_entry *thread, | |||
1909 | */ | 2052 | */ |
1910 | void switch_thread(void) | 2053 | void switch_thread(void) |
1911 | { | 2054 | { |
2055 | #ifndef ONDA_VX747 | ||
2056 | |||
1912 | const unsigned int core = CURRENT_CORE; | 2057 | const unsigned int core = CURRENT_CORE; |
1913 | struct thread_entry *block = cores[core].block_task; | 2058 | struct thread_entry *block = cores[core].block_task; |
1914 | struct thread_entry *thread = cores[core].running; | 2059 | struct thread_entry *thread = cores[core].running; |
@@ -2043,6 +2188,8 @@ void switch_thread(void) | |||
2043 | #ifdef RB_PROFILE | 2188 | #ifdef RB_PROFILE |
2044 | profile_thread_started(thread - threads); | 2189 | profile_thread_started(thread - threads); |
2045 | #endif | 2190 | #endif |
2191 | |||
2192 | #endif | ||
2046 | } | 2193 | } |
2047 | 2194 | ||
2048 | /*--------------------------------------------------------------------------- | 2195 | /*--------------------------------------------------------------------------- |