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diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
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1/*
2 * init.S
3 *
4 * Initialization code for JzRISC.
5 *
6 * Author: Seeger Chin
7 * e-mail: seeger.chin@gmail.com
8 *
9 * Copyright (C) 2006 Ingenic Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#include "config.h"
18#include "mips.h"
19
20 .text
21
22 .set mips3
23
24 .extern main
25
26 .global _start
27#ifdef BOOTLOADER
28 .section .init.text,"ax",%progbits
29#else
30 .section .resetvectors,"ax",%progbits
31#endif
32 .set noreorder
33 .set noat
34
35#ifdef BOOTLOADER
36 .word 0 /* HACK */
37 .word 0 /* HACK */
38#endif
39_start:
40 la ra, _start
41 //----------------------------------------------------
42 // init cp0 registers.
43 //----------------------------------------------------
44 mtc0 zero, C0_WATCHLO
45 mtc0 zero, C0_WATCHHI
46
47 li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
48 | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
49 | M_StatusIM2 | M_StatusERL)
50 // BEV = Enable Boot Exception Vectors
51 // IMx = Interrupt mask
52 // ERL = Denotes error level
53 mtc0 t0, C0_STATUS
54
55 li t1, M_CauseIV
56 mtc0 t1, C0_CAUSE
57
58 //----------------------------------------------------
59 // init caches, assumes a 4way*128set*32byte i/d cache
60 //----------------------------------------------------
61 li t0, 3 // enable cache for kseg0 accesses
62 mtc0 t0, C0_CONFIG // CONFIG reg
63 la t0, 0x80000000 // an idx op should use a unmappable address
64 ori t1, t0, 0x4000 // 16kB cache
65 mtc0 zero, C0_TAGLO // TAGLO reg
66 mtc0 zero, C0_TAGHI // TAGHI reg
67
68_init_cache_loop:
69 cache 0x8, 0(t0) // index store icache tag
70 cache 0x9, 0(t0) // index store dcache tag
71 bne t0, t1, _init_cache_loop
72 addiu t0, t0, 0x20 // 32 bytes per cache line
73 nop
74
75 //----------------------------------------------------
76 // Invalidate BTB
77 //----------------------------------------------------
78 mfc0 t0, C0_CONFIG
79 nop
80 ori t0, 2
81 mtc0 t0, C0_CONFIG
82 nop
83
84 //----------------------------------------------------
85 // setup stack, jump to C code
86 //----------------------------------------------------
87 la sp, stackend
88 la t0, stackbegin
89 li t1, 0xDEADBEEF
90
91_init_stack_loop:
92 sw t1, 0(t0)
93 bne t0, sp, _init_stack_loop
94 addiu t0, t0, 4
95
96 la t0, main
97 jr t0
98 nop
99
100
101#ifndef BOOTLOADER
102 .section .vectors,"ax",%progbits
103#endif
104 .extern exception_handler
105 .global except_common_entry
106 .type except_common_entry,@function
107except_common_entry:
108 la k0, exception_handler
109 jr k0
110 nop
111 nop
112 nop
113
114 .extern _int
115 .extern _exception
116 .global exception_handler
117 .type exception_handler,@function
118 .set noreorder
119exception_handler:
120
121
122 addiu sp, -0x80 # Add Immediate Unsigned
123 sw ra, 0(sp) # Store Word
124 sw fp, 4(sp) # Store Word
125 sw gp, 8(sp) # Store Word
126 sw t9, 0xC(sp) # Store Word
127 sw t8, 0x10(sp) # Store Word
128 sw s7, 0x14(sp) # Store Word
129 sw s6, 0x18(sp) # Store Word
130 sw s5, 0x1C(sp) # Store Word
131 sw s4, 0x20(sp) # Store Word
132 sw s3, 0x24(sp) # Store Word
133 sw s2, 0x28(sp) # Store Word
134 sw s1, 0x2C(sp) # Store Word
135 sw s0, 0x30(sp) # Store Word
136 sw t7, 0x34(sp) # Store Word
137 sw t6, 0x38(sp) # Store Word
138 sw t5, 0x3C(sp) # Store Word
139 sw t4, 0x40(sp) # Store Word
140 sw t3, 0x44(sp) # Store Word
141 sw t2, 0x48(sp) # Store Word
142 sw t1, 0x4C(sp) # Store Word
143 sw t0, 0x50(sp) # Store Word
144 sw a3, 0x54(sp) # Store Word
145 sw a2, 0x58(sp) # Store Word
146 sw a1, 0x5C(sp) # Store Word
147 sw a0, 0x60(sp) # Store Word
148 sw v1, 0x64(sp) # Store Word
149 sw v0, 0x68(sp) # Store Word
150 sw $1, 0x6C(sp) # Store Word
151 mflo t0 # Move F LO
152 nop
153 sw t0, 0x70(sp) # Store Word
154 mfhi t0 # Move F HI
155 nop
156 sw t0, 0x74(sp) # Store Word
157 mfc0 t0, C0_STATUS # Status register
158 sll zero, 1 # Shift Left Logical
159 sll zero, 1 # Shift Left Logical
160 sll zero, 1 # Shift Left Logical
161 sll zero, 1 # Shift Left Logical
162 sw t0, 0x78(sp) # Store Word
163 mfc0 t0, C0_EPC # Exception Program Counter
164 sll zero, 1 # Shift Left Logical
165 sll zero, 1 # Shift Left Logical
166 sll zero, 1 # Shift Left Logical
167 sll zero, 1 # Shift Left Logical
168 sw t0, 0x7C(sp) # Store Word
169 li k1, 0x7C # Load Immediate
170 mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
171 and k0, k1 # AND
172 beq zero, k0, _int # Branch on Equal
173 nop
174 la k0, _exception
175 jr k0
176 nop
177
178 .global _int
179 .type _int,@function
180_int:
181 jal intr_handler # Jump And Link
182 nop
183 lw ra, 0(sp) # Load Word
184 lw fp, 4(sp) # Load Word
185 sw gp, 8(sp) # Store Word
186 lw t9, 0xC(sp) # Load Word
187 lw t8, 0x10(sp) # Load Word
188 lw s7, 0x14(sp) # Load Word
189 lw s6, 0x18(sp) # Load Word
190 lw s5, 0x1C(sp) # Load Word
191 lw s4, 0x20(sp) # Load Word
192 lw s3, 0x24(sp) # Load Word
193 lw s2, 0x28(sp) # Load Word
194 lw s1, 0x2C(sp) # Load Word
195 lw s0, 0x30(sp) # Load Word
196 lw t7, 0x34(sp) # Load Word
197 lw t6, 0x38(sp) # Load Word
198 lw t5, 0x3C(sp) # Load Word
199 lw t4, 0x40(sp) # Load Word
200 lw t3, 0x44(sp) # Load Word
201 lw t2, 0x48(sp) # Load Word
202 lw t1, 0x4C(sp) # Load Word
203 lw t0, 0x50(sp) # Load Word
204 lw a3, 0x54(sp) # Load Word
205 lw a2, 0x58(sp) # Load Word
206 lw a1, 0x5C(sp) # Load Word
207 lw a0, 0x60(sp) # Load Word
208 lw v1, 0x64(sp) # Load Word
209 lw v0, 0x68(sp) # Load Word
210 lw v1, 0x6C(sp) # Load Word
211 lw k0, 0x70(sp) # Load Word
212 mtlo k0 # Move To LO
213 nop
214 lw k0, 0x74(sp) # Load Word
215 mthi k0 # Move To HI
216 nop
217 lw k0, 0x78(sp) # Load Word
218 nop
219 mtc0 k0, C0_STATUS # Status register
220 sll zero, 1 # Shift Left Logical
221 sll zero, 1 # Shift Left Logical
222 sll zero, 1 # Shift Left Logical
223 sll zero, 1 # Shift Left Logical
224 lw k0, 0x7C(sp) # Load Word
225 nop
226 mtc0 k0, C0_EPC # Exception Program Counter
227 sll zero, 1 # Shift Left Logical
228 sll zero, 1 # Shift Left Logical
229 sll zero, 1 # Shift Left Logical
230 sll zero, 1 # Shift Left Logical
231 addiu sp, 0x80 # Add Immediate Unsigned
232 eret # Exception Return
233 nop
234
235 .extern _except_handler
236 .global _exception
237 .type _exception,@function
238_exception:
239 move a0, sp
240 mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
241 mfc0 a2, C0_EPC # Exception Program Counter
242 la k0, except_handler # Load Address
243 jr k0 # Jump Register
244 nop
245
246 .set reorder
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