8 files changed, 19 insertions, 19 deletions

diff --git a/firmware/target/arm/tms320dm320/creative-zvm/pic-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/pic-creativezvm.c
index 334ef25683..836d46c067 100644
--- a/firmware/target/arm/tms320dm320/creative-zvm/pic-creativezvm.c
+++ b/firmware/target/arm/tms320dm320/creative-zvm/pic-creativezvm.c
@@ -271,7 +271,7 @@ void send_command_to_pic(unsigned char in, unsigned char* out,
     IO_INTC_EINT1 &= ~INTR_EINT1_EXT0;
     /* Clear EXT0 interrupt */
     IO_INTC_IRQ1 = INTR_IRQ1_EXT0;
-    /* Write command to I²C */
+    /* Write command to I²C */
     restart:
     i2c_write(PIC_ADR, &in, 1);
     /* Wait for PIC */
@@ -283,7 +283,7 @@ void send_command_to_pic(unsigned char in, unsigned char* out,
         if(i > 50)
             goto restart;
     }
-    /* Read return from I²C */
+    /* Read return from I²C */
     i2c_read(PIC_ADR, out, length);
     /* Re-enable GIO0 interrupt */
     IO_INTC_EINT1 |= INTR_EINT1_EXT0;
diff --git a/firmware/target/arm/tms320dm320/i2c-dm320.c b/firmware/target/arm/tms320dm320/i2c-dm320.c
index a87019c69c..7915ca5a94 100755
--- a/firmware/target/arm/tms320dm320/i2c-dm320.c
+++ b/firmware/target/arm/tms320dm320/i2c-dm320.c
@@ -9,7 +9,7 @@
  *
  * Copyright (C) 2008 by Maurus Cuelenaere
  *
- * DM320 I²C driver
+ * DM320 I²C driver
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
@@ -145,12 +145,12 @@ int i2c_read(unsigned short address, unsigned char* buf, int count)
 void i2c_init(void)
 {
 #if 0 //TODO: mimic OF I2C clock settings; currently this is done by the bootloader
-    IO_CLK_MOD2 &= ~CLK_MOD2_I2C; // turn I²C clock off (just to be sure)
+    IO_CLK_MOD2 &= ~CLK_MOD2_I2C; // turn I²C clock off (just to be sure)
     IO_CLK_LPCTL1 &= ~1; // set Powerdown mode to off
-    IO_CLK_SEL0 &= ~0x800; // set I²C clock to PLLA
-    IO_CLK_DIV4 &= ~0x1F; // I²C clock division = 1
-    IO_CLK_MOD2 |= CLK_MOD2_I2C; // enable I²C clock
+    IO_CLK_SEL0 &= ~0x800; // set I²C clock to PLLA
+    IO_CLK_DIV4 &= ~0x1F; // I²C clock division = 1
+    IO_CLK_MOD2 |= CLK_MOD2_I2C; // enable I²C clock
 #endif
     IO_I2C_SCS &= ~0x8; //set clock to 100 kHz
-    IO_INTC_EINT2 &= ~INTR_EINT2_I2C; // disable I²C interrupt
+    IO_INTC_EINT2 &= ~INTR_EINT2_I2C; // disable I²C interrupt
 }
diff --git a/firmware/target/arm/usb-drv-arc.c b/firmware/target/arm/usb-drv-arc.c
index 7758cba2e7..f785535100 100644
--- a/firmware/target/arm/usb-drv-arc.c
+++ b/firmware/target/arm/usb-drv-arc.c
@@ -9,7 +9,7 @@
  *
  * Driver for ARC USBOTG Device Controller
  *
- * Copyright (C) 2007 by Björn Stenberg
+ * Copyright (C) 2007 by Björn Stenberg
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c
index 5997f2419a..9f5bf04a64 100644
--- a/firmware/target/coldfire/iaudio/m3/adc-m3.c
+++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c
@@ -25,8 +25,8 @@
 
 #define ADC_I2C_ADDR 0xa0
 
-/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires
- * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read
+/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires
+ * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read
  * transfer each tick, and handle it via an ISR. At 11MHz, one transfer
  * takes too long to be started every tick, but it seems we have to live 
  * with that. */
@@ -92,7 +92,7 @@ unsigned short adc_read(int channel)
 
 void adc_init(void)
 {
-    MFDR2 = 0x1f;             /* I²C clock = SYSCLK / 3840 */
+    MFDR2 = 0x1f;             /* I²C clock = SYSCLK / 3840 */
     MBCR2 = IEN;              /* Enable interface */
     MBSR2 = 0;                /* Clear flags */
     MBCR2 = (IEN|IIEN);       /* Enable interrupts */
@@ -105,7 +105,7 @@ void adc_init(void)
         sleep(1);             /* Ensure valid readings when adc_init returns */
 }
 
-/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C
+/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C
  * implementation. If a transfer is stopped prematurely, it often locks up
  * and doesn't react anymore until the unit is power cycled. */
 
diff --git a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
index 8e483d23ad..4cb6d13adf 100644
--- a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
+++ b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
@@ -8,7 +8,7 @@
  * $Id$
  *
  * Copyright (C) 2004 by Jens Arnold
- * Based on the work of Alan Korr and Jörg Hohensohn
+ * Based on the work of Alan Korr and Jörg Hohensohn
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
diff --git a/firmware/target/coldfire/iriver/lcd-remote-iriver.c b/firmware/target/coldfire/iriver/lcd-remote-iriver.c
index 85ba0fef7a..83b7a022e5 100644
--- a/firmware/target/coldfire/iriver/lcd-remote-iriver.c
+++ b/firmware/target/coldfire/iriver/lcd-remote-iriver.c
@@ -7,7 +7,7 @@
  *                     \/            \/     \/    \/            \/
  * $Id$
  *
- * Copyright (C) 2005 by Richard S. La Charité III
+ * Copyright (C) 2005 by Richard S. La Charité III
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
diff --git a/firmware/target/sh/archos/lcd-as-archos-bitmap.S b/firmware/target/sh/archos/lcd-as-archos-bitmap.S
index f2ac525976..c6f95c23a3 100644
--- a/firmware/target/sh/archos/lcd-as-archos-bitmap.S
+++ b/firmware/target/sh/archos/lcd-as-archos-bitmap.S
@@ -8,7 +8,7 @@
  * $Id$
  *
  * Copyright (C) 2004 by Jens Arnold
- * Based on the work of Alan Korr and Jörg Hohensohn
+ * Based on the work of Alan Korr and Jörg Hohensohn
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
@@ -121,7 +121,7 @@ _lcd_write_data:
 
     /* This code will fail if an interrupt changes the contents of PBDRL.
      * If so, we must disable the interrupt here. If disabling interrupts
-     * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
+     * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
      * recorders)is undesirable, the loop has to be rewritten to
      * disable/precalculate/transfer/enable for each iteration. However,
      * this would significantly decrease performance. */
diff --git a/firmware/target/sh/archos/player/lcd-as-player.S b/firmware/target/sh/archos/player/lcd-as-player.S
index 6c19e1ab2f..3a80782735 100644
--- a/firmware/target/sh/archos/player/lcd-as-player.S
+++ b/firmware/target/sh/archos/player/lcd-as-player.S
@@ -8,7 +8,7 @@
  * $Id$
  *
  * Copyright (C) 2004 by Jens Arnold
- * Based on the work of Alan Korr and Jörg Hohensohn
+ * Based on the work of Alan Korr and Jörg Hohensohn
  *
  * All files in this archive are subject to the GNU General Public License.
  * See the file COPYING in the source tree root for full license agreement.
@@ -167,7 +167,7 @@ _lcd_write_data:
 
     /* This code will fail if an interrupt changes the contents of PBDRL.
      * If so, we must disable the interrupt here. If disabling interrupts
-     * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
+     * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
      * recorders)is undesirable, the loop has to be rewritten to
      * disable/precalculate/transfer/enable for each iteration. However,
      * this would significantly decrease performance. */