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Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000')
-rw-r--r--firmware/target/mips/ingenic_x1000/x1000/aic.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h
index d212ddc4e1..5f5e771c2c 100644
--- a/firmware/target/mips/ingenic_x1000/x1000/aic.h
+++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h
@@ -123,18 +123,30 @@
123#define JI_AIC_CCR 123#define JI_AIC_CCR
124#define BP_AIC_CCR_CHANNEL 24 124#define BP_AIC_CCR_CHANNEL 24
125#define BM_AIC_CCR_CHANNEL 0x7000000 125#define BM_AIC_CCR_CHANNEL 0x7000000
126#define BV_AIC_CCR_CHANNEL__MONO 0x0
127#define BV_AIC_CCR_CHANNEL__STEREO 0x1
126#define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) 128#define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24)
127#define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL 129#define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL
128#define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) 130#define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e)
129#define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL 131#define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL
130#define BP_AIC_CCR_OSS 19 132#define BP_AIC_CCR_OSS 19
131#define BM_AIC_CCR_OSS 0x380000 133#define BM_AIC_CCR_OSS 0x380000
134#define BV_AIC_CCR_OSS__8BIT 0x0
135#define BV_AIC_CCR_OSS__16BIT 0x1
136#define BV_AIC_CCR_OSS__18BIT 0x2
137#define BV_AIC_CCR_OSS__20BIT 0x3
138#define BV_AIC_CCR_OSS__24BIT 0x4
132#define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) 139#define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19)
133#define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS 140#define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS
134#define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) 141#define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e)
135#define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS 142#define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS
136#define BP_AIC_CCR_ISS 16 143#define BP_AIC_CCR_ISS 16
137#define BM_AIC_CCR_ISS 0x70000 144#define BM_AIC_CCR_ISS 0x70000
145#define BV_AIC_CCR_ISS__8BIT 0x0
146#define BV_AIC_CCR_ISS__16BIT 0x1
147#define BV_AIC_CCR_ISS__18BIT 0x2
148#define BV_AIC_CCR_ISS__20BIT 0x3
149#define BV_AIC_CCR_ISS__24BIT 0x4
138#define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) 150#define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16)
139#define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS 151#define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS
140#define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) 152#define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e)