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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-30 19:56:44 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-30 19:17:50 +0000 |
commit | f63edb52ef8ecf18520926b40b3c61db37081a9d (patch) | |
tree | 29c36d3f247d7bab2f547d76655ac81fa8a71946 /firmware/target/mips/ingenic_x1000/x1000 | |
parent | c78ba1aa689b178ebb73b2730bc1b13697371fbf (diff) | |
download | rockbox-f63edb52ef8ecf18520926b40b3c61db37081a9d.tar.gz rockbox-f63edb52ef8ecf18520926b40b3c61db37081a9d.zip |
x1000: refactor AIC initialization
Have pcm-x1000 handle most work, so target's audiohw code touches
only the relevant settings.
Change-Id: Icf3d1b7ca428ac50a5a16ecec39ed8186ac5ae13
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/aic.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h index d212ddc4e1..5f5e771c2c 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/aic.h +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
@@ -123,18 +123,30 @@ | |||
123 | #define JI_AIC_CCR | 123 | #define JI_AIC_CCR |
124 | #define BP_AIC_CCR_CHANNEL 24 | 124 | #define BP_AIC_CCR_CHANNEL 24 |
125 | #define BM_AIC_CCR_CHANNEL 0x7000000 | 125 | #define BM_AIC_CCR_CHANNEL 0x7000000 |
126 | #define BV_AIC_CCR_CHANNEL__MONO 0x0 | ||
127 | #define BV_AIC_CCR_CHANNEL__STEREO 0x1 | ||
126 | #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) | 128 | #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) |
127 | #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL | 129 | #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL |
128 | #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) | 130 | #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) |
129 | #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL | 131 | #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL |
130 | #define BP_AIC_CCR_OSS 19 | 132 | #define BP_AIC_CCR_OSS 19 |
131 | #define BM_AIC_CCR_OSS 0x380000 | 133 | #define BM_AIC_CCR_OSS 0x380000 |
134 | #define BV_AIC_CCR_OSS__8BIT 0x0 | ||
135 | #define BV_AIC_CCR_OSS__16BIT 0x1 | ||
136 | #define BV_AIC_CCR_OSS__18BIT 0x2 | ||
137 | #define BV_AIC_CCR_OSS__20BIT 0x3 | ||
138 | #define BV_AIC_CCR_OSS__24BIT 0x4 | ||
132 | #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) | 139 | #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) |
133 | #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS | 140 | #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS |
134 | #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) | 141 | #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) |
135 | #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS | 142 | #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS |
136 | #define BP_AIC_CCR_ISS 16 | 143 | #define BP_AIC_CCR_ISS 16 |
137 | #define BM_AIC_CCR_ISS 0x70000 | 144 | #define BM_AIC_CCR_ISS 0x70000 |
145 | #define BV_AIC_CCR_ISS__8BIT 0x0 | ||
146 | #define BV_AIC_CCR_ISS__16BIT 0x1 | ||
147 | #define BV_AIC_CCR_ISS__18BIT 0x2 | ||
148 | #define BV_AIC_CCR_ISS__20BIT 0x3 | ||
149 | #define BV_AIC_CCR_ISS__24BIT 0x4 | ||
138 | #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) | 150 | #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) |
139 | #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS | 151 | #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS |
140 | #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) | 152 | #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) |