summaryrefslogtreecommitdiff
path: root/firmware/target/mips/ingenic_jz47xx
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c24
-rw-r--r--firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c13
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c13
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4740.c2
4 files changed, 42 insertions, 10 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
index ad053c7deb..00165b2d2d 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
@@ -66,3 +66,27 @@ int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const v
66 (void)buf; 66 (void)buf;
67 return 0; 67 return 0;
68} 68}
69
70static int jz_device_ready(void)
71{
72 int ready, wait = 10;
73 while (wait--);
74 ready = __gpio_get_pin(32*2+30);
75 return ready;
76}
77
78int ata_init(void)
79{
80 /*
81 * EMC setup
82 */
83
84 /* Set NFE bit */
85 REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
86
87 /* Read/Write timings */
88 REG_EMC_SMCR1 = (EMC_SMCR_BL_4 | EMC_SMCR_BW_8BIT | 4 << EMC_SMCR_TAS_BIT
89 | 4 << EMC_SMCR_TAH_BIT | 4 << EMC_SMCR_TBP_BIT | 4 << EMC_SMCR_TAW_BIT
90 | 4 << EMC_SMCR_STRV_BIT);
91 return 0;
92}
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
index 429178aeee..907351c64e 100644
--- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -49,6 +49,13 @@ bool lcd_enabled(void)
49 return _lcd_on; 49 return _lcd_on;
50} 50}
51 51
52void lcd_copy_buffer_rect(fb_data* dest, fb_data* src, int width, int height)
53{
54 int i;
55 for(i=0; i<width*height; i++)
56 *dest++ = *src++;
57}
58
52#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)]) 59#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)])
53#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000) 60#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000)
54 61
@@ -57,11 +64,12 @@ void lcd_update_rect(int x, int y, int width, int height)
57{ 64{
58 /* HACKY... */ 65 /* HACKY... */
59 x=0; y=0; width=400; height=240; 66 x=0; y=0; width=400; height=240;
67
60 lcd_set_target(x, y, width-1, height-1); 68 lcd_set_target(x, y, width-1, height-1);
61 69
62 REG_DMAC_DCCSR(0) = 0; 70 REG_DMAC_DCCSR(0) = 0;
63 REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ 71 REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
64 REG_DMAC_DSAR(0) = LCDADDR(x,y) & 0x1FFFFFFF; 72 REG_DMAC_DSAR(0) = LCDADDR(x, y) & 0x1FFFFFFF;
65#if 0 73#if 0
66 REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO); 74 REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO);
67#else 75#else
@@ -73,13 +81,12 @@ void lcd_update_rect(int x, int y, int width, int height)
73 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ 81 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
74 REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ 82 REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
75 83
76 jz_flush_icache(); 84 jz_flush_dcache();
77 85
78 REG_DMAC_DMACR = DMAC_DMACR_DMAE; 86 REG_DMAC_DMACR = DMAC_DMACR_DMAE;
79 87
80 while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) ) 88 while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
81 asm("nop"); 89 asm("nop");
82
83 //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT; 90 //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT;
84} 91}
85 92
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
index e99bc178f1..33809bb50f 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
@@ -69,7 +69,11 @@ static void _display_init(void)
69 69
70 SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100); 70 SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100);
71 SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100); 71 SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100);
72 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID)); 72#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
73 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM));
74#else
75 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM | ENTRY_MODE_HWM));
76#endif
73 SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503); 77 SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503);
74 SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1); 78 SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1);
75 SLCD_SEND_COMMAND(REG_LPCTRL, 0x10); 79 SLCD_SEND_COMMAND(REG_LPCTRL, 0x10);
@@ -193,15 +197,12 @@ static void _set_lcd_clock(void)
193 int pll_div; 197 int pll_div;
194 198
195 __cpm_stop_lcd(); 199 __cpm_stop_lcd();
196 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 200 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */
197 pll_div = pll_div ? 1 : 2 ; 201 pll_div = pll_div ? 1 : 2 ;
198 val = ( __cpm_get_pllout()/pll_div ) / 336000000; 202 val = ( __cpm_get_pllout()/pll_div ) / 336000000;
199 val--; 203 val--;
200 if ( val > 0x1ff ) 204 if ( val > 0x1ff )
201 { 205 val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */
202 //printf("CPM_LPCDR too large, set it to 0x1ff\n");
203 val = 0x1ff;
204 }
205 __cpm_set_pixdiv(val); 206 __cpm_set_pixdiv(val);
206 __cpm_start_lcd(); 207 __cpm_start_lcd();
207} 208}
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index ee50520243..2dca4619c0 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -26,7 +26,7 @@
26 26
27void intr_handler(void) 27void intr_handler(void)
28{ 28{
29 _printf("Interrupt!"); 29 //printf("Interrupt!");
30 return; 30 return;
31} 31}
32 32