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Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
index 429178aeee..907351c64e 100644
--- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -49,6 +49,13 @@ bool lcd_enabled(void)
49 return _lcd_on; 49 return _lcd_on;
50} 50}
51 51
52void lcd_copy_buffer_rect(fb_data* dest, fb_data* src, int width, int height)
53{
54 int i;
55 for(i=0; i<width*height; i++)
56 *dest++ = *src++;
57}
58
52#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)]) 59#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)])
53#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000) 60#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000)
54 61
@@ -57,11 +64,12 @@ void lcd_update_rect(int x, int y, int width, int height)
57{ 64{
58 /* HACKY... */ 65 /* HACKY... */
59 x=0; y=0; width=400; height=240; 66 x=0; y=0; width=400; height=240;
67
60 lcd_set_target(x, y, width-1, height-1); 68 lcd_set_target(x, y, width-1, height-1);
61 69
62 REG_DMAC_DCCSR(0) = 0; 70 REG_DMAC_DCCSR(0) = 0;
63 REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ 71 REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
64 REG_DMAC_DSAR(0) = LCDADDR(x,y) & 0x1FFFFFFF; 72 REG_DMAC_DSAR(0) = LCDADDR(x, y) & 0x1FFFFFFF;
65#if 0 73#if 0
66 REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO); 74 REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO);
67#else 75#else
@@ -73,13 +81,12 @@ void lcd_update_rect(int x, int y, int width, int height)
73 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ 81 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
74 REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ 82 REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
75 83
76 jz_flush_icache(); 84 jz_flush_dcache();
77 85
78 REG_DMAC_DMACR = DMAC_DMACR_DMAE; 86 REG_DMAC_DMACR = DMAC_DMACR_DMAE;
79 87
80 while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) ) 88 while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
81 asm("nop"); 89 asm("nop");
82
83 //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT; 90 //REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT;
84} 91}
85 92