summaryrefslogtreecommitdiff
path: root/firmware/target/coldfire
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/coldfire')
-rw-r--r--firmware/target/coldfire/iaudio/m3/adc-m3.c8
-rw-r--r--firmware/target/coldfire/iriver/h100/lcd-as-h100.S2
-rw-r--r--firmware/target/coldfire/iriver/lcd-remote-iriver.c2
3 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c
index 5997f2419a..9f5bf04a64 100644
--- a/firmware/target/coldfire/iaudio/m3/adc-m3.c
+++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c
@@ -25,8 +25,8 @@
25 25
26#define ADC_I2C_ADDR 0xa0 26#define ADC_I2C_ADDR 0xa0
27 27
28/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires 28/* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires
29 * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read 29 * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read
30 * transfer each tick, and handle it via an ISR. At 11MHz, one transfer 30 * transfer each tick, and handle it via an ISR. At 11MHz, one transfer
31 * takes too long to be started every tick, but it seems we have to live 31 * takes too long to be started every tick, but it seems we have to live
32 * with that. */ 32 * with that. */
@@ -92,7 +92,7 @@ unsigned short adc_read(int channel)
92 92
93void adc_init(void) 93void adc_init(void)
94{ 94{
95 MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ 95 MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */
96 MBCR2 = IEN; /* Enable interface */ 96 MBCR2 = IEN; /* Enable interface */
97 MBSR2 = 0; /* Clear flags */ 97 MBSR2 = 0; /* Clear flags */
98 MBCR2 = (IEN|IIEN); /* Enable interrupts */ 98 MBCR2 = (IEN|IIEN); /* Enable interrupts */
@@ -105,7 +105,7 @@ void adc_init(void)
105 sleep(1); /* Ensure valid readings when adc_init returns */ 105 sleep(1); /* Ensure valid readings when adc_init returns */
106} 106}
107 107
108/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C 108/* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C
109 * implementation. If a transfer is stopped prematurely, it often locks up 109 * implementation. If a transfer is stopped prematurely, it often locks up
110 * and doesn't react anymore until the unit is power cycled. */ 110 * and doesn't react anymore until the unit is power cycled. */
111 111
diff --git a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
index 8e483d23ad..4cb6d13adf 100644
--- a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
+++ b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
@@ -8,7 +8,7 @@
8 * $Id$ 8 * $Id$
9 * 9 *
10 * Copyright (C) 2004 by Jens Arnold 10 * Copyright (C) 2004 by Jens Arnold
11 * Based on the work of Alan Korr and Jörg Hohensohn 11 * Based on the work of Alan Korr and Jörg Hohensohn
12 * 12 *
13 * All files in this archive are subject to the GNU General Public License. 13 * All files in this archive are subject to the GNU General Public License.
14 * See the file COPYING in the source tree root for full license agreement. 14 * See the file COPYING in the source tree root for full license agreement.
diff --git a/firmware/target/coldfire/iriver/lcd-remote-iriver.c b/firmware/target/coldfire/iriver/lcd-remote-iriver.c
index 85ba0fef7a..83b7a022e5 100644
--- a/firmware/target/coldfire/iriver/lcd-remote-iriver.c
+++ b/firmware/target/coldfire/iriver/lcd-remote-iriver.c
@@ -7,7 +7,7 @@
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id$ 8 * $Id$
9 * 9 *
10 * Copyright (C) 2005 by Richard S. La Charité III 10 * Copyright (C) 2005 by Richard S. La Charité III
11 * 11 *
12 * All files in this archive are subject to the GNU General Public License. 12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement. 13 * See the file COPYING in the source tree root for full license agreement.