diff options
Diffstat (limited to 'firmware/target/coldfire/mpio/hd200')
-rw-r--r-- | firmware/target/coldfire/mpio/hd200/adc-hd200.c | 30 | ||||
-rw-r--r-- | firmware/target/coldfire/mpio/hd200/system-hd200.c | 13 |
2 files changed, 21 insertions, 22 deletions
diff --git a/firmware/target/coldfire/mpio/hd200/adc-hd200.c b/firmware/target/coldfire/mpio/hd200/adc-hd200.c index 8a64e00443..3e162a2251 100644 --- a/firmware/target/coldfire/mpio/hd200/adc-hd200.c +++ b/firmware/target/coldfire/mpio/hd200/adc-hd200.c | |||
@@ -29,18 +29,16 @@ | |||
29 | volatile unsigned short adc_data[NUM_ADC_CHANNELS] IBSS_ATTR; | 29 | volatile unsigned short adc_data[NUM_ADC_CHANNELS] IBSS_ATTR; |
30 | 30 | ||
31 | /* Reading takes 4096 adclk ticks | 31 | /* Reading takes 4096 adclk ticks |
32 | * We do read one channel at once | 32 | * 1) tick task is created that enables ADC interrupt |
33 | * | 33 | * 2) On interrupt single channel is readed and |
34 | * state FCPU Fbus Fadc bus/Fadc Fchannelread | 34 | * ADC is prepared for next channel |
35 | * default 11.2896 MHz 5.6448 MHz 5.6448 MHz 2 172.2656 Hz | 35 | * 3) When all 4 channels are scanned ADC interrupt is disabled |
36 | * normal 45.1584 MHz 22.5792 MHz 2.8224 MHz 8 172.2656 Hz | ||
37 | * max 124.1856 MHz 62.0928 MHz 1.9404 MHz 32 118.4326 Hz | ||
38 | */ | 36 | */ |
39 | 37 | ||
40 | void ADC(void) __attribute__ ((interrupt_handler,section(".icode"))); | 38 | void ADC(void) __attribute__ ((interrupt_handler,section(".icode"))); |
41 | void ADC(void) | 39 | void ADC(void) |
42 | { | 40 | { |
43 | static unsigned int channel IBSS_ATTR; | 41 | static unsigned char channel IBSS_ATTR; |
44 | /* read current value */ | 42 | /* read current value */ |
45 | adc_data[(channel & 0x03)] = ADVALUE; | 43 | adc_data[(channel & 0x03)] = ADVALUE; |
46 | 44 | ||
@@ -55,7 +53,10 @@ void ADC(void) | |||
55 | 53 | ||
56 | and_l(~(3<<24),&ADCONFIG); | 54 | and_l(~(3<<24),&ADCONFIG); |
57 | or_l( (((channel & 0x03) << 8 )|(1<<7))<<16, &ADCONFIG); | 55 | or_l( (((channel & 0x03) << 8 )|(1<<7))<<16, &ADCONFIG); |
58 | 56 | ||
57 | if ( (channel & 0x03) == 0 ) | ||
58 | /* disable ADC interrupt */ | ||
59 | and_l((~(1<<6))<<16,&ADCONFIG); | ||
59 | } | 60 | } |
60 | 61 | ||
61 | unsigned short adc_scan(int channel) | 62 | unsigned short adc_scan(int channel) |
@@ -64,6 +65,12 @@ unsigned short adc_scan(int channel) | |||
64 | return adc_data[(channel&0x03)]; | 65 | return adc_data[(channel&0x03)]; |
65 | } | 66 | } |
66 | 67 | ||
68 | void adc_tick(void) | ||
69 | { | ||
70 | /* enable ADC interrupt */ | ||
71 | or_l( ((1<<6))<<16, &ADCONFIG); | ||
72 | } | ||
73 | |||
67 | void adc_init(void) | 74 | void adc_init(void) |
68 | { | 75 | { |
69 | /* GPIO38 GPIO39 */ | 76 | /* GPIO38 GPIO39 */ |
@@ -72,13 +79,16 @@ void adc_init(void) | |||
72 | /* ADOUT_SEL = 01 | 79 | /* ADOUT_SEL = 01 |
73 | * SOURCE SELECT = 000 | 80 | * SOURCE SELECT = 000 |
74 | * CLEAR INTERRUPT FLAG | 81 | * CLEAR INTERRUPT FLAG |
75 | * ENABLE INTERRUPT = 1 | 82 | * ENABLE INTERRUPT = 0 |
76 | * ADOUT_DRIVE = 00 | 83 | * ADOUT_DRIVE = 00 |
77 | * ADCLK_SEL = 011 (busclk/8) | 84 | * ADCLK_SEL = 011 (busclk/8) |
78 | */ | 85 | */ |
79 | 86 | ||
80 | ADCONFIG = (1<<10)|(1<<7)|(1<<6)|(1<<1)|(1<<0); | 87 | ADCONFIG = (1<<10)|(1<<7)|(1<<1)|(1<<0); |
81 | 88 | ||
82 | /* ADC interrupt level 4.0 */ | 89 | /* ADC interrupt level 4.0 */ |
83 | or_l((4<<28), &INTPRI8); | 90 | or_l((4<<28), &INTPRI8); |
91 | |||
92 | /* create tick task which enables ADC interrupt */ | ||
93 | tick_add_task(adc_tick); | ||
84 | } | 94 | } |
diff --git a/firmware/target/coldfire/mpio/hd200/system-hd200.c b/firmware/target/coldfire/mpio/hd200/system-hd200.c index a11499b2f1..27ff0a1966 100644 --- a/firmware/target/coldfire/mpio/hd200/system-hd200.c +++ b/firmware/target/coldfire/mpio/hd200/system-hd200.c | |||
@@ -77,10 +77,6 @@ void cf_set_cpu_frequency(long frequency) | |||
77 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(3<<10); | 77 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(3<<10); |
78 | /* BUFEN2 enable on /CS2 | CS2Post 1 clock| CS2Pre 3 clocks*/ | 78 | /* BUFEN2 enable on /CS2 | CS2Post 1 clock| CS2Pre 3 clocks*/ |
79 | IDECONFIG2 = (1<<18)|(1<<16)|(1<<8)|(1<<0); /* TA /CS2 enable + CS2wait */ | 79 | IDECONFIG2 = (1<<18)|(1<<16)|(1<<8)|(1<<0); /* TA /CS2 enable + CS2wait */ |
80 | |||
81 | and_l(~(0x07<<16), &ADCONFIG); | ||
82 | or_l(((1<<7)|(1<<2)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/32 */ | ||
83 | |||
84 | break; | 80 | break; |
85 | 81 | ||
86 | case CPUFREQ_NORMAL: | 82 | case CPUFREQ_NORMAL: |
@@ -98,11 +94,8 @@ void cf_set_cpu_frequency(long frequency) | |||
98 | cpu_frequency = CPUFREQ_NORMAL; | 94 | cpu_frequency = CPUFREQ_NORMAL; |
99 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); | 95 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); |
100 | IDECONFIG2 = (1<<18)|(1<<16); | 96 | IDECONFIG2 = (1<<18)|(1<<16); |
101 | |||
102 | and_l(~(0x07<<16), &ADCONFIG); | ||
103 | or_l(((1<<7)|(1<<1)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/8 */ | ||
104 | |||
105 | break; | 97 | break; |
98 | |||
106 | default: | 99 | default: |
107 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | 100 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; |
108 | /* Refresh timer for bypass frequency */ | 101 | /* Refresh timer for bypass frequency */ |
@@ -116,10 +109,6 @@ void cf_set_cpu_frequency(long frequency) | |||
116 | cpu_frequency = CPUFREQ_DEFAULT; | 109 | cpu_frequency = CPUFREQ_DEFAULT; |
117 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); | 110 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); |
118 | IDECONFIG2 = (1<<18)|(1<<16); | 111 | IDECONFIG2 = (1<<18)|(1<<16); |
119 | |||
120 | and_l(~(0x07<<16), &ADCONFIG); | ||
121 | or_l(((1<<7)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/2 */ | ||
122 | |||
123 | break; | 112 | break; |
124 | } | 113 | } |
125 | } | 114 | } |