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-rw-r--r--firmware/target/arm/imx233/i2c-imx233.c186
-rw-r--r--firmware/target/arm/imx233/i2c-imx233.h137
2 files changed, 323 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/i2c-imx233.c b/firmware/target/arm/imx233/i2c-imx233.c
new file mode 100644
index 0000000000..9d29605bce
--- /dev/null
+++ b/firmware/target/arm/imx233/i2c-imx233.c
@@ -0,0 +1,186 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2011 by amaury Pouly
11 *
12 * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
13 * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21 * KIND, either express or implied.
22 *
23 ****************************************************************************/
24#include "config.h"
25#include "system.h"
26#include "kernel.h"
27#include "dma-imx233.h"
28#include "i2c-imx233.h"
29#include "pinctrl-imx233.h"
30
31/* Used for DMA */
32struct i2c_dma_command_t
33{
34 struct apb_dma_command_t dma;
35 /* PIO words */
36 uint32_t ctrl0;
37};
38
39#define I2C_NR_STAGES 4
40/* Current transfer */
41static int i2c_nr_stages;
42static struct i2c_dma_command_t i2c_stage[I2C_NR_STAGES];
43static struct mutex i2c_mutex;
44static struct semaphore i2c_sema;
45
46void INT_I2C_DMA(void)
47{
48 /* reset dma channel on error */
49 if(imx233_dma_is_channel_error_irq(APB_I2C))
50 imx233_dma_reset_channel(APB_I2C);
51 /* clear irq flags */
52 imx233_dma_clear_channel_interrupt(APB_I2C);
53 semaphore_release(&i2c_sema);
54}
55
56void imx233_i2c_init(void)
57{
58 __REG_SET(HW_I2C_CTRL0) = __BLOCK_SFTRST | __BLOCK_CLKGATE;
59 /* setup pins (must be done when shutdown) */
60 imx233_set_pin_function(0, 30, PINCTRL_FUNCTION_MAIN);
61 imx233_set_pin_function(0, 31, PINCTRL_FUNCTION_MAIN);
62 /* clear softreset */
63 __REG_CLR(HW_I2C_CTRL0) = __BLOCK_SFTRST | __BLOCK_CLKGATE;
64 /* Errata:
65 * When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA
66 * line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is
67 * generated.
68 * HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for
69 * this issue.
70 */
71 __REG_SET(HW_I2C_CTRL1) = HW_I2C_CTRL1__ACK_MODE;
72 __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
73 /* Fast-mode @ 400K */
74 HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */
75 HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */
76 HW_I2C_TIMING2 = 0x0015000D;
77
78 mutex_init(&i2c_mutex);
79 semaphore_init(&i2c_sema, 1, 0);
80}
81
82void imx233_i2c_begin(void)
83{
84 mutex_lock(&i2c_mutex);
85 /* wakeup */
86 __REG_CLR(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
87 i2c_nr_stages = 0;
88}
89
90enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop)
91{
92 if(i2c_nr_stages == I2C_NR_STAGES)
93 return I2C_ERROR;
94 if(i2c_nr_stages > 0)
95 {
96 i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma;
97 i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__CHAIN;
98 if(!start)
99 i2c_stage[i2c_nr_stages - 1].ctrl0 |= HW_I2C_CTRL0__RETAIN_CLOCK;
100 }
101 i2c_stage[i2c_nr_stages].dma.buffer = buffer;
102 i2c_stage[i2c_nr_stages].dma.next = NULL;
103 i2c_stage[i2c_nr_stages].dma.cmd =
104 (transmit ? HW_APB_CHx_CMD__COMMAND__READ : HW_APB_CHx_CMD__COMMAND__WRITE) |
105 HW_APB_CHx_CMD__WAIT4ENDCMD |
106 1 << HW_APB_CHx_CMD__CMDWORDS_BP |
107 size << HW_APB_CHx_CMD__XFER_COUNT_BP;
108 /* assume that any read is final (send nak on last) */
109 i2c_stage[i2c_nr_stages].ctrl0 = size |
110 (transmit ? HW_I2C_CTRL0__TRANSMIT : HW_I2C_CTRL0__SEND_NAK_ON_LAST) |
111 (start ? HW_I2C_CTRL0__PRE_SEND_START : 0) |
112 (stop ? HW_I2C_CTRL0__POST_SEND_STOP : 0) |
113 HW_I2C_CTRL0__MASTER_MODE;
114 i2c_nr_stages++;
115 return I2C_SUCCESS;
116}
117
118enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
119{
120 if(i2c_nr_stages == 0)
121 return I2C_ERROR;
122 i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT;
123
124 __REG_CLR(HW_I2C_CTRL1) = HW_I2C_CTRL1__ALL_IRQ;
125 imx233_enable_interrupt(INT_SRC_I2C_DMA, true);
126 imx233_dma_enable_channel_interrupt(APB_I2C, true);
127 imx233_dma_reset_channel(APB_I2C);
128 imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma);
129
130 enum imx233_i2c_error_t ret ;
131 if(semaphore_wait(&i2c_sema, timeout) == OBJ_WAIT_TIMEDOUT)
132 {
133 imx233_dma_reset_channel(APB_I2C);
134 ret = I2C_TIMEOUT;
135 }
136 else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__MASTER_LOSS_IRQ)
137 ret = I2C_MASTER_LOSS;
138 else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ)
139 ret= I2C_NO_SLAVE_ACK;
140 else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__EARLY_TERM_IRQ)
141 ret = I2C_SLAVE_NAK;
142 else
143 ret = I2C_SUCCESS;
144 /* sleep */
145 __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
146 mutex_unlock(&i2c_mutex);
147 return ret;
148}
149
150int i2c_write(int device, const unsigned char* buf, int count)
151{
152 uint8_t addr = device;
153 imx233_i2c_begin();
154 imx233_i2c_add(true, true, &addr, 1, false); /* start + addr */
155 imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
156 return imx233_i2c_end(TIMEOUT_BLOCK);
157}
158
159int i2c_read(int device, unsigned char* buf, int count)
160{
161 uint8_t addr = device | 1;
162 imx233_i2c_begin();
163 imx233_i2c_add(true, true, &addr, 1, false); /* start + addr */
164 imx233_i2c_add(false, false, buf, count, true); /* data + stop */
165 return imx233_i2c_end(TIMEOUT_BLOCK);
166}
167
168int i2c_readmem(int device, int address, unsigned char* buf, int count)
169{
170 uint8_t start[2] = {device, address};
171 uint8_t addr_rd = device | 1;
172 imx233_i2c_begin();
173 imx233_i2c_add(true, true, start, 2, false); /* start + addr + addr */
174 imx233_i2c_add(true, true, &addr_rd, 1, false); /* start + addr */
175 imx233_i2c_add(false, false, buf, count, true); /* data + stop */
176 return imx233_i2c_end(TIMEOUT_BLOCK);
177}
178
179int i2c_writemem(int device, int address, const unsigned char* buf, int count)
180{
181 uint8_t start[2] = {device, address};
182 imx233_i2c_begin();
183 imx233_i2c_add(true, true, start, 2, false); /* start + addr + addr */
184 imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
185 return imx233_i2c_end(TIMEOUT_BLOCK);
186}
diff --git a/firmware/target/arm/imx233/i2c-imx233.h b/firmware/target/arm/imx233/i2c-imx233.h
new file mode 100644
index 0000000000..5ee22efd2a
--- /dev/null
+++ b/firmware/target/arm/imx233/i2c-imx233.h
@@ -0,0 +1,137 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2011 by amaury Pouly
11 *
12 * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
13 * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21 * KIND, either express or implied.
22 *
23 ****************************************************************************/
24#ifndef __I2C_IMX233_H__
25#define __I2C_IMX233_H__
26
27#include "cpu.h"
28#include "system.h"
29#include "system-target.h"
30#include "i2c.h"
31
32#define HW_I2C_BASE 0x80058000
33
34#define HW_I2C_CTRL0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x0))
35#define HW_I2C_CTRL0__XFER_COUNT_BM 0xffff
36#define HW_I2C_CTRL0__TRANSMIT (1 << 16)
37#define HW_I2C_CTRL0__MASTER_MODE (1 << 17)
38#define HW_I2C_CTRL0__SLAVE_ADDRESS_ENABLE (1 << 18)
39#define HW_I2C_CTRL0__PRE_SEND_START (1 << 19)
40#define HW_I2C_CTRL0__POST_SEND_STOP (1 << 20)
41#define HW_I2C_CTRL0__RETAIN_CLOCK (1 << 21)
42#define HW_I2C_CTRL0__CLOCK_HELD (1 << 22)
43#define HW_I2C_CTRL0__PIO_MODE (1 << 24)
44#define HW_I2C_CTRL0__SEND_NAK_ON_LAST (1 << 25)
45#define HW_I2C_CTRL0__ACKNOWLEDGE (1 << 26)
46#define HW_I2C_CTRL0__RUN (1 << 29)
47
48#define HW_I2C_TIMING0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x10))
49#define HW_I2C_TIMING0__RECV_COUNT_BM 0x3ff
50#define HW_I2C_TIMING0__HIGH_COUNT_BM (0x3ff << 16)
51#define HW_I2C_TIMING0__HIGH_COUNT_BP 16
52
53#define HW_I2C_TIMING1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x20))
54#define HW_I2C_TIMING1__XMIT_COUNT_BM 0x3ff
55#define HW_I2C_TIMING1__LOW_COUNT_BM (0x3ff << 16)
56#define HW_I2C_TIMING1__LOW_COUNT_BP 16
57
58#define HW_I2C_TIMING2 (*(volatile uint32_t *)(HW_I2C_BASE + 0x30))
59#define HW_I2C_TIMING2__LEADIN_COUNT_BM 0x3ff
60#define HW_I2C_TIMING2__BUS_FREE_BM (0x3ff << 16)
61#define HW_I2C_TIMING2__BUS_FREE_BP 16
62
63#define HW_I2C_CTRL1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x40))
64#define HW_I2C_CTRL1__SLAVE_IRQ (1 << 0)
65#define HW_I2C_CTRL1__SLAVE_STOP_IRQ (1 << 1)
66#define HW_I2C_CTRL1__MASTER_LOSS_IRQ (1 << 2)
67#define HW_I2C_CTRL1__EARLY_TERM_IRQ (1 << 3)
68#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ (1 << 4)
69#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ (1 << 5)
70#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ (1 << 6)
71#define HW_I2C_CTRL1__BUS_FREE_IRQ (1 << 7)
72#define HW_I2C_CTRL1__SLAVE_IRQ_EN (1 << 8)
73#define HW_I2C_CTRL1__SLAVE_STOP_IRQ_EN (1 << 9)
74#define HW_I2C_CTRL1__MASTER_LOSS_IRQ_EN (1 << 10)
75#define HW_I2C_CTRL1__EARLY_TERM_IRQ_EN (1 << 11)
76#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
77#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ_EN (1 << 13)
78#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ_EN (1 << 14)
79#define HW_I2C_CTRL1__BUS_FREE_IRQ_EN (1 << 15)
80#define HW_I2C_CTRL1__BCAST_SLAVE_EN (1 << 24)
81#define HW_I2C_CTRL1__FORCE_CLK_IDLE (1 << 25)
82#define HW_I2C_CTRL1__FORCE_DATA_IDLE (1 << 26)
83#define HW_I2C_CTRL1__ACK_MODE (1 << 27)
84#define HW_I2C_CTRL1__CLR_GOT_A_NAK (1 << 28)
85#define HW_I2C_CTRL1__ALL_IRQ 0xff
86#define HW_I2C_CTRL1__ALL_IRQ_EN 0xff00
87
88#define HW_I2C_STAT (*(volatile uint32_t *)(HW_I2C_BASE + 0x50))
89#define HW_I2C_STAT__SLAVE_IRQ_SUMMARY (1 << 0)
90#define HW_I2C_STAT__SLAVE_STOP_IRQ_SUMMARY (1 << 1)
91#define HW_I2C_STAT__MASTER_LOSS_IRQ_SUMMARY (1 << 2)
92#define HW_I2C_STAT__EARLY_TERM_IRQ_SUMMARY (1 << 3)
93#define HW_I2C_STAT__OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
94#define HW_I2C_STAT__NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
95#define HW_I2C_STAT__DATA_ENGINE_COMPLT_IRQ_SUMMARY (1 << 6)
96#define HW_I2C_STAT__BUS_FREE_IRQ_SUMMARY (1 << 7)
97#define HW_I2C_STAT__SLAVE_BUSY (1 << 8)
98#define HW_I2C_STAT__DATA_ENGINE_BUSY (1 << 9)
99#define HW_I2C_STAT__CLK_GEN_BUSY (1 << 10)
100#define HW_I2C_STAT__BUS_BUSY (1 << 11)
101#define HW_I2C_STAT__DATA_ENGINE_DMA_WAIT (1 << 12)
102#define HW_I2C_STAT__SLAVE_SEARCHING (1 << 13)
103#define HW_I2C_STAT__SLAVE_FOUND (1 << 14)
104#define HW_I2C_STAT__SLAVE_ADDR_EQ_ZERO (1 << 15)
105#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BM (0xff << 16)
106#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BP 16
107#define HW_I2C_STAT__GOT_A_NAK (1 << 28)
108#define HW_I2C_STAT__ANY_ENABLED_IRQ (1 << 29)
109#define HW_I2C_STAT__MASTER_PRESENT (1 << 31)
110
111#define HW_I2C_DATA (*(volatile uint32_t *)(HW_I2C_BASE + 0x60))
112
113#define HW_I2C_DEBUG0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x70))
114
115#define HW_I2C_DEBUG1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x80))
116
117#define HW_I2C_VERSION (*(volatile uint32_t *)(HW_I2C_BASE + 0x90))
118
119enum imx233_i2c_error_t
120{
121 I2C_SUCCESS = 0,
122 I2C_ERROR = -1,
123 I2C_TIMEOUT = -2,
124 I2C_MASTER_LOSS = -3,
125 I2C_NO_SLAVE_ACK = -4,
126 I2C_SLAVE_NAK = -5
127};
128
129void imx233_i2c_init(void);
130/* start building a transfer, will acquire an exclusive lock */
131void imx233_i2c_begin(void);
132/* add stage */
133enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop);
134/* end building a transfer and start the transfer */
135enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout);
136
137#endif // __DMA_IMX233_H__
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-30 23:42:22 +0000