diff options
Diffstat (limited to 'firmware/target/arm/imx233/i2c-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/i2c-imx233.h | 137 |
1 files changed, 137 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/i2c-imx233.h b/firmware/target/arm/imx233/i2c-imx233.h new file mode 100644 index 0000000000..5ee22efd2a --- /dev/null +++ b/firmware/target/arm/imx233/i2c-imx233.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __I2C_IMX233_H__ | ||
25 | #define __I2C_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | #include "i2c.h" | ||
31 | |||
32 | #define HW_I2C_BASE 0x80058000 | ||
33 | |||
34 | #define HW_I2C_CTRL0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x0)) | ||
35 | #define HW_I2C_CTRL0__XFER_COUNT_BM 0xffff | ||
36 | #define HW_I2C_CTRL0__TRANSMIT (1 << 16) | ||
37 | #define HW_I2C_CTRL0__MASTER_MODE (1 << 17) | ||
38 | #define HW_I2C_CTRL0__SLAVE_ADDRESS_ENABLE (1 << 18) | ||
39 | #define HW_I2C_CTRL0__PRE_SEND_START (1 << 19) | ||
40 | #define HW_I2C_CTRL0__POST_SEND_STOP (1 << 20) | ||
41 | #define HW_I2C_CTRL0__RETAIN_CLOCK (1 << 21) | ||
42 | #define HW_I2C_CTRL0__CLOCK_HELD (1 << 22) | ||
43 | #define HW_I2C_CTRL0__PIO_MODE (1 << 24) | ||
44 | #define HW_I2C_CTRL0__SEND_NAK_ON_LAST (1 << 25) | ||
45 | #define HW_I2C_CTRL0__ACKNOWLEDGE (1 << 26) | ||
46 | #define HW_I2C_CTRL0__RUN (1 << 29) | ||
47 | |||
48 | #define HW_I2C_TIMING0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x10)) | ||
49 | #define HW_I2C_TIMING0__RECV_COUNT_BM 0x3ff | ||
50 | #define HW_I2C_TIMING0__HIGH_COUNT_BM (0x3ff << 16) | ||
51 | #define HW_I2C_TIMING0__HIGH_COUNT_BP 16 | ||
52 | |||
53 | #define HW_I2C_TIMING1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x20)) | ||
54 | #define HW_I2C_TIMING1__XMIT_COUNT_BM 0x3ff | ||
55 | #define HW_I2C_TIMING1__LOW_COUNT_BM (0x3ff << 16) | ||
56 | #define HW_I2C_TIMING1__LOW_COUNT_BP 16 | ||
57 | |||
58 | #define HW_I2C_TIMING2 (*(volatile uint32_t *)(HW_I2C_BASE + 0x30)) | ||
59 | #define HW_I2C_TIMING2__LEADIN_COUNT_BM 0x3ff | ||
60 | #define HW_I2C_TIMING2__BUS_FREE_BM (0x3ff << 16) | ||
61 | #define HW_I2C_TIMING2__BUS_FREE_BP 16 | ||
62 | |||
63 | #define HW_I2C_CTRL1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x40)) | ||
64 | #define HW_I2C_CTRL1__SLAVE_IRQ (1 << 0) | ||
65 | #define HW_I2C_CTRL1__SLAVE_STOP_IRQ (1 << 1) | ||
66 | #define HW_I2C_CTRL1__MASTER_LOSS_IRQ (1 << 2) | ||
67 | #define HW_I2C_CTRL1__EARLY_TERM_IRQ (1 << 3) | ||
68 | #define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ (1 << 4) | ||
69 | #define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ (1 << 5) | ||
70 | #define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ (1 << 6) | ||
71 | #define HW_I2C_CTRL1__BUS_FREE_IRQ (1 << 7) | ||
72 | #define HW_I2C_CTRL1__SLAVE_IRQ_EN (1 << 8) | ||
73 | #define HW_I2C_CTRL1__SLAVE_STOP_IRQ_EN (1 << 9) | ||
74 | #define HW_I2C_CTRL1__MASTER_LOSS_IRQ_EN (1 << 10) | ||
75 | #define HW_I2C_CTRL1__EARLY_TERM_IRQ_EN (1 << 11) | ||
76 | #define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) | ||
77 | #define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ_EN (1 << 13) | ||
78 | #define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ_EN (1 << 14) | ||
79 | #define HW_I2C_CTRL1__BUS_FREE_IRQ_EN (1 << 15) | ||
80 | #define HW_I2C_CTRL1__BCAST_SLAVE_EN (1 << 24) | ||
81 | #define HW_I2C_CTRL1__FORCE_CLK_IDLE (1 << 25) | ||
82 | #define HW_I2C_CTRL1__FORCE_DATA_IDLE (1 << 26) | ||
83 | #define HW_I2C_CTRL1__ACK_MODE (1 << 27) | ||
84 | #define HW_I2C_CTRL1__CLR_GOT_A_NAK (1 << 28) | ||
85 | #define HW_I2C_CTRL1__ALL_IRQ 0xff | ||
86 | #define HW_I2C_CTRL1__ALL_IRQ_EN 0xff00 | ||
87 | |||
88 | #define HW_I2C_STAT (*(volatile uint32_t *)(HW_I2C_BASE + 0x50)) | ||
89 | #define HW_I2C_STAT__SLAVE_IRQ_SUMMARY (1 << 0) | ||
90 | #define HW_I2C_STAT__SLAVE_STOP_IRQ_SUMMARY (1 << 1) | ||
91 | #define HW_I2C_STAT__MASTER_LOSS_IRQ_SUMMARY (1 << 2) | ||
92 | #define HW_I2C_STAT__EARLY_TERM_IRQ_SUMMARY (1 << 3) | ||
93 | #define HW_I2C_STAT__OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) | ||
94 | #define HW_I2C_STAT__NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) | ||
95 | #define HW_I2C_STAT__DATA_ENGINE_COMPLT_IRQ_SUMMARY (1 << 6) | ||
96 | #define HW_I2C_STAT__BUS_FREE_IRQ_SUMMARY (1 << 7) | ||
97 | #define HW_I2C_STAT__SLAVE_BUSY (1 << 8) | ||
98 | #define HW_I2C_STAT__DATA_ENGINE_BUSY (1 << 9) | ||
99 | #define HW_I2C_STAT__CLK_GEN_BUSY (1 << 10) | ||
100 | #define HW_I2C_STAT__BUS_BUSY (1 << 11) | ||
101 | #define HW_I2C_STAT__DATA_ENGINE_DMA_WAIT (1 << 12) | ||
102 | #define HW_I2C_STAT__SLAVE_SEARCHING (1 << 13) | ||
103 | #define HW_I2C_STAT__SLAVE_FOUND (1 << 14) | ||
104 | #define HW_I2C_STAT__SLAVE_ADDR_EQ_ZERO (1 << 15) | ||
105 | #define HW_I2C_STAT__RCVD_SLAVE_ADDR_BM (0xff << 16) | ||
106 | #define HW_I2C_STAT__RCVD_SLAVE_ADDR_BP 16 | ||
107 | #define HW_I2C_STAT__GOT_A_NAK (1 << 28) | ||
108 | #define HW_I2C_STAT__ANY_ENABLED_IRQ (1 << 29) | ||
109 | #define HW_I2C_STAT__MASTER_PRESENT (1 << 31) | ||
110 | |||
111 | #define HW_I2C_DATA (*(volatile uint32_t *)(HW_I2C_BASE + 0x60)) | ||
112 | |||
113 | #define HW_I2C_DEBUG0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x70)) | ||
114 | |||
115 | #define HW_I2C_DEBUG1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x80)) | ||
116 | |||
117 | #define HW_I2C_VERSION (*(volatile uint32_t *)(HW_I2C_BASE + 0x90)) | ||
118 | |||
119 | enum imx233_i2c_error_t | ||
120 | { | ||
121 | I2C_SUCCESS = 0, | ||
122 | I2C_ERROR = -1, | ||
123 | I2C_TIMEOUT = -2, | ||
124 | I2C_MASTER_LOSS = -3, | ||
125 | I2C_NO_SLAVE_ACK = -4, | ||
126 | I2C_SLAVE_NAK = -5 | ||
127 | }; | ||
128 | |||
129 | void imx233_i2c_init(void); | ||
130 | /* start building a transfer, will acquire an exclusive lock */ | ||
131 | void imx233_i2c_begin(void); | ||
132 | /* add stage */ | ||
133 | enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop); | ||
134 | /* end building a transfer and start the transfer */ | ||
135 | enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout); | ||
136 | |||
137 | #endif // __DMA_IMX233_H__ | ||