diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/mrobe-500')
-rw-r--r-- | firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c index 153b589b61..fb94adae71 100644 --- a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c +++ b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c | |||
@@ -29,14 +29,19 @@ | |||
29 | #include "dsp/ipc.h" | 29 | #include "dsp/ipc.h" |
30 | #include "mmu-arm.h" | 30 | #include "mmu-arm.h" |
31 | 31 | ||
32 | /* These are global to save some latency when pcm_play_dma_get_peak_buffer is | 32 | /* This is global to save some latency when pcm_play_dma_get_peak_buffer is |
33 | * called. | 33 | * called. |
34 | */ | 34 | */ |
35 | static void *start; | 35 | static void *start; |
36 | static size_t size; | ||
37 | 36 | ||
38 | void pcm_postinit(void) | 37 | void pcm_postinit(void) |
39 | { | 38 | { |
39 | /* Configure clock divider */ | ||
40 | tsc2100_writereg(CONTROL_PAGE2, TSPP1_ADDRESS, 0x1120); | ||
41 | tsc2100_writereg(CONTROL_PAGE2, TSAC3_ADDRESS, 0x0800); | ||
42 | tsc2100_writereg(CONTROL_PAGE2, TSCPC_ADDRESS, 0x3B00); | ||
43 | tsc2100_writereg(CONTROL_PAGE2, TSAC1_ADDRESS, 0x0300); | ||
44 | tsc2100_writereg(CONTROL_PAGE2, TSCSC_ADDRESS, 0xC580); | ||
40 | audiohw_postinit(); | 45 | audiohw_postinit(); |
41 | } | 46 | } |
42 | 47 | ||
@@ -50,7 +55,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count) | |||
50 | { | 55 | { |
51 | int cnt = DSP_(_sdem_level); | 56 | int cnt = DSP_(_sdem_level); |
52 | 57 | ||
53 | unsigned long addr = (unsigned long) start +cnt; | 58 | unsigned long addr = (unsigned long) start + cnt; |
54 | 59 | ||
55 | *count = (cnt & 0xFFFFF) >> 1; | 60 | *count = (cnt & 0xFFFFF) >> 1; |
56 | return (void *)((addr + 2) & ~3); | 61 | return (void *)((addr + 2) & ~3); |
@@ -58,16 +63,23 @@ const void * pcm_play_dma_get_peak_buffer(int *count) | |||
58 | 63 | ||
59 | void pcm_play_dma_init(void) | 64 | void pcm_play_dma_init(void) |
60 | { | 65 | { |
61 | IO_INTC_IRQ0 = 1 << 11; | 66 | IO_INTC_IRQ0 = INTR_IRQ0_IMGBUF; |
62 | IO_INTC_EINT0 |= 1 << 11; | 67 | bitset16(&IO_INTC_EINT0, INTR_EINT0_IMGBUF); |
63 | 68 | ||
64 | /* Set this as a FIQ */ | 69 | /* Set this as a FIQ */ |
65 | IO_INTC_FISEL0 |= 1 << 11; | 70 | bitset16(&IO_INTC_FISEL0, INTR_EINT0_IMGBUF); |
66 | 71 | ||
72 | /* Enable the HPIB clock */ | ||
73 | bitset16(&IO_CLK_MOD0, (CLK_MOD0_HPIB | CLK_MOD0_DSP)); | ||
74 | |||
75 | IO_SDRAM_SDDMASEL = 0x24; | ||
76 | |||
67 | IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0; | 77 | IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0; |
68 | 78 | ||
69 | dsp_reset(); | 79 | dsp_reset(); |
70 | dsp_load(dsp_image); | 80 | dsp_load(dsp_image); |
81 | |||
82 | DSP_(_dma0_stopped)=1; | ||
71 | dsp_wake(); | 83 | dsp_wake(); |
72 | } | 84 | } |
73 | 85 | ||
@@ -133,8 +145,9 @@ void DSPHINT(void) __attribute__ ((section(".icode"))); | |||
133 | void DSPHINT(void) | 145 | void DSPHINT(void) |
134 | { | 146 | { |
135 | unsigned int i; | 147 | unsigned int i; |
148 | size_t size; | ||
136 | 149 | ||
137 | IO_INTC_FIQ0 = 1 << 11; | 150 | IO_INTC_FIQ0 = INTR_IRQ0_IMGBUF; |
138 | 151 | ||
139 | switch (dsp_message.msg) | 152 | switch (dsp_message.msg) |
140 | { | 153 | { |