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-rw-r--r--firmware/drivers/audio/tsc2100.c4
-rw-r--r--firmware/export/tsc2100.h18
-rw-r--r--firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c27
3 files changed, 29 insertions, 20 deletions
diff --git a/firmware/drivers/audio/tsc2100.c b/firmware/drivers/audio/tsc2100.c
index cc6a7eed7d..88327767df 100644
--- a/firmware/drivers/audio/tsc2100.c
+++ b/firmware/drivers/audio/tsc2100.c
@@ -117,7 +117,7 @@ void audiohw_close(void)
117void audiohw_set_frequency(int fsel) 117void audiohw_set_frequency(int fsel)
118{ 118{
119 int reg_val; 119 int reg_val;
120 reg_val = tsc2100_readreg(TSAC1_PAGE, TSAC1_ADDRESS); 120 reg_val = tsc2100_readreg(CONTROL_PAGE2, TSAC1_ADDRESS);
121 121
122 reg_val &= ~(0x07<<3); 122 reg_val &= ~(0x07<<3);
123 123
@@ -137,5 +137,5 @@ void audiohw_set_frequency(int fsel)
137 break; 137 break;
138 } 138 }
139 139
140 tsc2100_writereg(TSAC1_PAGE, TSAC1_ADDRESS, reg_val); 140 tsc2100_writereg(CONTROL_PAGE2, TSAC1_ADDRESS, reg_val);
141} 141}
diff --git a/firmware/export/tsc2100.h b/firmware/export/tsc2100.h
index a0be067409..9566c588df 100644
--- a/firmware/export/tsc2100.h
+++ b/firmware/export/tsc2100.h
@@ -91,10 +91,6 @@ void tsc2100_keyclick(void);
91#define VOLUME_MAX 0 91#define VOLUME_MAX 0
92#define VOLUME_MIN -630 92#define VOLUME_MIN -630
93 93
94/* ts audio control 1*/
95#define TSAC1_PAGE 2
96#define TSAC1_ADDRESS 0x00
97
98/* ts audio control 2 */ 94/* ts audio control 2 */
99#define TSAC2_PAGE 2 95#define TSAC2_PAGE 2
100#define TSAC2_ADDRESS 0x04 96#define TSAC2_ADDRESS 0x04
@@ -111,13 +107,13 @@ void tsc2100_keyclick(void);
111#define TSAC2_DASTC (1<<1) 107#define TSAC2_DASTC (1<<1)
112#define TSAC2_ADGAF (1<<0) /* r only */ 108#define TSAC2_ADGAF (1<<0) /* r only */
113 109
114/* ts codec power control */ 110#define CONTROL_PAGE2 2
115#define TSCPC_PAGE 2 111#define TSAC1_ADDRESS 0x00 /* ts audio control 1*/
116#define TSCPC_ADDRESS 0x05 112#define TSCSC_ADDRESS 0x03 /* Codec Sidetone Control */
117 113#define TSCPC_ADDRESS 0x05 /* ts codec power control */
118/* ts audio control 3 */ 114#define TSAC3_ADDRESS 0x06 /* ts audio control 3 */
119#define TSAC3_PAGE 2 115#define TSPP1_ADDRESS 0x1b /* PLL Programability */
120#define TSAC3_ADDRESS 0x06 116#define TSPP2_ADDRESS 0x1c /* PLL Programability */
121 117
122/* ts audio control 4 */ 118/* ts audio control 4 */
123#define TSAC4_PAGE 2 119#define TSAC4_PAGE 2
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c
index 153b589b61..fb94adae71 100644
--- a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c
+++ b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c
@@ -29,14 +29,19 @@
29#include "dsp/ipc.h" 29#include "dsp/ipc.h"
30#include "mmu-arm.h" 30#include "mmu-arm.h"
31 31
32/* These are global to save some latency when pcm_play_dma_get_peak_buffer is 32/* This is global to save some latency when pcm_play_dma_get_peak_buffer is
33 * called. 33 * called.
34 */ 34 */
35static void *start; 35static void *start;
36static size_t size;
37 36
38void pcm_postinit(void) 37void pcm_postinit(void)
39{ 38{
39 /* Configure clock divider */
40 tsc2100_writereg(CONTROL_PAGE2, TSPP1_ADDRESS, 0x1120);
41 tsc2100_writereg(CONTROL_PAGE2, TSAC3_ADDRESS, 0x0800);
42 tsc2100_writereg(CONTROL_PAGE2, TSCPC_ADDRESS, 0x3B00);
43 tsc2100_writereg(CONTROL_PAGE2, TSAC1_ADDRESS, 0x0300);
44 tsc2100_writereg(CONTROL_PAGE2, TSCSC_ADDRESS, 0xC580);
40 audiohw_postinit(); 45 audiohw_postinit();
41} 46}
42 47
@@ -50,7 +55,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
50{ 55{
51 int cnt = DSP_(_sdem_level); 56 int cnt = DSP_(_sdem_level);
52 57
53 unsigned long addr = (unsigned long) start +cnt; 58 unsigned long addr = (unsigned long) start + cnt;
54 59
55 *count = (cnt & 0xFFFFF) >> 1; 60 *count = (cnt & 0xFFFFF) >> 1;
56 return (void *)((addr + 2) & ~3); 61 return (void *)((addr + 2) & ~3);
@@ -58,16 +63,23 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
58 63
59void pcm_play_dma_init(void) 64void pcm_play_dma_init(void)
60{ 65{
61 IO_INTC_IRQ0 = 1 << 11; 66 IO_INTC_IRQ0 = INTR_IRQ0_IMGBUF;
62 IO_INTC_EINT0 |= 1 << 11; 67 bitset16(&IO_INTC_EINT0, INTR_EINT0_IMGBUF);
63 68
64 /* Set this as a FIQ */ 69 /* Set this as a FIQ */
65 IO_INTC_FISEL0 |= 1 << 11; 70 bitset16(&IO_INTC_FISEL0, INTR_EINT0_IMGBUF);
66 71
72 /* Enable the HPIB clock */
73 bitset16(&IO_CLK_MOD0, (CLK_MOD0_HPIB | CLK_MOD0_DSP));
74
75 IO_SDRAM_SDDMASEL = 0x24;
76
67 IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0; 77 IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0;
68 78
69 dsp_reset(); 79 dsp_reset();
70 dsp_load(dsp_image); 80 dsp_load(dsp_image);
81
82 DSP_(_dma0_stopped)=1;
71 dsp_wake(); 83 dsp_wake();
72} 84}
73 85
@@ -133,8 +145,9 @@ void DSPHINT(void) __attribute__ ((section(".icode")));
133void DSPHINT(void) 145void DSPHINT(void)
134{ 146{
135 unsigned int i; 147 unsigned int i;
148 size_t size;
136 149
137 IO_INTC_FIQ0 = 1 << 11; 150 IO_INTC_FIQ0 = INTR_IRQ0_IMGBUF;
138 151
139 switch (dsp_message.msg) 152 switch (dsp_message.msg)
140 { 153 {