diff options
Diffstat (limited to 'firmware/target/arm/imx233')
-rw-r--r-- | firmware/target/arm/imx233/dcp-imx233.c | 198 | ||||
-rw-r--r-- | firmware/target/arm/imx233/dcp-imx233.h | 363 | ||||
-rw-r--r-- | firmware/target/arm/imx233/debug-imx233.c | 49 | ||||
-rw-r--r-- | firmware/target/arm/imx233/kernel-imx233.c | 43 | ||||
-rw-r--r-- | firmware/target/arm/imx233/lradc-imx233.c | 54 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-target.h | 3 |
7 files changed, 662 insertions, 52 deletions
diff --git a/firmware/target/arm/imx233/dcp-imx233.c b/firmware/target/arm/imx233/dcp-imx233.c new file mode 100644 index 0000000000..565dba7691 --- /dev/null +++ b/firmware/target/arm/imx233/dcp-imx233.c | |||
@@ -0,0 +1,198 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #include "config.h" | ||
25 | #include "system.h" | ||
26 | #include "dcp-imx233.h" | ||
27 | #include "string.h" | ||
28 | #include "kernel-imx233.h" | ||
29 | |||
30 | /* The hardware uses 160 bytes of storage to enable context switching */ | ||
31 | static uint8_t dcp_context[160] NOCACHEBSS_ATTR; | ||
32 | /* Channel arbiter */ | ||
33 | static struct channel_arbiter_t channel_arbiter; | ||
34 | /* Channel packets */ | ||
35 | static struct imx233_dcp_packet_t channel_packet[HW_DCP_NUM_CHANNELS]; | ||
36 | /* completion semaphore */ | ||
37 | static struct semaphore channel_sema[HW_DCP_NUM_CHANNELS]; | ||
38 | |||
39 | void INT_DCP(void) | ||
40 | { | ||
41 | /* clear interrupt and wakeup completion handler */ | ||
42 | for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++) | ||
43 | { | ||
44 | if(HW_DCP_STAT & HW_DCP_STAT__IRQ(i)) | ||
45 | { | ||
46 | __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(i); | ||
47 | semaphore_release(&channel_sema[i]); | ||
48 | } | ||
49 | } | ||
50 | } | ||
51 | |||
52 | void imx233_dcp_init(void) | ||
53 | { | ||
54 | /* Reset block */ | ||
55 | imx233_reset_block(&HW_DCP_CTRL); | ||
56 | /* Setup contexte pointer */ | ||
57 | HW_DCP_CONTEXT = (uint32_t)PHYSICAL_ADDR(&dcp_context); | ||
58 | /* Enable context switching and caching */ | ||
59 | __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__ENABLE_CONTEXT_CACHING | | ||
60 | HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING; | ||
61 | /* Check that there are sufficiently many channels */ | ||
62 | if(__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS) != HW_DCP_NUM_CHANNELS) | ||
63 | panicf("DCP has %lu channels but was configured to use %d !", | ||
64 | __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS), HW_DCP_NUM_CHANNELS); | ||
65 | /* Setup channel arbiter to use */ | ||
66 | arbiter_init(&channel_arbiter, HW_DCP_NUM_CHANNELS); | ||
67 | /* Merge channel0 interrupt */ | ||
68 | __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED; | ||
69 | /* setup semaphores */ | ||
70 | for(int i = 0; i< HW_DCP_NUM_CHANNELS; i++) | ||
71 | semaphore_init(&channel_sema[i], 1, 0); | ||
72 | } | ||
73 | |||
74 | // return OBJ_WAIT_TIMEOUT on failure | ||
75 | int imx233_dcp_acquire_channel(int timeout) | ||
76 | { | ||
77 | return arbiter_acquire(&channel_arbiter, timeout); | ||
78 | } | ||
79 | |||
80 | void imx233_dcp_release_channel(int chan) | ||
81 | { | ||
82 | arbiter_release(&channel_arbiter, chan); | ||
83 | } | ||
84 | |||
85 | // doesn't check that channel is in use! | ||
86 | void imx233_dcp_reserve_channel(int channel) | ||
87 | { | ||
88 | arbiter_reserve(&channel_arbiter, channel); | ||
89 | } | ||
90 | |||
91 | static enum imx233_dcp_error_t get_error_status(int ch) | ||
92 | { | ||
93 | uint32_t stat = channel_packet[ch].status; | ||
94 | if(stat & HW_DCP_STATUS__ERROR_SETUP) | ||
95 | return DCP_ERROR_SETUP; | ||
96 | if(stat & HW_DCP_STATUS__ERROR_PACKET) | ||
97 | return DCP_ERROR_PACKET; | ||
98 | if(stat & HW_DCP_STATUS__ERROR_SRC) | ||
99 | return DCP_ERROR_SRC; | ||
100 | if(stat & HW_DCP_STATUS__ERROR_DST) | ||
101 | return DCP_ERROR_DST; | ||
102 | switch(__XTRACT_EX(stat, HW_DCP_STATUS__ERROR_CODE)) | ||
103 | { | ||
104 | case 0: return DCP_SUCCESS; | ||
105 | case 1: return DCP_ERROR_CHAIN_IS_0; | ||
106 | case 2: return DCP_ERROR_NO_CHAIN; | ||
107 | case 3: return DCP_ERROR_CONTEXT; | ||
108 | case 4: return DCP_ERROR_PAYLOAD; | ||
109 | case 5: return DCP_ERROR_MODE; | ||
110 | default: return DCP_ERROR; | ||
111 | } | ||
112 | } | ||
113 | |||
114 | enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int ch, void *src, void *dst, size_t len) | ||
115 | { | ||
116 | /* enable channel, clear interrupt, enable interrupt */ | ||
117 | imx233_enable_interrupt(INT_SRC_DCP, true); | ||
118 | __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch); | ||
119 | __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch); | ||
120 | __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch); | ||
121 | |||
122 | /* prepare packet */ | ||
123 | channel_packet[ch].next = 0; | ||
124 | channel_packet[ch].ctrl0 = HW_DCP_CTRL0__INTERRUPT_ENABLE | | ||
125 | HW_DCP_CTRL0__ENABLE_MEMCOPY | HW_DCP_CTRL0__DECR_SEMAPHORE; | ||
126 | channel_packet[ch].ctrl1 = 0; | ||
127 | channel_packet[ch].src = (uint32_t)PHYSICAL_ADDR(src); | ||
128 | channel_packet[ch].dst = (uint32_t)PHYSICAL_ADDR(dst); | ||
129 | channel_packet[ch].size = len; | ||
130 | channel_packet[ch].payload = 0; | ||
131 | channel_packet[ch].status = 0; | ||
132 | |||
133 | /* write-back src, discard dst, write-back packet */ | ||
134 | commit_discard_dcache_range(src, len); | ||
135 | discard_dcache_range(dst, len); | ||
136 | commit_discard_dcache_range(&channel_packet[ch], sizeof(struct imx233_dcp_packet_t)); | ||
137 | /* write 1 to semaphore to run job */ | ||
138 | HW_DCP_CHxCMDPTR(ch) = (uint32_t)PHYSICAL_ADDR(&channel_packet[ch]); | ||
139 | HW_DCP_CHxSEMA(ch) = 1; | ||
140 | /* wait completion */ | ||
141 | semaphore_wait(&channel_sema[ch], TIMEOUT_BLOCK); | ||
142 | /* read status */ | ||
143 | return get_error_status(ch); | ||
144 | } | ||
145 | |||
146 | enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo) | ||
147 | { | ||
148 | int chan = imx233_dcp_acquire_channel(tmo); | ||
149 | if(chan == OBJ_WAIT_TIMEDOUT) | ||
150 | return DCP_TIMEOUT; | ||
151 | enum imx233_dcp_error_t err = imx233_dcp_memcpy_ex(chan, src, dst, len); | ||
152 | imx233_dcp_release_channel(chan); | ||
153 | return err; | ||
154 | } | ||
155 | |||
156 | struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags) | ||
157 | { | ||
158 | struct imx233_dcp_info_t info; | ||
159 | memset(&info, 0, sizeof(info)); | ||
160 | if(flags & DCP_INFO_CAPABILITIES) | ||
161 | { | ||
162 | info.has_crypto = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CRYPTO; | ||
163 | info.has_csc = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CSC; | ||
164 | info.num_keys = __XTRACT(HW_DCP_CAPABILITY0, NUM_KEYS); | ||
165 | info.num_channels = __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS); | ||
166 | info.ciphers = __XTRACT(HW_DCP_CAPABILITY1, CIPHER_ALGORITHMS); | ||
167 | info.hashs = __XTRACT(HW_DCP_CAPABILITY1, HASH_ALGORITHMS); | ||
168 | } | ||
169 | if(flags & DCP_INFO_GLOBAL_STATE) | ||
170 | { | ||
171 | info.otp_key_ready = HW_DCP_STAT & HW_DCP_STAT__OTP_KEY_READY; | ||
172 | info.context_switching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING; | ||
173 | info.context_caching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_CACHING; | ||
174 | info.gather_writes = HW_DCP_CTRL & HW_DCP_CTRL__GATHER_RESIDUAL_WRITES; | ||
175 | info.ch0_merged = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED; | ||
176 | } | ||
177 | if(flags & DCP_INFO_CHANNELS) | ||
178 | { | ||
179 | for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++) | ||
180 | { | ||
181 | info.channel[i].irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(i); | ||
182 | info.channel[i].irq = HW_DCP_STAT & HW_DCP_STAT__IRQ(i); | ||
183 | info.channel[i].ready = HW_DCP_STAT & HW_DCP_STAT__READY_CHANNELS(i); | ||
184 | info.channel[i].high_priority = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(i); | ||
185 | info.channel[i].enable = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(i); | ||
186 | info.channel[i].sema = __XTRACT_EX(HW_DCP_CHxSEMA(i), HW_DCP_CHxSEMA__VALUE); | ||
187 | info.channel[i].cmdptr = HW_DCP_CHxCMDPTR(i); | ||
188 | } | ||
189 | } | ||
190 | if(flags & DCP_INFO_CSC) | ||
191 | { | ||
192 | info.csc.irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CSC_INTERRUPT_ENABLE; | ||
193 | info.csc.irq = HW_DCP_STAT & HW_DCP_STAT__CSCIRQ; | ||
194 | info.csc.priority = __XTRACT(HW_DCP_CHANNELCTRL, CSC_PRIORITY); | ||
195 | info.csc.enable = HW_DCP_CSCCTRL0 & HW_DCP_CSCCTRL0__ENABLE; | ||
196 | } | ||
197 | return info; | ||
198 | } \ No newline at end of file | ||
diff --git a/firmware/target/arm/imx233/dcp-imx233.h b/firmware/target/arm/imx233/dcp-imx233.h new file mode 100644 index 0000000000..375da16c04 --- /dev/null +++ b/firmware/target/arm/imx233/dcp-imx233.h | |||
@@ -0,0 +1,363 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __DCP_IMX233_H__ | ||
25 | #define __DCP_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | |||
31 | #define HW_DCP_BASE 0x80028000 | ||
32 | |||
33 | /* channels */ | ||
34 | #define HW_DCP_CH(x) (x) | ||
35 | #define HW_DCP_NUM_CHANNELS 4 | ||
36 | #define HW_DCP_CSC 8 | ||
37 | |||
38 | /* ciphers */ | ||
39 | #define HW_DCP_CIPHER_AES128 1 | ||
40 | |||
41 | /* hash */ | ||
42 | #define HW_DCP_HASH_SHA1 1 | ||
43 | #define HW_DCP_HASH_CRC32 2 | ||
44 | |||
45 | #define HW_DCP_CTRL (*(volatile uint32_t *)(HW_DCP_BASE + 0x0)) | ||
46 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BP 0 | ||
47 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BM 0xf | ||
48 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(x) (1 << (x)) | ||
49 | #define HW_DCP_CTRL__CSC_INTERRUPT_ENABLE (1 << 8) | ||
50 | #define HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING (1 << 21) | ||
51 | #define HW_DCP_CTRL__ENABLE_CONTEXT_CACHING (1 << 22) | ||
52 | #define HW_DCP_CTRL__GATHER_RESIDUAL_WRITES (1 << 23) | ||
53 | #define HW_DCP_CTRL__PRESENT_CSC (1 << 28) | ||
54 | #define HW_DCP_CTRL__PRESENT_CRYPTO (1 << 29) | ||
55 | |||
56 | #define HW_DCP_STAT (*(volatile uint32_t *)(HW_DCP_BASE + 0x10)) | ||
57 | #define HW_DCP_STAT__IRQ_BP 0 | ||
58 | #define HW_DCP_STAT__IRQ_BM 0xf | ||
59 | #define HW_DCP_STAT__IRQ(x) (1 << (x)) | ||
60 | #define HW_DCP_STAT__CSCIRQ (1 << 8) | ||
61 | #define HW_DCP_STAT__READY_CHANNELS_BP 16 | ||
62 | #define HW_DCP_STAT__READY_CHANNELS_BM (0xff << 16) | ||
63 | #define HW_DCP_STAT__READY_CHANNELS(x) (1 << (16 + (x))) | ||
64 | #define HW_DCP_STAT__CUR_CHANNEL_BP 24 | ||
65 | #define HW_DCP_STAT__CUR_CHANNEL_BM (0xf << 24) | ||
66 | #define HW_DCP_STAT__OTP_KEY_READY (1 << 28) | ||
67 | |||
68 | #define HW_DCP_CHANNELCTRL (*(volatile uint32_t *)(HW_DCP_BASE + 0x20)) | ||
69 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BP 0 | ||
70 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BM 0xff | ||
71 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(x) (1 << (x)) | ||
72 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BP 8 | ||
73 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BM (0xff << 8) | ||
74 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(x) (1 << (8 + (x))) | ||
75 | #define HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED (1 << 16) | ||
76 | #define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BP 17 | ||
77 | #define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BM (3 << 17) | ||
78 | |||
79 | #define HW_DCP_CAPABILITY0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x30)) | ||
80 | #define HW_DCP_CAPABILITY0__NUM_KEYS_BP 0 | ||
81 | #define HW_DCP_CAPABILITY0__NUM_KEYS_BM 0xff | ||
82 | #define HW_DCP_CAPABILITY0__NUM_CHANNELS_BP 8 | ||
83 | #define HW_DCP_CAPABILITY0__NUM_CHANNELS_BM 0xf00 | ||
84 | #define HW_DCP_CAPABILITY0__ENABLE_TZONE (1 << 30) | ||
85 | #define HW_DCP_CAPABILITY0__DISABLE_DECRYPT (1 << 31) | ||
86 | |||
87 | #define HW_DCP_CAPABILITY1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x40)) | ||
88 | #define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BP 0 | ||
89 | #define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BM 0xffff | ||
90 | #define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BP 16 | ||
91 | #define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BM 0xffff0000 | ||
92 | |||
93 | #define HW_DCP_CONTEXT (*(volatile uint32_t *)(HW_DCP_BASE + 0x50)) | ||
94 | |||
95 | #define HW_DCP_KEY (*(volatile uint32_t *)(HW_DCP_BASE + 0x60)) | ||
96 | |||
97 | #define HW_DCP_KEYDATA (*(volatile uint32_t *)(HW_DCP_BASE + 0x70)) | ||
98 | |||
99 | #define HW_DCP_PACKET0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x80)) | ||
100 | |||
101 | #define HW_DCP_PACKET1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x90)) | ||
102 | |||
103 | #define HW_DCP_PACKET2 (*(volatile uint32_t *)(HW_DCP_BASE + 0xa0)) | ||
104 | |||
105 | #define HW_DCP_PACKET3 (*(volatile uint32_t *)(HW_DCP_BASE + 0xb0)) | ||
106 | |||
107 | #define HW_DCP_PACKET4 (*(volatile uint32_t *)(HW_DCP_BASE + 0xc0)) | ||
108 | |||
109 | #define HW_DCP_PACKET5 (*(volatile uint32_t *)(HW_DCP_BASE + 0xd0)) | ||
110 | |||
111 | #define HW_DCP_PACKET6 (*(volatile uint32_t *)(HW_DCP_BASE + 0xe0)) | ||
112 | |||
113 | #define HW_DCP_CHxCMDPTR(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x100 + (x) * 0x40)) | ||
114 | |||
115 | #define HW_DCP_CHxSEMA(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x110 + (x) * 0x40)) | ||
116 | #define HW_DCP_CHxSEMA__INCREMENT_BP 0 | ||
117 | #define HW_DCP_CHxSEMA__INCREMENT_BM 0xff | ||
118 | #define HW_DCP_CHxSEMA__VALUE_BP 16 | ||
119 | #define HW_DCP_CHxSEMA__VALUE_BM 0xff0000 | ||
120 | |||
121 | #define HW_DCP_CHxSTAT(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x120 + (x) * 0x40)) | ||
122 | |||
123 | #define HW_DCP_CHxOPTS(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x130 + (x) * 0x40)) | ||
124 | #define HW_DCP_CHxOPTS__RECOVERY_TIMER_BP 0 | ||
125 | #define HW_DCP_CHxOPTS__RECOVERY_TIMER_BM 0xffff | ||
126 | |||
127 | #define HW_DCP_CSCCTRL0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x300)) | ||
128 | #define HW_DCP_CSCCTRL0__ENABLE (1 << 0) | ||
129 | #define HW_DCP_CSCCTRL0__YUV_FORMAT_BP 4 | ||
130 | #define HW_DCP_CSCCTRL0__YUV_FORMAT_BM 0xf0 | ||
131 | #define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV420 0x0 | ||
132 | #define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV422 0x2 | ||
133 | #define HW_DCP_CSCCTRL0__RGB_FORMAT_BP 8 | ||
134 | #define HW_DCP_CSCCTRL0__RGB_FORMAT_BM 0x300 | ||
135 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB16_565 0x0 | ||
136 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__YCbCrI 0x1 | ||
137 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB24 0x2 | ||
138 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__YUV422I 0x3 | ||
139 | #define HW_DCP_CSCCTRL0__DELTA (1 << 10) | ||
140 | #define HW_DCP_CSCCTRL0__SUBSAMPLE (1 << 11) | ||
141 | #define HW_DCP_CSCCTRL0__ROTATE (1 << 12) | ||
142 | #define HW_DCP_CSCCTRL0__SCALE (1 << 13) | ||
143 | #define HW_DCP_CSCCTRL0__UPSAMPLE (1 << 14) | ||
144 | #define HW_DCP_CSCCTRL0__CLIP (1 << 15) | ||
145 | |||
146 | #define HW_DCP_CSCSTAT (*(volatile uint32_t *)(HW_DCP_BASE + 0x310)) | ||
147 | #define HW_DCP_CSCSTAT__COMPLETE (1 << 0) | ||
148 | #define HW_DCP_CSCSTAT__ERROR_SETUP (1 << 2) | ||
149 | #define HW_DCP_CSCSTAT__ERROR_SRC (1 << 4) | ||
150 | #define HW_DCP_CSCSTAT__ERROR_DST (1 << 5) | ||
151 | #define HW_DCP_CSCSTAT__ERROR_PAGEFAULT (1 << 6) | ||
152 | #define HW_DCP_CSCSTAT__ERROR_CODE_BP 16 | ||
153 | #define HW_DCP_CSCSTAT__ERROR_CODE_BM (0xff << 16) | ||
154 | |||
155 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile uint32_t *)(HW_DCP_BASE + 0x320)) | ||
156 | #define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BP 0 | ||
157 | #define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BM 0xfff | ||
158 | #define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BP 12 | ||
159 | #define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BM 0xfff000 | ||
160 | |||
161 | #define HW_DCP_CSCINBUFPARAM (*(volatile uint32_t *)(HW_DCP_BASE + 0x330)) | ||
162 | #define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BP 0 | ||
163 | #define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BM 0xfff | ||
164 | |||
165 | #define HW_DCP_CSCRGB (*(volatile uint32_t *)(HW_DCP_BASE + 0x340)) | ||
166 | |||
167 | #define HW_DCP_CSCLUMA (*(volatile uint32_t *)(HW_DCP_BASE + 0x350)) | ||
168 | |||
169 | #define HW_DCP_CSCCHROMAU (*(volatile uint32_t *)(HW_DCP_BASE + 0x360)) | ||
170 | |||
171 | #define HW_DCP_CSCCHROMAV (*(volatile uint32_t *)(HW_DCP_BASE + 0x370)) | ||
172 | |||
173 | #define HW_DCP_CSCCOEFF0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x380)) | ||
174 | #define HW_DCP_CSCCOEFF0__Y_OFFSET_BP 0 | ||
175 | #define HW_DCP_CSCCOEFF0__Y_OFFSET_BM 0xff | ||
176 | #define HW_DCP_CSCCOEFF0__UV_OFFSET_BP 8 | ||
177 | #define HW_DCP_CSCCOEFF0__UV_OFFSET_BM 0xff00 | ||
178 | #define HW_DCP_CSCCOEFF0__C0_BP 16 | ||
179 | #define HW_DCP_CSCCOEFF0__C0_BM 0x3ff0000 | ||
180 | |||
181 | #define HW_DCP_CSCCOEFF1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x390)) | ||
182 | #define HW_DCP_CSCCOEFF1__C4_BP 0 | ||
183 | #define HW_DCP_CSCCOEFF1__C4_BM 0x3ff | ||
184 | #define HW_DCP_CSCCOEFF1__C1_BP 16 | ||
185 | #define HW_DCP_CSCCOEFF1__C1_BM 0x3ff0000 | ||
186 | |||
187 | #define HW_DCP_CSCCOEFF2 (*(volatile uint32_t *)(HW_DCP_BASE + 0x3a0)) | ||
188 | #define HW_DCP_CSCCOEFF2__C3_BP 0 | ||
189 | #define HW_DCP_CSCCOEFF2__C3_BM 0x3ff | ||
190 | #define HW_DCP_CSCCOEFF2__C2_BP 16 | ||
191 | #define HW_DCP_CSCCOEFF2__C2_BM 0x3ff0000 | ||
192 | |||
193 | #define HW_DCP_CSCCLIP (*(volatile uint32_t *)(HW_DCP_BASE + 0x3b0)) | ||
194 | #define HW_DCP_CSCCLIP__WIDTH_BP 0 | ||
195 | #define HW_DCP_CSCCLIP__WIDTH_BM 0xfff | ||
196 | #define HW_DCP_CSCCLIP__HEIGHT_BP 12 | ||
197 | #define HW_DCP_CSCCLIP__HEIGHT_BM 0xfff000 | ||
198 | |||
199 | #define HW_DCP_CSCXSCALE (*(volatile uint32_t *)(HW_DCP_BASE + 0x3c0)) | ||
200 | #define HW_DCP_CSCXSCALE__WIDTH_BP 0 | ||
201 | #define HW_DCP_CSCXSCALE__WIDTH_BM 0xfff | ||
202 | #define HW_DCP_CSCXSCALE__FRAC_BP 12 | ||
203 | #define HW_DCP_CSCXSCALE__FRAC_BM 0xfff000 | ||
204 | #define HW_DCP_CSCXSCALE__INT_BP 24 | ||
205 | #define HW_DCP_CSCXSCALE__INT_BM 0x3000000 | ||
206 | |||
207 | #define HW_DCP_CSCYSCALE (*(volatile uint32_t *)(HW_DCP_BASE + 0x3d0)) | ||
208 | #define HW_DCP_CSCYSCALE__WIDTH_BP 0 | ||
209 | #define HW_DCP_CSCYSCALE__WIDTH_BM 0xfff | ||
210 | #define HW_DCP_CSCYSCALE__FRAC_BP 12 | ||
211 | #define HW_DCP_CSCYSCALE__FRAC_BM 0xfff000 | ||
212 | #define HW_DCP_CSCYSCALE__INT_BP 24 | ||
213 | #define HW_DCP_CSCYSCALE__INT_BM 0x3000000 | ||
214 | |||
215 | #define HW_DCP_PAGETABLE (*(volatile uint32_t *)(HW_DCP_BASE + 0x420)) | ||
216 | #define HW_DCP_PAGETABLE__ENABLE (1 << 0) | ||
217 | #define HW_DCP_PAGETABLE__FLUSH (1 << 1) | ||
218 | #define HW_DCP_PAGETABLE__BASE_BP 2 | ||
219 | #define HW_DCP_PAGETABLE__BASE_BM 0xfffffffc | ||
220 | |||
221 | struct imx233_dcp_packet_t | ||
222 | { | ||
223 | uint32_t next; | ||
224 | uint32_t ctrl0; | ||
225 | uint32_t ctrl1; | ||
226 | uint32_t src; | ||
227 | uint32_t dst; | ||
228 | uint32_t size; | ||
229 | uint32_t payload; | ||
230 | uint32_t status; | ||
231 | } __attribute__((packed)); | ||
232 | |||
233 | #define HW_DCP_CTRL0__INTERRUPT_ENABLE (1 << 0) | ||
234 | #define HW_DCP_CTRL0__DECR_SEMAPHORE (1 << 1) | ||
235 | #define HW_DCP_CTRL0__CHAIN (1 << 2) | ||
236 | #define HW_DCP_CTRL0__CHAIN_CONTINUOUS (1 << 3) | ||
237 | #define HW_DCP_CTRL0__ENABLE_MEMCOPY (1 << 4) | ||
238 | #define HW_DCP_CTRL0__ENABLE_CIPHER (1 << 5) | ||
239 | #define HW_DCP_CTRL0__ENABLE_HASH (1 << 6) | ||
240 | #define HW_DCP_CTRL0__ENABLE_BLIT (1 << 7) | ||
241 | #define HW_DCP_CTRL0__CIPHER_ENCRYPT (1 << 8) | ||
242 | #define HW_DCP_CTRL0__CIPHER_INIT (1 << 9) | ||
243 | #define HW_DCP_CTRL0__OTP_KEY (1 << 10) | ||
244 | #define HW_DCP_CTRL0__PAYLOAD_KEY (1 << 11) | ||
245 | #define HW_DCP_CTRL0__HASH_INIT (1 << 12) | ||
246 | #define HW_DCP_CTRL0__HASH_TERM (1 << 13) | ||
247 | #define HW_DCP_CTRL0__HASH_CHECK (1 << 14) | ||
248 | #define HW_DCP_CTRL0__HASH_OUTPUT (1 << 15) | ||
249 | #define HW_DCP_CTRL0__CONSTANT_FILL (1 << 16) | ||
250 | #define HW_DCP_CTRL0__TEST_SEMA_IRQ (1 << 17) | ||
251 | #define HW_DCP_CTRL0__KEY_BYTESWAP (1 << 18) | ||
252 | #define HW_DCP_CTRL0__KEY_WORDSWAP (1 << 19) | ||
253 | #define HW_DCP_CTRL0__INPUT_BYTESWAP (1 << 20) | ||
254 | #define HW_DCP_CTRL0__INPUT_WORDSWAP (1 << 21) | ||
255 | #define HW_DCP_CTRL0__OUTPUT_BYTESWAP (1 << 22) | ||
256 | #define HW_DCP_CTRL0__OUTPUT_WORDSWAP (1 << 23) | ||
257 | #define HW_DCP_CTRL0__TAG_BP 24 | ||
258 | #define HW_DCP_CTRL0__TAG_BM (0xff << 24) | ||
259 | |||
260 | #define HW_DCP_CTRL1__CIPHER_SELECT_BP 0 | ||
261 | #define HW_DCP_CTRL1__CIPHER_SELECT_BM 0xf | ||
262 | #define HW_DCP_CTRL1__CIPHER_MODE_BP 4 | ||
263 | #define HW_DCP_CTRL1__CIPHER_MODE_BM 0xf0 | ||
264 | #define HW_DCP_CTRL1__KEY_SELECT_BP 8 | ||
265 | #define HW_DCP_CTRL1__KEY_SELECT_BM 0xff00 | ||
266 | #define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BP 0 | ||
267 | #define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BM 0xffff | ||
268 | #define HW_DCP_CTRL1__HASH_SELECT_BP 16 | ||
269 | #define HW_DCP_CTRL1__HASH_SELECT_BM 0xf0000 | ||
270 | #define HW_DCP_CTRL1__CIPHER_CONFIG_BP 24 | ||
271 | #define HW_DCP_CTRL1__CIPHER_CONFIG_BM (0xff << 24) | ||
272 | |||
273 | #define HW_DCP_SIZE__BLIT_WIDTH_BP 0 | ||
274 | #define HW_DCP_SIZE__BLIT_WIDTH_BM 0xffff | ||
275 | #define HW_DCP_SIZE__NUMBER_LINES_BP 16 | ||
276 | #define HW_DCP_SIZE__NUMBER_LINES_BM 0xffff0000 | ||
277 | |||
278 | #define HW_DCP_STATUS__COMPLETE (1 << 0) | ||
279 | #define HW_DCP_STATUS__HASH_MISMATCH (1 << 1) | ||
280 | #define HW_DCP_STATUS__ERROR_SETUP (1 << 2) | ||
281 | #define HW_DCP_STATUS__ERROR_PACKET (1 << 3) | ||
282 | #define HW_DCP_STATUS__ERROR_SRC (1 << 4) | ||
283 | #define HW_DCP_STATUS__ERROR_DST (1 << 5) | ||
284 | #define HW_DCP_STATUS__ERROR_CODE_BP 16 | ||
285 | #define HW_DCP_STATUS__ERROR_CODE_BM (0xff << 16) | ||
286 | #define HW_DCP_STATUS__TAG_BP 24 | ||
287 | #define HW_DCP_STATUS__TAG_BM (0xff << 24) | ||
288 | |||
289 | struct imx233_dcp_channel_info_t | ||
290 | { | ||
291 | bool irq; | ||
292 | bool irq_en; | ||
293 | bool enable; | ||
294 | bool high_priority; | ||
295 | bool ready; | ||
296 | int sema; | ||
297 | uint32_t cmdptr; | ||
298 | }; | ||
299 | |||
300 | struct imx233_dcp_csc_info_t | ||
301 | { | ||
302 | bool irq; | ||
303 | bool irq_en; | ||
304 | bool enable; | ||
305 | int priority; | ||
306 | }; | ||
307 | |||
308 | struct imx233_dcp_info_t | ||
309 | { | ||
310 | /* capabilities */ | ||
311 | bool has_crypto; | ||
312 | bool has_csc; | ||
313 | int num_keys; | ||
314 | int num_channels; | ||
315 | unsigned ciphers; | ||
316 | unsigned hashs; | ||
317 | /* global state */ | ||
318 | bool context_switching; | ||
319 | bool context_caching; | ||
320 | bool gather_writes; | ||
321 | bool otp_key_ready; | ||
322 | bool ch0_merged; | ||
323 | /* channel state */ | ||
324 | struct imx233_dcp_channel_info_t channel[HW_DCP_NUM_CHANNELS]; | ||
325 | /* csc state */ | ||
326 | struct imx233_dcp_csc_info_t csc; | ||
327 | }; | ||
328 | |||
329 | #define DCP_INFO_CAPABILITIES (1 << 0) | ||
330 | #define DCP_INFO_GLOBAL_STATE (1 << 1) | ||
331 | #define DCP_INFO_CHANNELS (1 << 2) | ||
332 | #define DCP_INFO_CSC (1 << 3) | ||
333 | #define DCP_INFO_ALL 0xf | ||
334 | |||
335 | enum imx233_dcp_error_t | ||
336 | { | ||
337 | DCP_SUCCESS = 0, | ||
338 | DCP_TIMEOUT = -1, | ||
339 | DCP_ERROR_SETUP = -2, | ||
340 | DCP_ERROR_PACKET = -3, | ||
341 | DCP_ERROR_SRC = -4, | ||
342 | DCP_ERROR_DST = -5, | ||
343 | DCP_ERROR_CHAIN_IS_0 = -6, | ||
344 | DCP_ERROR_NO_CHAIN = -7, | ||
345 | DCP_ERROR_CONTEXT = -8, | ||
346 | DCP_ERROR_PAYLOAD = -9, | ||
347 | DCP_ERROR_MODE = -10, | ||
348 | DCP_ERROR = -11 | ||
349 | }; | ||
350 | |||
351 | void imx233_dcp_init(void); | ||
352 | // return OBJ_WAIT_TIMEOUT on failure | ||
353 | int imx233_dcp_acquire_channel(int timeout); | ||
354 | void imx233_dcp_release_channel(int chan); | ||
355 | // doesn't check that channel is in use! | ||
356 | void imx233_dcp_reserve_channel(int channel); | ||
357 | |||
358 | enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int channel, void *src, void *dst, size_t len); | ||
359 | enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo); | ||
360 | |||
361 | struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags); | ||
362 | |||
363 | #endif // __DMA_IMX233_H__ | ||
diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c index 51d306b7b1..7db7ee97d7 100644 --- a/firmware/target/arm/imx233/debug-imx233.c +++ b/firmware/target/arm/imx233/debug-imx233.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include "clkctrl-imx233.h" | 30 | #include "clkctrl-imx233.h" |
31 | #include "powermgmt-imx233.h" | 31 | #include "powermgmt-imx233.h" |
32 | #include "rtc-imx233.h" | 32 | #include "rtc-imx233.h" |
33 | #include "dcp-imx233.h" | ||
33 | #include "string.h" | 34 | #include "string.h" |
34 | 35 | ||
35 | #define DEBUG_CANCEL BUTTON_BACK | 36 | #define DEBUG_CANCEL BUTTON_BACK |
@@ -347,11 +348,57 @@ bool dbg_hw_info_rtc(void) | |||
347 | } | 348 | } |
348 | } | 349 | } |
349 | 350 | ||
351 | bool dbg_hw_info_dcp(void) | ||
352 | { | ||
353 | lcd_setfont(FONT_SYSFIXED); | ||
354 | |||
355 | while(1) | ||
356 | { | ||
357 | int button = get_action(CONTEXT_STD, HZ / 10); | ||
358 | switch(button) | ||
359 | { | ||
360 | case ACTION_STD_NEXT: | ||
361 | case ACTION_STD_PREV: | ||
362 | case ACTION_STD_OK: | ||
363 | case ACTION_STD_MENU: | ||
364 | lcd_setfont(FONT_UI); | ||
365 | return true; | ||
366 | case ACTION_STD_CANCEL: | ||
367 | lcd_setfont(FONT_UI); | ||
368 | return false; | ||
369 | } | ||
370 | |||
371 | lcd_clear_display(); | ||
372 | struct imx233_dcp_info_t info = imx233_dcp_get_info(DCP_INFO_ALL); | ||
373 | |||
374 | lcd_putsf(0, 0, "crypto: %d csc: %d", info.has_crypto, info.has_csc); | ||
375 | lcd_putsf(0, 1, "keys: %d channels: %d", info.num_keys, info.num_channels); | ||
376 | lcd_putsf(0, 2, "ciphers: 0x%lx hash: 0x%lx", info.ciphers, info.hashs); | ||
377 | lcd_putsf(0, 3, "gather wr: %d otp rdy: %d ch0merged: %d", | ||
378 | info.gather_writes, info.otp_key_ready, info.ch0_merged); | ||
379 | lcd_putsf(0, 4, "ctx switching: %d caching: %d", info.context_switching, | ||
380 | info.context_caching); | ||
381 | lcd_putsf(0, 5, "ch irq ien en rdy pri sem cmdptr"); | ||
382 | int nr = HW_DCP_NUM_CHANNELS; | ||
383 | for(int i = 0; i < nr; i++) | ||
384 | { | ||
385 | lcd_putsf(0, 6 + i, "%d %d %d %d %d %d %d 0x%08lx", | ||
386 | i, info.channel[i].irq, info.channel[i].irq_en, info.channel[i].enable, | ||
387 | info.channel[i].ready, info.channel[i].high_priority, | ||
388 | info.channel[i].sema, info.channel[i].cmdptr); | ||
389 | } | ||
390 | lcd_putsf(0, 6 + nr, "csc %d %d %d %d", | ||
391 | info.csc.irq, info.csc.irq_en, info.csc.enable, info.csc.priority); | ||
392 | lcd_update(); | ||
393 | yield(); | ||
394 | } | ||
395 | } | ||
396 | |||
350 | bool dbg_hw_info(void) | 397 | bool dbg_hw_info(void) |
351 | { | 398 | { |
352 | return dbg_hw_info_clkctrl() && dbg_hw_info_dma() && dbg_hw_info_adc() && | 399 | return dbg_hw_info_clkctrl() && dbg_hw_info_dma() && dbg_hw_info_adc() && |
353 | dbg_hw_info_power() && dbg_hw_info_powermgmt() && dbg_hw_info_rtc() && | 400 | dbg_hw_info_power() && dbg_hw_info_powermgmt() && dbg_hw_info_rtc() && |
354 | dbg_hw_target_info(); | 401 | dbg_hw_info_dcp() && dbg_hw_target_info(); |
355 | } | 402 | } |
356 | 403 | ||
357 | bool dbg_ports(void) | 404 | bool dbg_ports(void) |
diff --git a/firmware/target/arm/imx233/kernel-imx233.c b/firmware/target/arm/imx233/kernel-imx233.c index edb9b8366c..b59d3ed63f 100644 --- a/firmware/target/arm/imx233/kernel-imx233.c +++ b/firmware/target/arm/imx233/kernel-imx233.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include "kernel.h" | 21 | #include "kernel.h" |
22 | #include "timrot-imx233.h" | 22 | #include "timrot-imx233.h" |
23 | #include "clkctrl-imx233.h" | 23 | #include "clkctrl-imx233.h" |
24 | #include "kernel-imx233.h" | ||
24 | 25 | ||
25 | static void tick_timer(void) | 26 | static void tick_timer(void) |
26 | { | 27 | { |
@@ -35,3 +36,45 @@ void tick_start(unsigned int interval_in_ms) | |||
35 | HW_TIMROT_TIMCTRL__SELECT_1KHZ_XTAL, HW_TIMROT_TIMCTRL__PRESCALE_1, | 36 | HW_TIMROT_TIMCTRL__SELECT_1KHZ_XTAL, HW_TIMROT_TIMCTRL__PRESCALE_1, |
36 | false, &tick_timer); | 37 | false, &tick_timer); |
37 | } | 38 | } |
39 | |||
40 | |||
41 | void arbiter_init(struct channel_arbiter_t *a, unsigned count) | ||
42 | { | ||
43 | mutex_init(&a->mutex); | ||
44 | semaphore_init(&a->sema, count, count); | ||
45 | a->free_bm = (1 << count) - 1; | ||
46 | a->count = count; | ||
47 | } | ||
48 | |||
49 | // doesn't check in use ! | ||
50 | void arbiter_reserve(struct channel_arbiter_t *a, unsigned channel) | ||
51 | { | ||
52 | // assume semaphore has a free slot immediately | ||
53 | if(semaphore_wait(&a->sema, TIMEOUT_NOBLOCK) != OBJ_WAIT_SUCCEEDED) | ||
54 | panicf("arbiter_reserve failed on semaphore_wait !"); | ||
55 | mutex_lock(&a->mutex); | ||
56 | a->free_bm &= ~(1 << channel); | ||
57 | mutex_unlock(&a->mutex); | ||
58 | } | ||
59 | |||
60 | int arbiter_acquire(struct channel_arbiter_t *a, int timeout) | ||
61 | { | ||
62 | int w = semaphore_wait(&a->sema, timeout); | ||
63 | if(w == OBJ_WAIT_TIMEDOUT) | ||
64 | return w; | ||
65 | mutex_lock(&a->mutex); | ||
66 | int chan = find_first_set_bit(a->free_bm); | ||
67 | if(chan >= a->count) | ||
68 | panicf("arbiter_acquire cannot find a free channel !"); | ||
69 | a->free_bm &= ~(1 << chan); | ||
70 | mutex_unlock(&a->mutex); | ||
71 | return chan; | ||
72 | } | ||
73 | |||
74 | void arbiter_release(struct channel_arbiter_t *a, int channel) | ||
75 | { | ||
76 | mutex_lock(&a->mutex); | ||
77 | a->free_bm |= 1 << channel; | ||
78 | mutex_unlock(&a->mutex); | ||
79 | semaphore_release(&a->sema); | ||
80 | } | ||
diff --git a/firmware/target/arm/imx233/lradc-imx233.c b/firmware/target/arm/imx233/lradc-imx233.c index 8b065bffea..432d1c1035 100644 --- a/firmware/target/arm/imx233/lradc-imx233.c +++ b/firmware/target/arm/imx233/lradc-imx233.c | |||
@@ -21,60 +21,12 @@ | |||
21 | #include "system.h" | 21 | #include "system.h" |
22 | #include "system-target.h" | 22 | #include "system-target.h" |
23 | #include "lradc-imx233.h" | 23 | #include "lradc-imx233.h" |
24 | 24 | #include "kernel-imx233.h" | |
25 | struct channel_arbiter_t | ||
26 | { | ||
27 | struct semaphore sema; | ||
28 | struct mutex mutex; | ||
29 | unsigned free_bm; | ||
30 | int count; | ||
31 | }; | ||
32 | |||
33 | static void arbiter_init(struct channel_arbiter_t *a, unsigned count) | ||
34 | { | ||
35 | mutex_init(&a->mutex); | ||
36 | semaphore_init(&a->sema, count, count); | ||
37 | a->free_bm = (1 << count) - 1; | ||
38 | a->count = count; | ||
39 | } | ||
40 | |||
41 | // doesn't check in use ! | ||
42 | static void arbiter_reserve(struct channel_arbiter_t *a, unsigned channel) | ||
43 | { | ||
44 | // assume semaphore has a free slot immediately | ||
45 | if(semaphore_wait(&a->sema, TIMEOUT_NOBLOCK) != OBJ_WAIT_SUCCEEDED) | ||
46 | panicf("arbiter_reserve failed on semaphore_wait !"); | ||
47 | mutex_lock(&a->mutex); | ||
48 | a->free_bm &= ~(1 << channel); | ||
49 | mutex_unlock(&a->mutex); | ||
50 | } | ||
51 | |||
52 | static int arbiter_acquire(struct channel_arbiter_t *a, int timeout) | ||
53 | { | ||
54 | int w = semaphore_wait(&a->sema, timeout); | ||
55 | if(w == OBJ_WAIT_TIMEDOUT) | ||
56 | return w; | ||
57 | mutex_lock(&a->mutex); | ||
58 | int chan = find_first_set_bit(a->free_bm); | ||
59 | if(chan >= a->count) | ||
60 | panicf("arbiter_acquire cannot find a free channel !"); | ||
61 | a->free_bm &= ~(1 << chan); | ||
62 | mutex_unlock(&a->mutex); | ||
63 | return chan; | ||
64 | } | ||
65 | |||
66 | static void arbiter_release(struct channel_arbiter_t *a, int channel) | ||
67 | { | ||
68 | mutex_lock(&a->mutex); | ||
69 | a->free_bm |= 1 << channel; | ||
70 | mutex_unlock(&a->mutex); | ||
71 | semaphore_release(&a->sema); | ||
72 | } | ||
73 | 25 | ||
74 | /* channels */ | 26 | /* channels */ |
75 | struct channel_arbiter_t channel_arbiter; | 27 | static struct channel_arbiter_t channel_arbiter; |
76 | /* delay channels */ | 28 | /* delay channels */ |
77 | struct channel_arbiter_t delay_arbiter; | 29 | static struct channel_arbiter_t delay_arbiter; |
78 | 30 | ||
79 | void imx233_lradc_setup_channel(int channel, bool div2, bool acc, int nr_samples, int src) | 31 | void imx233_lradc_setup_channel(int channel, bool div2, bool acc, int nr_samples, int src) |
80 | { | 32 | { |
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 19d0a7fac9..c9d490302e 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include "dma-imx233.h" | 30 | #include "dma-imx233.h" |
31 | #include "ssp-imx233.h" | 31 | #include "ssp-imx233.h" |
32 | #include "i2c-imx233.h" | 32 | #include "i2c-imx233.h" |
33 | #include "dcp-imx233.h" | ||
33 | #include "lcd.h" | 34 | #include "lcd.h" |
34 | #include "backlight-target.h" | 35 | #include "backlight-target.h" |
35 | #include "button.h" | 36 | #include "button.h" |
@@ -68,6 +69,7 @@ default_interrupt(INT_LRADC_CH6); | |||
68 | default_interrupt(INT_LRADC_CH7); | 69 | default_interrupt(INT_LRADC_CH7); |
69 | default_interrupt(INT_DAC_DMA); | 70 | default_interrupt(INT_DAC_DMA); |
70 | default_interrupt(INT_DAC_ERROR); | 71 | default_interrupt(INT_DAC_ERROR); |
72 | default_interrupt(INT_DCP); | ||
71 | 73 | ||
72 | typedef void (*isr_t)(void); | 74 | typedef void (*isr_t)(void); |
73 | 75 | ||
@@ -100,6 +102,7 @@ static isr_t isr_table[INT_SRC_NR_SOURCES] = | |||
100 | [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7, | 102 | [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7, |
101 | [INT_SRC_DAC_DMA] = INT_DAC_DMA, | 103 | [INT_SRC_DAC_DMA] = INT_DAC_DMA, |
102 | [INT_SRC_DAC_ERROR] = INT_DAC_ERROR, | 104 | [INT_SRC_DAC_ERROR] = INT_DAC_ERROR, |
105 | [INT_SRC_DCP] = INT_DCP, | ||
103 | }; | 106 | }; |
104 | 107 | ||
105 | static void UIRQ(void) | 108 | static void UIRQ(void) |
@@ -205,6 +208,7 @@ void system_init(void) | |||
205 | imx233_timrot_init(); | 208 | imx233_timrot_init(); |
206 | imx233_dma_init(); | 209 | imx233_dma_init(); |
207 | imx233_ssp_init(); | 210 | imx233_ssp_init(); |
211 | imx233_dcp_init(); | ||
208 | } | 212 | } |
209 | 213 | ||
210 | bool imx233_us_elapsed(uint32_t ref, unsigned us_delay) | 214 | bool imx233_us_elapsed(uint32_t ref, unsigned us_delay) |
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h index 9ad9d1d808..6a5cecaf87 100644 --- a/firmware/target/arm/imx233/system-target.h +++ b/firmware/target/arm/imx233/system-target.h | |||
@@ -34,6 +34,8 @@ | |||
34 | #define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0)) | 34 | #define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0)) |
35 | #define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2) | 35 | #define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2) |
36 | 36 | ||
37 | #define HW_DIGCTL_HCLKCOUNT (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20)) | ||
38 | |||
37 | #define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0)) | 39 | #define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0)) |
38 | 40 | ||
39 | /* USB Phy */ | 41 | /* USB Phy */ |
@@ -80,6 +82,7 @@ | |||
80 | #define INT_SRC_LRADC_CHx(x) (37 + (x)) | 82 | #define INT_SRC_LRADC_CHx(x) (37 + (x)) |
81 | #define INT_SRC_LCDIF_DMA 45 | 83 | #define INT_SRC_LCDIF_DMA 45 |
82 | #define INT_SRC_LCDIF_ERROR 46 | 84 | #define INT_SRC_LCDIF_ERROR 46 |
85 | #define INT_SRC_DCP 54 | ||
83 | #define INT_SRC_NR_SOURCES 66 | 86 | #define INT_SRC_NR_SOURCES 66 |
84 | 87 | ||
85 | /** | 88 | /** |