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Diffstat (limited to 'firmware/target/arm/imx233/dcp-imx233.c')
-rw-r--r--firmware/target/arm/imx233/dcp-imx233.c198
1 files changed, 198 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/dcp-imx233.c b/firmware/target/arm/imx233/dcp-imx233.c
new file mode 100644
index 0000000000..565dba7691
--- /dev/null
+++ b/firmware/target/arm/imx233/dcp-imx233.c
@@ -0,0 +1,198 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2011 by amaury Pouly
11 *
12 * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
13 * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21 * KIND, either express or implied.
22 *
23 ****************************************************************************/
24#include "config.h"
25#include "system.h"
26#include "dcp-imx233.h"
27#include "string.h"
28#include "kernel-imx233.h"
29
30/* The hardware uses 160 bytes of storage to enable context switching */
31static uint8_t dcp_context[160] NOCACHEBSS_ATTR;
32/* Channel arbiter */
33static struct channel_arbiter_t channel_arbiter;
34/* Channel packets */
35static struct imx233_dcp_packet_t channel_packet[HW_DCP_NUM_CHANNELS];
36/* completion semaphore */
37static struct semaphore channel_sema[HW_DCP_NUM_CHANNELS];
38
39void INT_DCP(void)
40{
41 /* clear interrupt and wakeup completion handler */
42 for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
43 {
44 if(HW_DCP_STAT & HW_DCP_STAT__IRQ(i))
45 {
46 __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(i);
47 semaphore_release(&channel_sema[i]);
48 }
49 }
50}
51
52void imx233_dcp_init(void)
53{
54 /* Reset block */
55 imx233_reset_block(&HW_DCP_CTRL);
56 /* Setup contexte pointer */
57 HW_DCP_CONTEXT = (uint32_t)PHYSICAL_ADDR(&dcp_context);
58 /* Enable context switching and caching */
59 __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__ENABLE_CONTEXT_CACHING |
60 HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
61 /* Check that there are sufficiently many channels */
62 if(__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS) != HW_DCP_NUM_CHANNELS)
63 panicf("DCP has %lu channels but was configured to use %d !",
64 __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS), HW_DCP_NUM_CHANNELS);
65 /* Setup channel arbiter to use */
66 arbiter_init(&channel_arbiter, HW_DCP_NUM_CHANNELS);
67 /* Merge channel0 interrupt */
68 __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
69 /* setup semaphores */
70 for(int i = 0; i< HW_DCP_NUM_CHANNELS; i++)
71 semaphore_init(&channel_sema[i], 1, 0);
72}
73
74// return OBJ_WAIT_TIMEOUT on failure
75int imx233_dcp_acquire_channel(int timeout)
76{
77 return arbiter_acquire(&channel_arbiter, timeout);
78}
79
80void imx233_dcp_release_channel(int chan)
81{
82 arbiter_release(&channel_arbiter, chan);
83}
84
85// doesn't check that channel is in use!
86void imx233_dcp_reserve_channel(int channel)
87{
88 arbiter_reserve(&channel_arbiter, channel);
89}
90
91static enum imx233_dcp_error_t get_error_status(int ch)
92{
93 uint32_t stat = channel_packet[ch].status;
94 if(stat & HW_DCP_STATUS__ERROR_SETUP)
95 return DCP_ERROR_SETUP;
96 if(stat & HW_DCP_STATUS__ERROR_PACKET)
97 return DCP_ERROR_PACKET;
98 if(stat & HW_DCP_STATUS__ERROR_SRC)
99 return DCP_ERROR_SRC;
100 if(stat & HW_DCP_STATUS__ERROR_DST)
101 return DCP_ERROR_DST;
102 switch(__XTRACT_EX(stat, HW_DCP_STATUS__ERROR_CODE))
103 {
104 case 0: return DCP_SUCCESS;
105 case 1: return DCP_ERROR_CHAIN_IS_0;
106 case 2: return DCP_ERROR_NO_CHAIN;
107 case 3: return DCP_ERROR_CONTEXT;
108 case 4: return DCP_ERROR_PAYLOAD;
109 case 5: return DCP_ERROR_MODE;
110 default: return DCP_ERROR;
111 }
112}
113
114enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int ch, void *src, void *dst, size_t len)
115{
116 /* enable channel, clear interrupt, enable interrupt */
117 imx233_enable_interrupt(INT_SRC_DCP, true);
118 __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
119 __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch);
120 __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
121
122 /* prepare packet */
123 channel_packet[ch].next = 0;
124 channel_packet[ch].ctrl0 = HW_DCP_CTRL0__INTERRUPT_ENABLE |
125 HW_DCP_CTRL0__ENABLE_MEMCOPY | HW_DCP_CTRL0__DECR_SEMAPHORE;
126 channel_packet[ch].ctrl1 = 0;
127 channel_packet[ch].src = (uint32_t)PHYSICAL_ADDR(src);
128 channel_packet[ch].dst = (uint32_t)PHYSICAL_ADDR(dst);
129 channel_packet[ch].size = len;
130 channel_packet[ch].payload = 0;
131 channel_packet[ch].status = 0;
132
133 /* write-back src, discard dst, write-back packet */
134 commit_discard_dcache_range(src, len);
135 discard_dcache_range(dst, len);
136 commit_discard_dcache_range(&channel_packet[ch], sizeof(struct imx233_dcp_packet_t));
137 /* write 1 to semaphore to run job */
138 HW_DCP_CHxCMDPTR(ch) = (uint32_t)PHYSICAL_ADDR(&channel_packet[ch]);
139 HW_DCP_CHxSEMA(ch) = 1;
140 /* wait completion */
141 semaphore_wait(&channel_sema[ch], TIMEOUT_BLOCK);
142 /* read status */
143 return get_error_status(ch);
144}
145
146enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo)
147{
148 int chan = imx233_dcp_acquire_channel(tmo);
149 if(chan == OBJ_WAIT_TIMEDOUT)
150 return DCP_TIMEOUT;
151 enum imx233_dcp_error_t err = imx233_dcp_memcpy_ex(chan, src, dst, len);
152 imx233_dcp_release_channel(chan);
153 return err;
154}
155
156struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags)
157{
158 struct imx233_dcp_info_t info;
159 memset(&info, 0, sizeof(info));
160 if(flags & DCP_INFO_CAPABILITIES)
161 {
162 info.has_crypto = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CRYPTO;
163 info.has_csc = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CSC;
164 info.num_keys = __XTRACT(HW_DCP_CAPABILITY0, NUM_KEYS);
165 info.num_channels = __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS);
166 info.ciphers = __XTRACT(HW_DCP_CAPABILITY1, CIPHER_ALGORITHMS);
167 info.hashs = __XTRACT(HW_DCP_CAPABILITY1, HASH_ALGORITHMS);
168 }
169 if(flags & DCP_INFO_GLOBAL_STATE)
170 {
171 info.otp_key_ready = HW_DCP_STAT & HW_DCP_STAT__OTP_KEY_READY;
172 info.context_switching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
173 info.context_caching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_CACHING;
174 info.gather_writes = HW_DCP_CTRL & HW_DCP_CTRL__GATHER_RESIDUAL_WRITES;
175 info.ch0_merged = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
176 }
177 if(flags & DCP_INFO_CHANNELS)
178 {
179 for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
180 {
181 info.channel[i].irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(i);
182 info.channel[i].irq = HW_DCP_STAT & HW_DCP_STAT__IRQ(i);
183 info.channel[i].ready = HW_DCP_STAT & HW_DCP_STAT__READY_CHANNELS(i);
184 info.channel[i].high_priority = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(i);
185 info.channel[i].enable = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(i);
186 info.channel[i].sema = __XTRACT_EX(HW_DCP_CHxSEMA(i), HW_DCP_CHxSEMA__VALUE);
187 info.channel[i].cmdptr = HW_DCP_CHxCMDPTR(i);
188 }
189 }
190 if(flags & DCP_INFO_CSC)
191 {
192 info.csc.irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CSC_INTERRUPT_ENABLE;
193 info.csc.irq = HW_DCP_STAT & HW_DCP_STAT__CSCIRQ;
194 info.csc.priority = __XTRACT(HW_DCP_CHANNELCTRL, CSC_PRIORITY);
195 info.csc.enable = HW_DCP_CSCCTRL0 & HW_DCP_CSCCTRL0__ENABLE;
196 }
197 return info;
198} \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-17 21:29:09 +0000