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Diffstat (limited to 'firmware/target/arm/imx233/power-imx233.h')
-rw-r--r--firmware/target/arm/imx233/power-imx233.h45
1 files changed, 30 insertions, 15 deletions
diff --git a/firmware/target/arm/imx233/power-imx233.h b/firmware/target/arm/imx233/power-imx233.h
index b38f9e576b..6991fde7b2 100644
--- a/firmware/target/arm/imx233/power-imx233.h
+++ b/firmware/target/arm/imx233/power-imx233.h
@@ -77,6 +77,8 @@
77#define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40)) 77#define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40))
78#define HW_POWER_VDDDCTRL__TRG_BP 0 78#define HW_POWER_VDDDCTRL__TRG_BP 0
79#define HW_POWER_VDDDCTRL__TRG_BM 0x1f 79#define HW_POWER_VDDDCTRL__TRG_BM 0x1f
80#define HW_POWER_VDDDCTRL__BO_OFFSET_BP 8
81#define HW_POWER_VDDDCTRL__BO_OFFSET_BM (0x7 << 8)
80#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */ 82#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
81#define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */ 83#define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */
82#define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16 84#define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16
@@ -86,6 +88,8 @@
86#define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50)) 88#define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50))
87#define HW_POWER_VDDACTRL__TRG_BP 0 89#define HW_POWER_VDDACTRL__TRG_BP 0
88#define HW_POWER_VDDACTRL__TRG_BM 0x1f 90#define HW_POWER_VDDACTRL__TRG_BM 0x1f
91#define HW_POWER_VDDACTRL__BO_OFFSET_BP 8
92#define HW_POWER_VDDACTRL__BO_OFFSET_BM (0x7 << 8)
89#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */ 93#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
90#define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */ 94#define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */
91#define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12 95#define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12
@@ -95,6 +99,8 @@
95#define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60)) 99#define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60))
96#define HW_POWER_VDDIOCTRL__TRG_BP 0 100#define HW_POWER_VDDIOCTRL__TRG_BP 0
97#define HW_POWER_VDDIOCTRL__TRG_BM 0x1f 101#define HW_POWER_VDDIOCTRL__TRG_BM 0x1f
102#define HW_POWER_VDDIOCTRL__BO_OFFSET_BP 8
103#define HW_POWER_VDDIOCTRL__BO_OFFSET_BM (0x7 << 8)
98#define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */ 104#define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */
99#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */ 105#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
100#define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP 12 106#define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP 12
@@ -173,10 +179,33 @@ void imx233_power_set_charge_current(unsigned current); /* in mA */
173void imx233_power_set_stop_current(unsigned current); /* in mA */ 179void imx233_power_set_stop_current(unsigned current); /* in mA */
174void imx233_power_enable_batadj(bool enable); 180void imx233_power_enable_batadj(bool enable);
175 181
182enum imx233_regulator_t
183{
184 REGULATOR_VDDD, /* target, brownout, linreg, linreg offset */
185 REGULATOR_VDDA, /* target, brownout, linreg, linreg offset */
186 REGULATOR_VDDIO, /* target, brownout, linreg offset */
187 REGULATOR_VDDMEM, /* target, linreg */
188 REGULATOR_COUNT,
189};
190
191void imx233_power_get_regulator(enum imx233_regulator_t reg, unsigned *target_mv,
192 unsigned *brownout_mv);
193
194void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned target_mv,
195 unsigned brownout_mv);
196
197// offset is -1,0 or 1
198void imx233_power_get_regulator_linreg(enum imx233_regulator_t reg,
199 bool *enabled, int *linreg_offset);
200
201// offset is -1,0 or 1
202void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg,
203 bool enabled, int linreg_offset);
204
176static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq) 205static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq)
177{ 206{
178 HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM); 207 HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM);
179 /* WARNING: HW_POWER_MISC does have a SET/CLR variant ! */ 208 /* WARNING: HW_POWER_MISC does not have a SET/CLR variant ! */
180 if(pll) 209 if(pll)
181 { 210 {
182 HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP; 211 HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP;
@@ -186,16 +215,6 @@ static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq)
186 215
187struct imx233_power_info_t 216struct imx233_power_info_t
188{ 217{
189 int vddd; /* in mV */
190 bool vddd_linreg; /* VDDD source: linreg from VDDA or DC-DC */
191 int vddd_linreg_offset;
192 int vdda; /* in mV */
193 bool vdda_linreg; /* VDDA source: linreg from VDDIO or DC-DC */
194 int vdda_linreg_offset;
195 int vddio; /* in mV */
196 int vddio_linreg_offset;
197 int vddmem; /* in mV */
198 bool vddmem_linreg; /* VDDMEM source: linreg from VDDIO or off */
199 bool dcdc_sel_pllclk; /* clock source of DC-DC: pll or 24MHz xtal */ 218 bool dcdc_sel_pllclk; /* clock source of DC-DC: pll or 24MHz xtal */
200 int dcdc_freqsel; 219 int dcdc_freqsel;
201 int charge_current; 220 int charge_current;
@@ -215,10 +234,6 @@ struct imx233_power_info_t
215 bool _5v_vbus_cmps; 234 bool _5v_vbus_cmps;
216}; 235};
217 236
218#define POWER_INFO_VDDD (1 << 0)
219#define POWER_INFO_VDDA (1 << 1)
220#define POWER_INFO_VDDIO (1 << 2)
221#define POWER_INFO_VDDMEM (1 << 3)
222#define POWER_INFO_DCDC (1 << 4) 237#define POWER_INFO_DCDC (1 << 4)
223#define POWER_INFO_CHARGE (1 << 5) 238#define POWER_INFO_CHARGE (1 << 5)
224#define POWER_INFO_4P2 (1 << 6) 239#define POWER_INFO_4P2 (1 << 6)