1 files changed, 19 insertions, 2 deletions

diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 6d16c1bfca..75539ba8d7 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -161,7 +161,7 @@ void fiq_handler(void)
     );
 }
 
-#ifdef BOOTLOADER
+#if defined(BOOTLOADER) && (CONFIG_CPU == AS3525) /* not v2 */
 static void sdram_delay(void)
 {
     int delay = 1024; /* arbitrary */
@@ -205,7 +205,7 @@ static void sdram_init(void)
 /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
 #define MEMORY_MODEL 0x21
 
-#elif defined(SANSA_E200V2) || defined(SANSA_FUZE)
+#elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2)
 /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
 #define MEMORY_MODEL 0x5
 
@@ -256,6 +256,21 @@ void memory_init(void)
 
 void system_init(void)
 {
+#ifdef SANSA_CLIPV2
+    /* Init procedure isn't fully understood yet
+     * CCU_* registers differ from AS3525
+     */
+    unsigned int reset_loops = 640;
+
+    CCU_SRC = 0x57D7BF0;
+    while(reset_loops--)
+        CCU_SRL = CCU_SRL_MAGIC_NUMBER;
+    CCU_SRC = CCU_SRL = 0;
+
+    CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
+    CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
+                | 1; /* clk_in = PLLA */
+#else   /* SANSA_CLIPV2 */
     unsigned int reset_loops = 640;
 
     CCU_SRC = 0x1fffff0
@@ -293,6 +308,8 @@ void system_init(void)
     sdram_init();
 #endif  /* BOOTLOADER */
 
+#endif /* SANSA_CLIPV2 */
+
 #if 0 /* the GPIO clock is already enabled by the dualboot function */
     CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
 #endif