diff options
Diffstat (limited to 'firmware/target/arm/as3525/sansa-clipv2/sd-clipv2.c')
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipv2/sd-clipv2.c | 777 |
1 files changed, 777 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipv2/sd-clipv2.c b/firmware/target/arm/as3525/sansa-clipv2/sd-clipv2.c new file mode 100644 index 0000000000..70c0477431 --- /dev/null +++ b/firmware/target/arm/as3525/sansa-clipv2/sd-clipv2.c | |||
@@ -0,0 +1,777 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 Daniel Ankers | ||
11 | * Copyright © 2008-2009 Rafaël Carré | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License | ||
15 | * as published by the Free Software Foundation; either version 2 | ||
16 | * of the License, or (at your option) any later version. | ||
17 | * | ||
18 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
19 | * KIND, either express or implied. | ||
20 | * | ||
21 | ****************************************************************************/ | ||
22 | |||
23 | #include "config.h" /* for HAVE_MULTIVOLUME */ | ||
24 | #include "fat.h" | ||
25 | #include "thread.h" | ||
26 | #include "hotswap.h" | ||
27 | #include "system.h" | ||
28 | #include "kernel.h" | ||
29 | #include "cpu.h" | ||
30 | #include <stdio.h> | ||
31 | #include <stdlib.h> | ||
32 | #include <string.h> | ||
33 | #include "as3525v2.h" | ||
34 | #include "pl081.h" /* DMA controller */ | ||
35 | #include "dma-target.h" /* DMA request lines */ | ||
36 | #include "clock-target.h" | ||
37 | #include "panic.h" | ||
38 | #include "stdbool.h" | ||
39 | #include "ata_idle_notify.h" | ||
40 | #include "sd.h" | ||
41 | |||
42 | #include "lcd.h" | ||
43 | #include <stdarg.h> | ||
44 | #include "sysfont.h" | ||
45 | |||
46 | static int line = 0; | ||
47 | static void printf(const char *format, ...) | ||
48 | { | ||
49 | char buf[50]; | ||
50 | int len; | ||
51 | va_list ap; | ||
52 | va_start(ap, format); | ||
53 | |||
54 | len = vsnprintf(buf, sizeof(buf), format, ap); | ||
55 | va_end(ap); | ||
56 | |||
57 | lcd_puts(0, line++, buf); | ||
58 | lcd_update(); | ||
59 | if(line >= LCD_HEIGHT/SYSFONT_HEIGHT) | ||
60 | line = 0; | ||
61 | } | ||
62 | |||
63 | /* command flags */ | ||
64 | #define MCI_NO_RESP (0<<0) | ||
65 | #define MCI_RESP (1<<0) | ||
66 | #define MCI_LONG_RESP (1<<1) | ||
67 | |||
68 | /* controller registers */ | ||
69 | #define SD_BASE 0xC6070000 | ||
70 | |||
71 | /* | ||
72 | * REGISTERS | ||
73 | * | ||
74 | * m = modify (orr/bic), r = read, w = write | ||
75 | * | ||
76 | * 00 m/r/w | ||
77 | * 04 m/w | ||
78 | * 08 m | ||
79 | * 0C ? | ||
80 | * 10 r/w | ||
81 | * 14 w | ||
82 | * 18 m | ||
83 | * 1C w ==> set a bit before transfer (sometimes) ! | ||
84 | * 20 w ==> set a bit before transfer ! | ||
85 | * 24 w irq mask ? | ||
86 | * 28 w arg | ||
87 | * 2C r/w cmd | ||
88 | * 30 r resp0 | ||
89 | * 34 r resp1 | ||
90 | * 38 r resp2 | ||
91 | * 3C r resp3 | ||
92 | * 40 r irq status (only read in isr) | ||
93 | * 44 m/w irq clear | ||
94 | * 48 r | ||
95 | * 4C m | ||
96 | * 64 w | ||
97 | * 70 r | ||
98 | * 100 FIFO | ||
99 | */ | ||
100 | |||
101 | /* | ||
102 | * STATUS register | ||
103 | * & 0xBA80 | ||
104 | * & 8 | ||
105 | * & 0x428 | ||
106 | * & 0x418 | ||
107 | */ | ||
108 | |||
109 | /* | ||
110 | * INFO on CMD register | ||
111 | * | ||
112 | * if(cmd >= 200) cmd -= 200; (>= 200 = acmd?) | ||
113 | * | ||
114 | * COMMANDS (| (x<<16) BITS RESPONSE | ||
115 | * | ||
116 | * 1 ? reserved & ~0x80, | 0x40, | 0x8000 ? | ||
117 | * 5 ? reserved for I/O cards & ~0x80, | 0x40 ? | ||
118 | * 11 ? reserved & ~0x80, | 0x40, | 0x2200, | 0x800 ? | ||
119 | * 14 ? reserved & ~0x80, | 0x40, | 0x2200, ~0x1000 ? | ||
120 | * 19 ? reserved & ~0x80, |0x40, | 0x2700, & ~0x1000 ? | ||
121 | * 20 ? reserved & ~0x80, |0x40, | 0x2700, | 0x800 ? | ||
122 | * 23 ? reserved & ~0x80, | 0x40 ? | ||
123 | * 39 ? reserved & ~0x80, | 0x40 ? | ||
124 | * 51 ? reserved & ~0x80, | 0x40, | 0x2000, | 0x200 ? | ||
125 | * 52 ? reserved for I/O & ~0x80, | 0x40 ? | ||
126 | * 53 ? reserved for I/O & ~0x80, | 0x40, | 0x2200, & ~0x1000 ? | ||
127 | * 253 ? & ~0x80, |0x40, | 0x2700, & ~0x1000 ? | ||
128 | * | ||
129 | * 0 GO IDLE STATE & ~0x4000, & ~0xC0, | 0x4000 no | ||
130 | * 2 ALL SEND CID & ~0x4000, |0xC0 r2 | ||
131 | * 3 SEND RCA & ~0x80, | 0x40 r6 | ||
132 | * 6 SWITCH_FUNC & ~0x80, | 0x40 r1 | ||
133 | * 7 SELECT CARD & ~0x80, | 0x40 r1b | ||
134 | * 8 SEND IF COND & ~0x80, | 0x40, | 0x2200, & ~0x1000 r7 | ||
135 | * 9 SEND CSD & ~0x4000, | 0xc0 r2 | ||
136 | * 12 STOP TRANSMISSION & ~0x80, | 0x40, | 0x4000 r1b | ||
137 | * 13 SEND STATUS & ~0x80, | 0x40 r1 | ||
138 | * 15 GO INACTIVE STATE & ~0x4000, & ~0xC0 no | ||
139 | * 16 SET BLOCKLEN & ~0x80, | 0x40 r1 | ||
140 | * 17 READ SINGLE BLOCK & ~0x80, | 0x40, | 0x2200 r1 | ||
141 | * 18 READ MULTIPLE BLOCK & ~0x80, | 0x40, | 0x2200 r1 | ||
142 | * 24 WRITE BLOCK & ~0x80, |0x40, | 0x2700 r1 | ||
143 | * 25 WRITE MULTIPLE BLOCK & ~0x80, |0x40, | 0x2700 r1 | ||
144 | * 41 SEND APP OP COND & ~0x80, | 0x40 r3 | ||
145 | * 42 LOCK UNLOCK & ~0x80, |0x40, | 0x2700 r1 | ||
146 | * 55 APP CMD & ~0x80, | 0x40 r1 | ||
147 | * 206 SET BUS WIDTH & ~0x80, | 0x40, | 0x2000 r1 | ||
148 | * 207 SELECT CARD ? & ~0x4000, & ~0xC0 r1b | ||
149 | * | ||
150 | * | ||
151 | * bits 5:0 = cmd | ||
152 | * bit 6 (0x40) = response | ||
153 | * bit 7 (0x80) = long response | ||
154 | * => like pl180 <= | ||
155 | * BIT SET IN COMANDS: | ||
156 | * | ||
157 | * bit 8 (0x100) ? write block, write multi_block, lock/unlock | ||
158 | * bit 9 (0x200) ? send if cond, read block, read multi_block, write block, write multi_block, lock/unlock | ||
159 | * bit 10 (0x400) ? write block, write multi_block, lock/unlock | ||
160 | * bit 11 (0x800) ? | ||
161 | * bit 12 (0x1000) ? | ||
162 | * bit 13 (0x2000) ? send if cond, read block, read multi_block, write block, write multi_block, lock/unlock, set bus width | ||
163 | * bit 14 (0x4000) ? go idle state, stop transmission | ||
164 | * bit 15 (0x8000) ? | ||
165 | * | ||
166 | */ | ||
167 | |||
168 | /* FIXME */ | ||
169 | #define MCI_POWER | ||
170 | #define MCI_CLOCK | ||
171 | #define MCI_ARGUMENT (*(volatile unsigned long *) (SD_BASE+0x28)) | ||
172 | #define MCI_COMMAND (*(volatile unsigned long *) (SD_BASE+0x2C)) | ||
173 | #define MCI_RESPCMD | ||
174 | #define MCI_RESP0 (*(volatile unsigned long *) (SD_BASE+0x30)) | ||
175 | #define MCI_RESP1 (*(volatile unsigned long *) (SD_BASE+0x34)) | ||
176 | #define MCI_RESP2 (*(volatile unsigned long *) (SD_BASE+0x38)) | ||
177 | #define MCI_RESP3 (*(volatile unsigned long *) (SD_BASE+0x3C)) | ||
178 | #define MCI_DATA_TIMER | ||
179 | #define MCI_DATA_LENGTH | ||
180 | #define MCI_DATA_CTRL | ||
181 | #define MCI_STATUS (*(volatile unsigned long *) (SD_BASE+0x40)) | ||
182 | #define MCI_CLEAR (*(volatile unsigned long *) (SD_BASE+0x44)) | ||
183 | #define MCI_MASK (*(volatile unsigned long *) (SD_BASE+0x24)) | ||
184 | #define MCI_SELECT | ||
185 | |||
186 | #define MCI_ERROR 0 /* FIXME */ | ||
187 | |||
188 | #define MCI_FIFO ((unsigned long *) (SD_BASE+0x100)) | ||
189 | |||
190 | #define MCI_COMMAND_ENABLE (1<<31) | ||
191 | #define MCI_COMMAND_ACTIVE MCI_COMMAND_ENABLE | ||
192 | #define MCI_COMMAND_RESPONSE (1<<6) | ||
193 | #define MCI_COMMAND_LONG_RESPONSE (1<<7) | ||
194 | |||
195 | |||
196 | |||
197 | static int sd_init_card(void); | ||
198 | static void init_controller(void); | ||
199 | |||
200 | static tCardInfo card_info; | ||
201 | |||
202 | /* for compatibility */ | ||
203 | static long last_disk_activity = -1; | ||
204 | |||
205 | #define MIN_YIELD_PERIOD 5 /* ticks */ | ||
206 | static long next_yield = 0; | ||
207 | |||
208 | static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)]; | ||
209 | static const char sd_thread_name[] = "ata/sd"; | ||
210 | static struct mutex sd_mtx SHAREDBSS_ATTR; | ||
211 | static struct event_queue sd_queue; | ||
212 | #ifndef BOOTLOADER | ||
213 | static bool sd_enabled = false; | ||
214 | #endif | ||
215 | |||
216 | static struct wakeup transfer_completion_signal; | ||
217 | static volatile bool retry; | ||
218 | |||
219 | static inline void mci_delay(void) { int i = 0xffff; while(i--) ; } | ||
220 | |||
221 | void INT_NAND(void) | ||
222 | { | ||
223 | (*(volatile unsigned long *) (SD_BASE+0x0)) &= ~0x10; // ? | ||
224 | const int status = MCI_STATUS; | ||
225 | |||
226 | #if 0 | ||
227 | if(status & MCI_ERROR) | ||
228 | retry = true; | ||
229 | #endif | ||
230 | |||
231 | // wakeup_signal(&transfer_completion_signal); | ||
232 | MCI_CLEAR = status; | ||
233 | |||
234 | static int x = 0; | ||
235 | switch(status) | ||
236 | { | ||
237 | case 0x4: /* cmd received ? */ | ||
238 | case 0x104: /* ? 1 time in init (10th interrupt) */ | ||
239 | case 0x2000: /* ? after cmd read_mul_blocks | 0x2200 */ | ||
240 | |||
241 | case 0x820: /* ? 1 time while copy from FIFO (not DMA) */ | ||
242 | case 0x20: /* ? rx fifo empty */ | ||
243 | break; | ||
244 | default: | ||
245 | printf("%2d NAND 0x%x", ++x, status); | ||
246 | int delay = 0x100000; while(delay--) ; | ||
247 | } | ||
248 | /* | ||
249 | * 0x48 = some kind of status | ||
250 | * 0x106 | ||
251 | * 0x4106 | ||
252 | * 1B906 | ||
253 | * 1F906 | ||
254 | * 1B906 | ||
255 | * 1F906 | ||
256 | * 1F906 | ||
257 | * 1906 | ||
258 | * ... | ||
259 | * 6906 | ||
260 | * 6D06 (dma) | ||
261 | * | ||
262 | * read resp (6, 7, 12, 42) : while bit 9 is unset ; | ||
263 | * | ||
264 | */ | ||
265 | printf("%x %x", status, (*(volatile unsigned long *) (SD_BASE+0x48))); | ||
266 | //while(!button_read_device()); | ||
267 | //while(button_read_device()); | ||
268 | |||
269 | (*(volatile unsigned long *) (SD_BASE+0x0)) |= 0x10; // ? | ||
270 | } | ||
271 | |||
272 | static bool send_cmd(const int cmd, const int arg, const int flags, | ||
273 | unsigned long *response) | ||
274 | { | ||
275 | int val; | ||
276 | val = cmd | MCI_COMMAND_ENABLE; | ||
277 | if(flags & MCI_RESP) | ||
278 | { | ||
279 | val |= MCI_COMMAND_RESPONSE; | ||
280 | if(flags & MCI_LONG_RESP) | ||
281 | val |= MCI_COMMAND_LONG_RESPONSE; | ||
282 | } | ||
283 | |||
284 | if(cmd == 18) /* r */ | ||
285 | val |= 0x2200; | ||
286 | else if(cmd == 25) /* w */ | ||
287 | val |= 0x2700; | ||
288 | |||
289 | int tmp = (*(volatile unsigned long *) (SD_BASE+0x10)); | ||
290 | (*(volatile unsigned long *) (SD_BASE+0x10)) = 0; | ||
291 | |||
292 | MCI_COMMAND = 0x80202000; | ||
293 | MCI_ARGUMENT = 0; | ||
294 | int max = 10; | ||
295 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); | ||
296 | |||
297 | (*(volatile unsigned long *) (SD_BASE+0x08)) &= ~0xff; | ||
298 | (*(volatile unsigned long *) (SD_BASE+0x08)) |= 0; | ||
299 | |||
300 | MCI_COMMAND = 0x80202000; | ||
301 | MCI_ARGUMENT = 0; | ||
302 | max = 10; | ||
303 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); | ||
304 | |||
305 | (*(volatile unsigned long *) (SD_BASE+0x10)) = tmp; | ||
306 | |||
307 | MCI_COMMAND = 0x80202000; | ||
308 | MCI_ARGUMENT = 0; | ||
309 | max = 10; | ||
310 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); | ||
311 | |||
312 | mci_delay(); | ||
313 | |||
314 | MCI_ARGUMENT = arg; | ||
315 | MCI_COMMAND = val; | ||
316 | |||
317 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10; | ||
318 | |||
319 | max = 1000; | ||
320 | while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */ | ||
321 | if(!max) | ||
322 | return false; | ||
323 | |||
324 | if(flags & MCI_RESP) | ||
325 | { | ||
326 | if(flags & MCI_LONG_RESP) | ||
327 | { | ||
328 | /* store the response in little endian order for the words */ | ||
329 | response[0] = MCI_RESP3; | ||
330 | response[1] = MCI_RESP2; | ||
331 | response[2] = MCI_RESP1; | ||
332 | response[3] = MCI_RESP0; | ||
333 | } | ||
334 | else | ||
335 | response[0] = MCI_RESP0; | ||
336 | } | ||
337 | return true; | ||
338 | } | ||
339 | |||
340 | static int sd_init_card(void) | ||
341 | { | ||
342 | unsigned long response; | ||
343 | unsigned long temp_reg[4]; | ||
344 | int max_tries = 100; /* max acmd41 attemps */ | ||
345 | bool sdhc; | ||
346 | int i; | ||
347 | |||
348 | if(!send_cmd(SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL)) | ||
349 | return -1; | ||
350 | |||
351 | mci_delay(); | ||
352 | |||
353 | sdhc = false; | ||
354 | if(send_cmd(SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response)) | ||
355 | if((response & 0xFFF) == 0x1AA) | ||
356 | sdhc = true; | ||
357 | |||
358 | do { | ||
359 | /* some MicroSD cards seems to need more delays, so play safe */ | ||
360 | mci_delay(); | ||
361 | mci_delay(); | ||
362 | mci_delay(); | ||
363 | |||
364 | /* app_cmd */ | ||
365 | if( !send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) /*|| | ||
366 | !(response & (1<<5))*/ ) | ||
367 | { | ||
368 | return -2; | ||
369 | } | ||
370 | |||
371 | /* acmd41 */ | ||
372 | if(!send_cmd(SD_APP_OP_COND, (sdhc ? 0x40FF8000 : (1<<23)), | ||
373 | MCI_RESP, &card_info.ocr)) | ||
374 | return -3; | ||
375 | } while(!(card_info.ocr & (1<<31)) && max_tries--); | ||
376 | |||
377 | if(max_tries < 0) | ||
378 | return -4; | ||
379 | |||
380 | mci_delay(); | ||
381 | mci_delay(); | ||
382 | mci_delay(); | ||
383 | |||
384 | /* send CID */ | ||
385 | if(!send_cmd(SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info.cid)) | ||
386 | return -5; | ||
387 | |||
388 | /* send RCA */ | ||
389 | if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info.rca)) | ||
390 | return -6; | ||
391 | |||
392 | /* send CSD */ | ||
393 | if(!send_cmd(SD_SEND_CSD, card_info.rca, | ||
394 | MCI_RESP|MCI_LONG_RESP, temp_reg)) | ||
395 | return -7; | ||
396 | |||
397 | for(i=0; i<4; i++) | ||
398 | card_info.csd[3-i] = temp_reg[i]; | ||
399 | |||
400 | sd_parse_csd(&card_info); | ||
401 | |||
402 | if(!send_cmd(SD_APP_CMD, 0, MCI_RESP, &response) || | ||
403 | !send_cmd(42, 0, MCI_NO_RESP, NULL)) /* disconnect the 50 KOhm pull-up | ||
404 | resistor on CD/DAT3 */ | ||
405 | return -13; | ||
406 | |||
407 | if(!send_cmd(SD_APP_CMD, card_info.rca, MCI_NO_RESP, NULL)) | ||
408 | return -10; | ||
409 | |||
410 | if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL)) | ||
411 | return -11; | ||
412 | |||
413 | (*(volatile unsigned long *) (SD_BASE+0x18)) &= ~(0x10001); | ||
414 | (*(volatile unsigned long *) (SD_BASE+0x18)) |= 0x1; | ||
415 | |||
416 | if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL)) | ||
417 | return -9; | ||
418 | |||
419 | /* not sent in init_card() by OF */ | ||
420 | if(!send_cmd(SD_SET_BLOCKLEN, card_info.blocksize, MCI_NO_RESP, | ||
421 | NULL)) | ||
422 | return -12; | ||
423 | |||
424 | card_info.initialized = 1; | ||
425 | |||
426 | return 0; | ||
427 | } | ||
428 | |||
429 | static void sd_thread(void) __attribute__((noreturn)); | ||
430 | static void sd_thread(void) | ||
431 | { | ||
432 | struct queue_event ev; | ||
433 | bool idle_notified = false; | ||
434 | |||
435 | while (1) | ||
436 | { | ||
437 | queue_wait_w_tmo(&sd_queue, &ev, HZ); | ||
438 | |||
439 | switch ( ev.id ) | ||
440 | { | ||
441 | case SYS_TIMEOUT: | ||
442 | if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ))) | ||
443 | { | ||
444 | idle_notified = false; | ||
445 | } | ||
446 | else | ||
447 | { | ||
448 | /* never let a timer wrap confuse us */ | ||
449 | next_yield = current_tick; | ||
450 | |||
451 | if (!idle_notified) | ||
452 | { | ||
453 | call_storage_idle_notifys(false); | ||
454 | idle_notified = true; | ||
455 | } | ||
456 | } | ||
457 | break; | ||
458 | #if 0 | ||
459 | case SYS_USB_CONNECTED: | ||
460 | usb_acknowledge(SYS_USB_CONNECTED_ACK); | ||
461 | /* Wait until the USB cable is extracted again */ | ||
462 | usb_wait_for_disconnect(&sd_queue); | ||
463 | |||
464 | break; | ||
465 | case SYS_USB_DISCONNECTED: | ||
466 | usb_acknowledge(SYS_USB_DISCONNECTED_ACK); | ||
467 | break; | ||
468 | #endif | ||
469 | } | ||
470 | } | ||
471 | } | ||
472 | |||
473 | static void init_controller(void) | ||
474 | { | ||
475 | int tmp = (*(volatile unsigned long *) (SD_BASE+0x70)); | ||
476 | int shift = 1 + ((tmp << 26) >> 27); | ||
477 | |||
478 | (*(volatile unsigned long *) (SD_BASE+0x04)) &= ~((1 << shift) -1); | ||
479 | (*(volatile unsigned long *) (SD_BASE+0x04)) = (1 << shift) -1; | ||
480 | |||
481 | mci_delay(); | ||
482 | |||
483 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 1; | ||
484 | int max = 1000; | ||
485 | while(max-- && !(*(volatile unsigned long *) (SD_BASE+0x00)) & 1) | ||
486 | ; | ||
487 | |||
488 | MCI_CLEAR = 0xffffffff; | ||
489 | MCI_MASK = 0xffffbffe; | ||
490 | |||
491 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10; | ||
492 | (*(volatile unsigned long *) (SD_BASE+0x14)) = 0xffffffff; | ||
493 | |||
494 | (*(volatile unsigned long *) (SD_BASE+0x10)) = (1<<shift) - 1; | ||
495 | |||
496 | MCI_ARGUMENT = 0; | ||
497 | MCI_COMMAND = 0x80202000; | ||
498 | max = 10; | ||
499 | while(max-- && (MCI_COMMAND & (1<<31))) ; | ||
500 | |||
501 | (*(volatile unsigned long *) (SD_BASE+0x64)) = 0xfffff; | ||
502 | |||
503 | (*(volatile unsigned long *) (SD_BASE+0x4c)) = ~0x7fff0fff; // interrupt mask ? | ||
504 | (*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080; | ||
505 | |||
506 | MCI_MASK = 0xffffbffe; | ||
507 | } | ||
508 | |||
509 | int sd_init(void) | ||
510 | { | ||
511 | int ret; | ||
512 | CGU_PERI |= CGU_MCI_CLOCK_ENABLE; | ||
513 | |||
514 | CGU_IDE = (1<<7) /* AHB interface enable */ | | ||
515 | (1<<6) /* interface enable */ | | ||
516 | ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) | | ||
517 | 1; /* clock source = PLLA */ | ||
518 | |||
519 | CGU_MEMSTICK = (1<<8) | (1<<7) | | ||
520 | (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) | 1; | ||
521 | |||
522 | /* ?? */ | ||
523 | *(volatile int*)0xC80F003C = (1<<7) | | ||
524 | (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1) | 1; | ||
525 | |||
526 | wakeup_init(&transfer_completion_signal); | ||
527 | |||
528 | VIC_INT_ENABLE |= INTERRUPT_NAND; | ||
529 | |||
530 | init_controller(); | ||
531 | ret = sd_init_card(); | ||
532 | if(ret < 0) | ||
533 | return ret; | ||
534 | |||
535 | /* init mutex */ | ||
536 | mutex_init(&sd_mtx); | ||
537 | |||
538 | queue_init(&sd_queue, true); | ||
539 | create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0, | ||
540 | sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU)); | ||
541 | |||
542 | #ifndef BOOTLOADER | ||
543 | sd_enabled = true; | ||
544 | sd_enable(false); | ||
545 | #endif | ||
546 | return 0; | ||
547 | } | ||
548 | |||
549 | #ifdef STORAGE_GET_INFO | ||
550 | void sd_get_info(struct storage_info *info) | ||
551 | { | ||
552 | info->sector_size=card_info.blocksize; | ||
553 | info->num_sectors=card_info.numblocks; | ||
554 | info->vendor="Rockbox"; | ||
555 | info->product = "Internal Storage"; | ||
556 | info->revision="0.00"; | ||
557 | } | ||
558 | #endif | ||
559 | |||
560 | static int sd_wait_for_state(unsigned int state) | ||
561 | { | ||
562 | unsigned long response; | ||
563 | unsigned int timeout = 100; /* ticks */ | ||
564 | long t = current_tick; | ||
565 | |||
566 | while (1) | ||
567 | { | ||
568 | long tick; | ||
569 | |||
570 | if(!send_cmd(SD_SEND_STATUS, card_info.rca, | ||
571 | MCI_RESP, &response)) | ||
572 | return -1; | ||
573 | |||
574 | if (((response >> 9) & 0xf) == state) | ||
575 | return 0; | ||
576 | |||
577 | if(TIME_AFTER(current_tick, t + timeout)) | ||
578 | return -10 * ((response >> 9) & 0xf); | ||
579 | |||
580 | if (TIME_AFTER((tick = current_tick), next_yield)) | ||
581 | { | ||
582 | yield(); | ||
583 | timeout += current_tick - tick; | ||
584 | next_yield = tick + MIN_YIELD_PERIOD; | ||
585 | } | ||
586 | } | ||
587 | } | ||
588 | |||
589 | static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool write) | ||
590 | { | ||
591 | int ret = 0; | ||
592 | |||
593 | if((int)buf & 3) | ||
594 | panicf("unaligned transfer"); | ||
595 | |||
596 | /* skip SanDisk OF */ | ||
597 | start += 0xf000; | ||
598 | |||
599 | mutex_lock(&sd_mtx); | ||
600 | #ifndef BOOTLOADER | ||
601 | sd_enable(true); | ||
602 | #endif | ||
603 | |||
604 | if (card_info.initialized <= 0) | ||
605 | { | ||
606 | ret = sd_init_card(); | ||
607 | if (!(card_info.initialized)) | ||
608 | { | ||
609 | panicf("card not initialised (%d)", ret); | ||
610 | goto sd_transfer_error; | ||
611 | } | ||
612 | } | ||
613 | |||
614 | last_disk_activity = current_tick; | ||
615 | ret = sd_wait_for_state(SD_TRAN); | ||
616 | if (ret < 0) | ||
617 | { | ||
618 | static const char *st[9] = { | ||
619 | "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV", "PRG", "DIS" | ||
620 | }; | ||
621 | if(ret <= -10) | ||
622 | panicf("wait for state failed (%s)", st[(-ret / 10) % 9]); | ||
623 | else | ||
624 | panicf("wait for state failed"); | ||
625 | goto sd_transfer_error; | ||
626 | } | ||
627 | |||
628 | dma_retain(); | ||
629 | |||
630 | while(count) | ||
631 | { | ||
632 | /* Interrupt handler might set this to true during transfer */ | ||
633 | retry = false; | ||
634 | /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH | ||
635 | * register, so we have to transfer maximum 127 sectors at a time. */ | ||
636 | //unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */ | ||
637 | unsigned int transfer = count; | ||
638 | |||
639 | const int cmd = | ||
640 | write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; | ||
641 | |||
642 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 2; | ||
643 | while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ; | ||
644 | |||
645 | //(*(volatile unsigned long *) (SD_BASE+0x1c)) = 512; | ||
646 | (*(volatile unsigned long *) (SD_BASE+0x20)) = transfer * 512; | ||
647 | |||
648 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 2; | ||
649 | while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ; | ||
650 | |||
651 | (*(volatile unsigned long *) (SD_BASE+0x4c)) &= ~0x7fff0fff; | ||
652 | |||
653 | if(0) | ||
654 | { | ||
655 | (*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x20; | ||
656 | MCI_MASK = 0xBE8C; | ||
657 | (*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080; | ||
658 | } | ||
659 | else | ||
660 | { | ||
661 | MCI_MASK = 0xBEB8; | ||
662 | (*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x3f0030; | ||
663 | } | ||
664 | |||
665 | if(card_info.ocr & (1<<30) ) /* SDHC */ | ||
666 | ret = send_cmd(cmd, start, MCI_NO_RESP, NULL); | ||
667 | else | ||
668 | ret = send_cmd(cmd, start * SD_BLOCK_SIZE, | ||
669 | MCI_NO_RESP, NULL); | ||
670 | |||
671 | if (ret < 0) | ||
672 | panicf("transfer multiple blocks failed (%d)", ret); | ||
673 | |||
674 | if(write) | ||
675 | dma_enable_channel(0, buf, MCI_FIFO, DMA_PERI_SD, | ||
676 | DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); | ||
677 | else | ||
678 | dma_enable_channel(0, MCI_FIFO, buf, DMA_PERI_SD, | ||
679 | DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL); | ||
680 | |||
681 | line = 0; | ||
682 | lcd_clear_display(); | ||
683 | printf("dma ->"); | ||
684 | |||
685 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | ||
686 | |||
687 | printf("dma <-"); | ||
688 | int delay = 0x1000000; while(delay--) ; | ||
689 | |||
690 | if(!retry) | ||
691 | { | ||
692 | buf += transfer * SECTOR_SIZE; | ||
693 | start += transfer; | ||
694 | count -= transfer; | ||
695 | } | ||
696 | |||
697 | last_disk_activity = current_tick; | ||
698 | |||
699 | if(!send_cmd(SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL)) | ||
700 | { | ||
701 | ret = -666; | ||
702 | panicf("STOP TRANSMISSION failed"); | ||
703 | goto sd_transfer_error; | ||
704 | } | ||
705 | |||
706 | ret = sd_wait_for_state(SD_TRAN); | ||
707 | if (ret < 0) | ||
708 | { | ||
709 | panicf(" wait for state TRAN failed (%d)", ret); | ||
710 | goto sd_transfer_error; | ||
711 | } | ||
712 | } | ||
713 | |||
714 | dma_release(); | ||
715 | |||
716 | #ifndef BOOTLOADER | ||
717 | sd_enable(false); | ||
718 | #endif | ||
719 | mutex_unlock(&sd_mtx); | ||
720 | return 0; | ||
721 | |||
722 | sd_transfer_error: | ||
723 | panicf("transfer error : %d",ret); | ||
724 | card_info.initialized = 0; | ||
725 | return ret; | ||
726 | } | ||
727 | |||
728 | int sd_read_sectors(unsigned long start, int count, void* buf) | ||
729 | { | ||
730 | return sd_transfer_sectors(start, count, buf, false); | ||
731 | } | ||
732 | |||
733 | int sd_write_sectors(unsigned long start, int count, const void* buf) | ||
734 | { | ||
735 | #if defined(BOOTLOADER) /* we don't need write support in bootloader */ | ||
736 | (void) start; | ||
737 | (void) count; | ||
738 | (void) buf; | ||
739 | return -1; | ||
740 | #else | ||
741 | return sd_transfer_sectors(start, count, (void*)buf, true); | ||
742 | #endif | ||
743 | } | ||
744 | |||
745 | #ifndef BOOTLOADER | ||
746 | void sd_sleep(void) | ||
747 | { | ||
748 | } | ||
749 | |||
750 | void sd_spin(void) | ||
751 | { | ||
752 | } | ||
753 | |||
754 | void sd_spindown(int seconds) | ||
755 | { | ||
756 | (void)seconds; | ||
757 | } | ||
758 | |||
759 | long sd_last_disk_activity(void) | ||
760 | { | ||
761 | return last_disk_activity; | ||
762 | } | ||
763 | |||
764 | void sd_enable(bool on) | ||
765 | { | ||
766 | /* TODO */ | ||
767 | (void)on; | ||
768 | return; | ||
769 | } | ||
770 | |||
771 | tCardInfo *card_get_info_target(int card_no) | ||
772 | { | ||
773 | (void)card_no; | ||
774 | return &card_info; | ||
775 | } | ||
776 | |||
777 | #endif /* BOOTLOADER */ | ||