diff options
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 34 |
1 files changed, 7 insertions, 27 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 97d6edb3d1..f4bb5568fb 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -70,11 +70,8 @@ | |||
70 | * - bit 12 = unknown (always set to 1) | 70 | * - bit 12 = unknown (always set to 1) |
71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz | 71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz |
72 | */ | 72 | */ |
73 | #define AS3525_PLLA_FREQ 240000000 | 73 | #define AS3525_PLLA_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/ |
74 | #define AS3525_PLLA_SETTING 0x113B | 74 | #define AS3525_PLLA_SETTING 0x155F |
75 | |||
76 | #define AS3525_PLLB_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/ | ||
77 | #define AS3525_PLLB_SETTING 0x155F | ||
78 | 75 | ||
79 | #define AS3525_FCLK_PREDIV 0 | 76 | #define AS3525_FCLK_PREDIV 0 |
80 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ | 77 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ |
@@ -86,13 +83,9 @@ | |||
86 | * Also note that CGU_PERI is based on fclk, not PLLA | 83 | * Also note that CGU_PERI is based on fclk, not PLLA |
87 | */ | 84 | */ |
88 | 85 | ||
89 | #ifdef SANSA_FUZEV2 | 86 | |
90 | /* display is unbearably slow at 24MHz | 87 | |
91 | * 34285715 HZ works ok but 40MHz works even better*/ | 88 | #define AS3525_DRAM_FREQ 96000000 /* Initial DRAM frequency */ |
92 | #define AS3525_DRAM_FREQ 40000000 /* Initial DRAM frequency */ | ||
93 | #else | ||
94 | #define AS3525_DRAM_FREQ 24000000 /* Initial DRAM frequency */ | ||
95 | #endif /* SANSA_FUZEV2 */ | ||
96 | 89 | ||
97 | #else | 90 | #else |
98 | /* AS3525v1 */ | 91 | /* AS3525v1 */ |
@@ -131,8 +124,8 @@ | |||
131 | 124 | ||
132 | /* Tell the software what frequencies we're running */ | 125 | /* Tell the software what frequencies we're running */ |
133 | #define CPUFREQ_MAX AS3525_FCLK_FREQ | 126 | #define CPUFREQ_MAX AS3525_FCLK_FREQ |
134 | #define CPUFREQ_DEFAULT AS3525_PCLK_FREQ | 127 | #define CPUFREQ_DEFAULT 38400000 |
135 | #define CPUFREQ_NORMAL AS3525_PCLK_FREQ | 128 | #define CPUFREQ_NORMAL CPUFREQ_DEFAULT |
136 | 129 | ||
137 | /* FCLK */ | 130 | /* FCLK */ |
138 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | 131 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA |
@@ -145,21 +138,8 @@ | |||
145 | #endif /* CONFIG_CPU == AS3525v2 */ | 138 | #endif /* CONFIG_CPU == AS3525v2 */ |
146 | 139 | ||
147 | /* MCLK */ | 140 | /* MCLK */ |
148 | #if CONFIG_CPU == AS3525v2 | ||
149 | /* on AMSv2 we can enable PLLB for MCLK to increase PCM sample rate accuracy | ||
150 | with no significant impact on battery life */ | ||
151 | #define AS3525_MCLK_SEL AS3525_CLK_PLLB | ||
152 | #else | ||
153 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA | 141 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA |
154 | #endif /* CONFIG_CPU == AS3525v2 */ | ||
155 | |||
156 | #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA) | ||
157 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ | 142 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ |
158 | #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB) | ||
159 | #define AS3525_MCLK_FREQ AS3525_PLLB_FREQ | ||
160 | #else | ||
161 | #error Choose either PLLA or PLLB for MCLK! | ||
162 | #endif | ||
163 | 143 | ||
164 | /* PCLK */ | 144 | /* PCLK */ |
165 | 145 | ||