diff options
-rw-r--r-- | firmware/export/config/sansaclipplus.h | 4 | ||||
-rw-r--r-- | firmware/export/config/sansaclipv2.h | 4 | ||||
-rw-r--r-- | firmware/export/config/sansaclipzip.h | 4 | ||||
-rw-r--r-- | firmware/export/config/sansafuzev2.h | 4 | ||||
-rw-r--r-- | firmware/rolo.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 34 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 35 |
7 files changed, 35 insertions, 54 deletions
diff --git a/firmware/export/config/sansaclipplus.h b/firmware/export/config/sansaclipplus.h index a2df3d21c8..e9ebf02f85 100644 --- a/firmware/export/config/sansaclipplus.h +++ b/firmware/export/config/sansaclipplus.h | |||
@@ -176,7 +176,7 @@ | |||
176 | #define CURRENT_MAX_CHG 150 | 176 | #define CURRENT_MAX_CHG 150 |
177 | 177 | ||
178 | /* Define this to the CPU frequency */ | 178 | /* Define this to the CPU frequency */ |
179 | #define CPU_FREQ 240000000 | 179 | #define CPU_FREQ 192000000 |
180 | 180 | ||
181 | /* Type of LCD */ | 181 | /* Type of LCD */ |
182 | #define CONFIG_LCD LCD_SSD1303 | 182 | #define CONFIG_LCD LCD_SSD1303 |
@@ -194,7 +194,7 @@ | |||
194 | #define CONFIG_LED LED_VIRTUAL | 194 | #define CONFIG_LED LED_VIRTUAL |
195 | 195 | ||
196 | /* Define this if you have adjustable CPU frequency */ | 196 | /* Define this if you have adjustable CPU frequency */ |
197 | //#define HAVE_ADJUSTABLE_CPU_FREQ | 197 | #define HAVE_ADJUSTABLE_CPU_FREQ |
198 | 198 | ||
199 | #define BOOTFILE_EXT "sansa" | 199 | #define BOOTFILE_EXT "sansa" |
200 | #define BOOTFILE "rockbox." BOOTFILE_EXT | 200 | #define BOOTFILE "rockbox." BOOTFILE_EXT |
diff --git a/firmware/export/config/sansaclipv2.h b/firmware/export/config/sansaclipv2.h index 8b0b84c1d0..d163d116cf 100644 --- a/firmware/export/config/sansaclipv2.h +++ b/firmware/export/config/sansaclipv2.h | |||
@@ -172,7 +172,7 @@ | |||
172 | #define CURRENT_MAX_CHG 150 | 172 | #define CURRENT_MAX_CHG 150 |
173 | 173 | ||
174 | /* Define this to the CPU frequency */ | 174 | /* Define this to the CPU frequency */ |
175 | #define CPU_FREQ 240000000 | 175 | #define CPU_FREQ 192000000 |
176 | 176 | ||
177 | /* Type of LCD */ | 177 | /* Type of LCD */ |
178 | #define CONFIG_LCD LCD_SSD1303 | 178 | #define CONFIG_LCD LCD_SSD1303 |
@@ -190,7 +190,7 @@ | |||
190 | #define CONFIG_LED LED_VIRTUAL | 190 | #define CONFIG_LED LED_VIRTUAL |
191 | 191 | ||
192 | /* Define this if you have adjustable CPU frequency */ | 192 | /* Define this if you have adjustable CPU frequency */ |
193 | //#define HAVE_ADJUSTABLE_CPU_FREQ | 193 | #define HAVE_ADJUSTABLE_CPU_FREQ |
194 | 194 | ||
195 | #define BOOTFILE_EXT "sansa" | 195 | #define BOOTFILE_EXT "sansa" |
196 | #define BOOTFILE "rockbox." BOOTFILE_EXT | 196 | #define BOOTFILE "rockbox." BOOTFILE_EXT |
diff --git a/firmware/export/config/sansaclipzip.h b/firmware/export/config/sansaclipzip.h index 9743261a52..1f6307865a 100644 --- a/firmware/export/config/sansaclipzip.h +++ b/firmware/export/config/sansaclipzip.h | |||
@@ -175,7 +175,7 @@ | |||
175 | #define CURRENT_MAX_CHG 150 | 175 | #define CURRENT_MAX_CHG 150 |
176 | 176 | ||
177 | /* Define this to the CPU frequency */ | 177 | /* Define this to the CPU frequency */ |
178 | #define CPU_FREQ 240000000 | 178 | #define CPU_FREQ 192000000 |
179 | 179 | ||
180 | /* Type of LCD */ | 180 | /* Type of LCD */ |
181 | #define CONFIG_LCD LCD_CLIPZIP | 181 | #define CONFIG_LCD LCD_CLIPZIP |
@@ -193,7 +193,7 @@ | |||
193 | #define CONFIG_LED LED_VIRTUAL | 193 | #define CONFIG_LED LED_VIRTUAL |
194 | 194 | ||
195 | /* Define this if you have adjustable CPU frequency */ | 195 | /* Define this if you have adjustable CPU frequency */ |
196 | //#define HAVE_ADJUSTABLE_CPU_FREQ | 196 | #define HAVE_ADJUSTABLE_CPU_FREQ |
197 | 197 | ||
198 | #define BOOTFILE_EXT "sansa" | 198 | #define BOOTFILE_EXT "sansa" |
199 | #define BOOTFILE "rockbox." BOOTFILE_EXT | 199 | #define BOOTFILE "rockbox." BOOTFILE_EXT |
diff --git a/firmware/export/config/sansafuzev2.h b/firmware/export/config/sansafuzev2.h index f53c287d87..3b4fb2279b 100644 --- a/firmware/export/config/sansafuzev2.h +++ b/firmware/export/config/sansafuzev2.h | |||
@@ -182,7 +182,7 @@ | |||
182 | #define CURRENT_MAX_CHG 200 | 182 | #define CURRENT_MAX_CHG 200 |
183 | 183 | ||
184 | /* Define this to the CPU frequency */ | 184 | /* Define this to the CPU frequency */ |
185 | #define CPU_FREQ 240000000 | 185 | #define CPU_FREQ 192000000 |
186 | 186 | ||
187 | /* Type of LCD */ | 187 | /* Type of LCD */ |
188 | #define CONFIG_LCD LCD_FUZE | 188 | #define CONFIG_LCD LCD_FUZE |
@@ -208,7 +208,7 @@ | |||
208 | #define HAVE_BOOTLOADER_USB_MODE | 208 | #define HAVE_BOOTLOADER_USB_MODE |
209 | 209 | ||
210 | /* Define this if you have adjustable CPU frequency */ | 210 | /* Define this if you have adjustable CPU frequency */ |
211 | //#define HAVE_ADJUSTABLE_CPU_FREQ | 211 | #define HAVE_ADJUSTABLE_CPU_FREQ |
212 | 212 | ||
213 | #define BOOTFILE_EXT "sansa" | 213 | #define BOOTFILE_EXT "sansa" |
214 | #define BOOTFILE "rockbox." BOOTFILE_EXT | 214 | #define BOOTFILE "rockbox." BOOTFILE_EXT |
diff --git a/firmware/rolo.c b/firmware/rolo.c index 923199f9d4..8976a3ea23 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c | |||
@@ -267,6 +267,10 @@ int rolo_load(const char* filename) | |||
267 | lcd_remote_update(); | 267 | lcd_remote_update(); |
268 | #endif | 268 | #endif |
269 | adc_close(); | 269 | adc_close(); |
270 | #if CONFIG_CPU == AS3525v2 | ||
271 | /* Set CVDD1 power supply to default*/ | ||
272 | ascodec_write_pmu(0x17, 1, 0); | ||
273 | #endif | ||
270 | 274 | ||
271 | #if CONFIG_CPU != IMX31L /* We're not finished yet */ | 275 | #if CONFIG_CPU != IMX31L /* We're not finished yet */ |
272 | #ifdef CPU_ARM | 276 | #ifdef CPU_ARM |
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 97d6edb3d1..f4bb5568fb 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -70,11 +70,8 @@ | |||
70 | * - bit 12 = unknown (always set to 1) | 70 | * - bit 12 = unknown (always set to 1) |
71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz | 71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz |
72 | */ | 72 | */ |
73 | #define AS3525_PLLA_FREQ 240000000 | 73 | #define AS3525_PLLA_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/ |
74 | #define AS3525_PLLA_SETTING 0x113B | 74 | #define AS3525_PLLA_SETTING 0x155F |
75 | |||
76 | #define AS3525_PLLB_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/ | ||
77 | #define AS3525_PLLB_SETTING 0x155F | ||
78 | 75 | ||
79 | #define AS3525_FCLK_PREDIV 0 | 76 | #define AS3525_FCLK_PREDIV 0 |
80 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ | 77 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ |
@@ -86,13 +83,9 @@ | |||
86 | * Also note that CGU_PERI is based on fclk, not PLLA | 83 | * Also note that CGU_PERI is based on fclk, not PLLA |
87 | */ | 84 | */ |
88 | 85 | ||
89 | #ifdef SANSA_FUZEV2 | 86 | |
90 | /* display is unbearably slow at 24MHz | 87 | |
91 | * 34285715 HZ works ok but 40MHz works even better*/ | 88 | #define AS3525_DRAM_FREQ 96000000 /* Initial DRAM frequency */ |
92 | #define AS3525_DRAM_FREQ 40000000 /* Initial DRAM frequency */ | ||
93 | #else | ||
94 | #define AS3525_DRAM_FREQ 24000000 /* Initial DRAM frequency */ | ||
95 | #endif /* SANSA_FUZEV2 */ | ||
96 | 89 | ||
97 | #else | 90 | #else |
98 | /* AS3525v1 */ | 91 | /* AS3525v1 */ |
@@ -131,8 +124,8 @@ | |||
131 | 124 | ||
132 | /* Tell the software what frequencies we're running */ | 125 | /* Tell the software what frequencies we're running */ |
133 | #define CPUFREQ_MAX AS3525_FCLK_FREQ | 126 | #define CPUFREQ_MAX AS3525_FCLK_FREQ |
134 | #define CPUFREQ_DEFAULT AS3525_PCLK_FREQ | 127 | #define CPUFREQ_DEFAULT 38400000 |
135 | #define CPUFREQ_NORMAL AS3525_PCLK_FREQ | 128 | #define CPUFREQ_NORMAL CPUFREQ_DEFAULT |
136 | 129 | ||
137 | /* FCLK */ | 130 | /* FCLK */ |
138 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA | 131 | #define AS3525_FCLK_SEL AS3525_CLK_PLLA |
@@ -145,21 +138,8 @@ | |||
145 | #endif /* CONFIG_CPU == AS3525v2 */ | 138 | #endif /* CONFIG_CPU == AS3525v2 */ |
146 | 139 | ||
147 | /* MCLK */ | 140 | /* MCLK */ |
148 | #if CONFIG_CPU == AS3525v2 | ||
149 | /* on AMSv2 we can enable PLLB for MCLK to increase PCM sample rate accuracy | ||
150 | with no significant impact on battery life */ | ||
151 | #define AS3525_MCLK_SEL AS3525_CLK_PLLB | ||
152 | #else | ||
153 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA | 141 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA |
154 | #endif /* CONFIG_CPU == AS3525v2 */ | ||
155 | |||
156 | #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA) | ||
157 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ | 142 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ |
158 | #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB) | ||
159 | #define AS3525_MCLK_FREQ AS3525_PLLB_FREQ | ||
160 | #else | ||
161 | #error Choose either PLLA or PLLB for MCLK! | ||
162 | #endif | ||
163 | 143 | ||
164 | /* PCLK */ | 144 | /* PCLK */ |
165 | 145 | ||
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 51b6755601..4de111d00f 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -306,8 +306,6 @@ void system_init(void) | |||
306 | 306 | ||
307 | CGU_PERI |= CGU_ROM_ENABLE; /* needed for rebooting */ | 307 | CGU_PERI |= CGU_ROM_ENABLE; /* needed for rebooting */ |
308 | 308 | ||
309 | set_cpu_frequency(CPUFREQ_DEFAULT); | ||
310 | |||
311 | #if 0 /* the GPIO clock is already enabled by the dualboot function */ | 309 | #if 0 /* the GPIO clock is already enabled by the dualboot function */ |
312 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; | 310 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; |
313 | #endif | 311 | #endif |
@@ -335,10 +333,8 @@ void system_init(void) | |||
335 | ascodec_write_pmu(0x18, 1, 0x35); | 333 | ascodec_write_pmu(0x18, 1, 0x35); |
336 | /* AVDD17: set AVDD17 power supply to 2.5V */ | 334 | /* AVDD17: set AVDD17 power supply to 2.5V */ |
337 | ascodec_write_pmu(0x18, 7, 0x31); | 335 | ascodec_write_pmu(0x18, 7, 0x31); |
338 | #ifdef SANSA_CLIPZIP | 336 | /* CVDD2: set CVDD2 power supply (digital for DAC/SD/etc) to 2.65V */ |
339 | /* CVDD2: set CVDD2 power supply to 2.8V */ | 337 | ascodec_write_pmu(0x17, 2, 0x80 | 113); |
340 | ascodec_write_pmu(0x17, 2, 0xF4); | ||
341 | #endif | ||
342 | #else /* HAVE_AS3543 */ | 338 | #else /* HAVE_AS3543 */ |
343 | ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING); | 339 | ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING); |
344 | #endif /* HAVE_AS3543 */ | 340 | #endif /* HAVE_AS3543 */ |
@@ -460,23 +456,18 @@ void set_cpu_frequency(long frequency) | |||
460 | } | 456 | } |
461 | } | 457 | } |
462 | #else /* as3525v2 */ | 458 | #else /* as3525v2 */ |
463 | /* FIXME : disabled for now, seems to cause buggy memory accesses | ||
464 | * Disabling MMU or putting the function in uncached memory seems to help? */ | ||
465 | void set_cpu_frequency(long frequency) | 459 | void set_cpu_frequency(long frequency) |
466 | { | 460 | { |
467 | int oldstatus = disable_irq_save(); | ||
468 | |||
469 | /* We only have 2 settings */ | ||
470 | cpu_frequency = (frequency == CPUFREQ_MAX) ? frequency : CPUFREQ_NORMAL; | ||
471 | |||
472 | if(frequency == CPUFREQ_MAX) | 461 | if(frequency == CPUFREQ_MAX) |
473 | { | 462 | { |
474 | /* Change PCLK while FCLK is low, so it doesn't go too high */ | 463 | /* Set CVDD1 power supply */ |
475 | CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0 << 2); | 464 | /*ascodec_write_pmu(0x17, 1, 0x80 | 47);*/ |
476 | 465 | ||
477 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | | 466 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | |
478 | (AS3525_FCLK_PREDIV << 2) | | 467 | (AS3525_FCLK_PREDIV << 2) | |
479 | AS3525_FCLK_SEL); | 468 | AS3525_FCLK_SEL); |
469 | |||
470 | cpu_frequency = CPUFREQ_MAX; | ||
480 | } | 471 | } |
481 | else | 472 | else |
482 | { | 473 | { |
@@ -484,11 +475,17 @@ void set_cpu_frequency(long frequency) | |||
484 | (AS3525_FCLK_PREDIV << 2) | | 475 | (AS3525_FCLK_PREDIV << 2) | |
485 | AS3525_FCLK_SEL); | 476 | AS3525_FCLK_SEL); |
486 | 477 | ||
487 | /* Change PCLK after FCLK is low, so it doesn't go too high */ | 478 | cpu_frequency = CPUFREQ_NORMAL; |
488 | CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2); | ||
489 | } | ||
490 | 479 | ||
491 | restore_irq(oldstatus); | 480 | /* Set CVDD1 power supply */ |
481 | /* | ||
482 | #ifdef SANSA_CLIPZIP | ||
483 | ascodec_write_pmu(0x17, 1, 0x80 | 19); | ||
484 | #else | ||
485 | ascodec_write_pmu(0x17, 1, 0x80 | 22); | ||
486 | #endif | ||
487 | */ | ||
488 | } | ||
492 | } | 489 | } |
493 | #endif | 490 | #endif |
494 | 491 | ||