diff options
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index bc112fdea8..08c385c7cd 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -56,6 +56,13 @@ | |||
56 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ | 56 | #define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ |
57 | 57 | ||
58 | /** ************ Change these to reconfigure clocking scheme *******************/ | 58 | /** ************ Change these to reconfigure clocking scheme *******************/ |
59 | #ifdef SANSA_CLIPV2 | ||
60 | |||
61 | /* PLL* registers differ from AS3525 */ | ||
62 | #define AS3525_PLLA_FREQ 240000000 | ||
63 | |||
64 | #else | ||
65 | |||
59 | /* PLL frequencies and settings*/ | 66 | /* PLL frequencies and settings*/ |
60 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ | 67 | #define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ |
61 | /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ | 68 | /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ |
@@ -63,6 +70,8 @@ | |||
63 | /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ | 70 | /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ |
64 | #define AS3525_PLLA_SETTING 0x261F | 71 | #define AS3525_PLLA_SETTING 0x261F |
65 | 72 | ||
73 | #endif /* SANSA_CLIPV2 */ | ||
74 | |||
66 | //#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ | 75 | //#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ |
67 | /* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3*/ | 76 | /* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3*/ |
68 | /* *6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, */ | 77 | /* *6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, */ |
@@ -118,7 +127,13 @@ | |||
118 | 127 | ||
119 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 128 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
120 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 129 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
130 | |||
131 | #ifdef SANSA_CLIPV2 | ||
132 | #define AS3525_MS_FREQ 120000000 | ||
133 | #define AS3525_IDE_FREQ 80000000 | ||
134 | #else | ||
121 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ | 135 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ |
136 | #endif /* SANSA_CLIPV2 */ | ||
122 | 137 | ||
123 | 138 | ||
124 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ | 139 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ |