diff options
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/s5l8700.h | 20 | ||||
| -rw-r--r-- | firmware/export/usb-s3c6400x.h | 586 |
2 files changed, 313 insertions, 293 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index e8f4bc70c7..6494787f5c 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
| @@ -571,6 +571,8 @@ | |||
| 571 | #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ | 571 | #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ |
| 572 | #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ | 572 | #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ |
| 573 | #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ | 573 | #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ |
| 574 | #define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */ | ||
| 575 | #define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */ | ||
| 574 | #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ | 576 | #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ |
| 575 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ | 577 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ |
| 576 | 578 | ||
| @@ -686,9 +688,9 @@ | |||
| 686 | #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ | 688 | #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ |
| 687 | 689 | ||
| 688 | 690 | ||
| 689 | /* Hardware AES crypto unit - S5L8701 only */ | ||
| 690 | #if CONFIG_CPU==S5L8701 | 691 | #if CONFIG_CPU==S5L8701 |
| 691 | 692 | ||
| 693 | /* Hardware AES crypto unit - S5L8701 only */ | ||
| 692 | #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000)) | 694 | #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000)) |
| 693 | #define ICONINTPND (*(REG32_PTR_T)(0x39C00010)) | 695 | #define ICONINTPND (*(REG32_PTR_T)(0x39C00010)) |
| 694 | #define AESCONTROL (*(REG32_PTR_T)(0x39800000)) | 696 | #define AESCONTROL (*(REG32_PTR_T)(0x39800000)) |
| @@ -709,4 +711,20 @@ | |||
| 709 | #define HASHRESULT ((REG32_PTR_T)(0x3C600020)) | 711 | #define HASHRESULT ((REG32_PTR_T)(0x3C600020)) |
| 710 | #define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) | 712 | #define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) |
| 711 | 713 | ||
| 714 | /* Clickwheel controller - S5L8701 only */ | ||
| 715 | #define WHEEL00 (*((uint32_t volatile*)(0x3C200000))) | ||
| 716 | #define WHEEL04 (*((uint32_t volatile*)(0x3C200004))) | ||
| 717 | #define WHEEL08 (*((uint32_t volatile*)(0x3C200008))) | ||
| 718 | #define WHEEL0C (*((uint32_t volatile*)(0x3C20000C))) | ||
| 719 | #define WHEEL10 (*((uint32_t volatile*)(0x3C200010))) | ||
| 720 | #define WHEELINT (*((uint32_t volatile*)(0x3C200014))) | ||
| 721 | #define WHEELRX (*((uint32_t volatile*)(0x3C200018))) | ||
| 722 | #define WHEELTX (*((uint32_t volatile*)(0x3C20001C))) | ||
| 723 | |||
| 724 | /* Synopsys OTG - S5L8701 only */ | ||
| 725 | #define OTGBASE 0x38800000 | ||
| 726 | #define PHYBASE 0x3C400000 | ||
| 727 | #define SYNOPSYSOTG_CLOCK 0 | ||
| 728 | #define SYNOPSYSOTG_AHBCFG 0x27 | ||
| 729 | |||
| 712 | #endif /* CONFIG_CPU==S5L8701 */ | 730 | #endif /* CONFIG_CPU==S5L8701 */ |
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index 22b0769681..eeac9d038e 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h | |||
| @@ -22,320 +22,322 @@ | |||
| 22 | #define USB_S3C6400X_H | 22 | #define USB_S3C6400X_H |
| 23 | 23 | ||
| 24 | 24 | ||
| 25 | #define REG32_PTR_T volatile uint32_t * | ||
| 26 | 25 | ||
| 27 | 26 | ||
| 28 | /*** OTG PHY CONTROL REGISTERS ***/ | 27 | /*** OTG PHY CONTROL REGISTERS ***/ |
| 29 | #define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000) | 28 | #define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000))) |
| 30 | #define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004) | 29 | #define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004))) |
| 31 | #define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008) | 30 | #define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008))) |
| 31 | #define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018))) | ||
| 32 | #define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c))) | ||
| 33 | #define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044))) | ||
| 32 | 34 | ||
| 33 | /*** OTG LINK CORE REGISTERS ***/ | 35 | /*** OTG LINK CORE REGISTERS ***/ |
| 34 | /* Core Global Registers */ | 36 | /* Core Global Registers */ |
| 35 | #define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000) | 37 | #define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000))) |
| 36 | #define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004) | 38 | #define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004))) |
| 37 | #define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008) | 39 | #define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008))) |
| 38 | #define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C) | 40 | #define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C))) |
| 39 | #define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010) | 41 | #define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010))) |
| 40 | #define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014) | 42 | #define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014))) |
| 41 | #define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018) | 43 | #define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018))) |
| 42 | #define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C) | 44 | #define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C))) |
| 43 | #define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020) | 45 | #define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020))) |
| 44 | #define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024) | 46 | #define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024))) |
| 45 | #define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028) | 47 | #define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028))) |
| 46 | #define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C) | 48 | #define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C))) |
| 47 | #define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100) | 49 | #define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100))) |
| 48 | #define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x) | 50 | #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x)))) |
| 49 | #define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104) | 51 | #define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104))) |
| 50 | #define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108) | 52 | #define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108))) |
| 51 | #define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C) | 53 | #define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C))) |
| 52 | #define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110) | 54 | #define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110))) |
| 53 | #define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114) | 55 | #define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114))) |
| 54 | #define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118) | 56 | #define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118))) |
| 55 | #define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C) | 57 | #define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C))) |
| 56 | #define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120) | 58 | #define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120))) |
| 57 | #define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124) | 59 | #define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124))) |
| 58 | #define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128) | 60 | #define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128))) |
| 59 | #define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C) | 61 | #define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C))) |
| 60 | #define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130) | 62 | #define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130))) |
| 61 | #define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134) | 63 | #define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134))) |
| 62 | #define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138) | 64 | #define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138))) |
| 63 | #define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C) | 65 | #define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C))) |
| 64 | 66 | ||
| 65 | /*** HOST MODE REGISTERS ***/ | 67 | /*** HOST MODE REGISTERS ***/ |
| 66 | /* Host Global Registers */ | 68 | /* Host Global Registers */ |
| 67 | #define HCFG *(REG32_PTR_T)(OTGBASE + 0x400) | 69 | #define HCFG (*((uint32_t volatile*)(OTGBASE + 0x400))) |
| 68 | #define HFIR *(REG32_PTR_T)(OTGBASE + 0x404) | 70 | #define HFIR (*((uint32_t volatile*)(OTGBASE + 0x404))) |
| 69 | #define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408) | 71 | #define HFNUM (*((uint32_t volatile*)(OTGBASE + 0x408))) |
| 70 | #define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410) | 72 | #define HPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x410))) |
| 71 | #define HAINT *(REG32_PTR_T)(OTGBASE + 0x414) | 73 | #define HAINT (*((uint32_t volatile*)(OTGBASE + 0x414))) |
| 72 | #define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418) | 74 | #define HAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x418))) |
| 73 | 75 | ||
| 74 | /* Host Port Control and Status Registers */ | 76 | /* Host Port Control and Status Registers */ |
| 75 | #define HPRT *(REG32_PTR_T)(OTGBASE + 0x440) | 77 | #define HPRT (*((uint32_t volatile*)(OTGBASE + 0x440))) |
| 76 | 78 | ||
| 77 | /* Host Channel-Specific Registers */ | 79 | /* Host Channel-Specific Registers */ |
| 78 | #define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x) | 80 | #define HCCHAR(x) (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x)))) |
| 79 | #define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x) | 81 | #define HCSPLT(x) (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x)))) |
| 80 | #define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x) | 82 | #define HCINT(x) (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x)))) |
| 81 | #define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x) | 83 | #define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x)))) |
| 82 | #define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x) | 84 | #define HCTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x)))) |
| 83 | #define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x) | 85 | #define HCDMA(x) (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x)))) |
| 84 | #define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500) | 86 | #define HCCHAR0 (*((uint32_t volatile*)(OTGBASE + 0x500))) |
| 85 | #define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504) | 87 | #define HCSPLT0 (*((uint32_t volatile*)(OTGBASE + 0x504))) |
| 86 | #define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508) | 88 | #define HCINT0 (*((uint32_t volatile*)(OTGBASE + 0x508))) |
| 87 | #define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C) | 89 | #define HCINTMSK0 (*((uint32_t volatile*)(OTGBASE + 0x50C))) |
| 88 | #define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510) | 90 | #define HCTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x510))) |
| 89 | #define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514) | 91 | #define HCDMA0 (*((uint32_t volatile*)(OTGBASE + 0x514))) |
| 90 | #define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520) | 92 | #define HCCHAR1 (*((uint32_t volatile*)(OTGBASE + 0x520))) |
| 91 | #define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524) | 93 | #define HCSPLT1 (*((uint32_t volatile*)(OTGBASE + 0x524))) |
| 92 | #define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528) | 94 | #define HCINT1 (*((uint32_t volatile*)(OTGBASE + 0x528))) |
| 93 | #define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C) | 95 | #define HCINTMSK1 (*((uint32_t volatile*)(OTGBASE + 0x52C))) |
| 94 | #define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530) | 96 | #define HCTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x530))) |
| 95 | #define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534) | 97 | #define HCDMA1 (*((uint32_t volatile*)(OTGBASE + 0x534))) |
| 96 | #define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540) | 98 | #define HCCHAR2 (*((uint32_t volatile*)(OTGBASE + 0x540))) |
| 97 | #define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544) | 99 | #define HCSPLT2 (*((uint32_t volatile*)(OTGBASE + 0x544))) |
| 98 | #define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548) | 100 | #define HCINT2 (*((uint32_t volatile*)(OTGBASE + 0x548))) |
| 99 | #define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C) | 101 | #define HCINTMSK2 (*((uint32_t volatile*)(OTGBASE + 0x54C))) |
| 100 | #define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550) | 102 | #define HCTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x550))) |
| 101 | #define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554) | 103 | #define HCDMA2 (*((uint32_t volatile*)(OTGBASE + 0x554))) |
| 102 | #define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560) | 104 | #define HCCHAR3 (*((uint32_t volatile*)(OTGBASE + 0x560))) |
| 103 | #define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564) | 105 | #define HCSPLT3 (*((uint32_t volatile*)(OTGBASE + 0x564))) |
| 104 | #define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568) | 106 | #define HCINT3 (*((uint32_t volatile*)(OTGBASE + 0x568))) |
| 105 | #define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C) | 107 | #define HCINTMSK3 (*((uint32_t volatile*)(OTGBASE + 0x56C))) |
| 106 | #define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570) | 108 | #define HCTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x570))) |
| 107 | #define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574) | 109 | #define HCDMA3 (*((uint32_t volatile*)(OTGBASE + 0x574))) |
| 108 | #define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580) | 110 | #define HCCHAR4 (*((uint32_t volatile*)(OTGBASE + 0x580))) |
| 109 | #define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584) | 111 | #define HCSPLT4 (*((uint32_t volatile*)(OTGBASE + 0x584))) |
| 110 | #define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588) | 112 | #define HCINT4 (*((uint32_t volatile*)(OTGBASE + 0x588))) |
| 111 | #define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C) | 113 | #define HCINTMSK4 (*((uint32_t volatile*)(OTGBASE + 0x58C))) |
| 112 | #define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590) | 114 | #define HCTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x590))) |
| 113 | #define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594) | 115 | #define HCDMA4 (*((uint32_t volatile*)(OTGBASE + 0x594))) |
| 114 | #define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0) | 116 | #define HCCHAR5 (*((uint32_t volatile*)(OTGBASE + 0x5A0))) |
| 115 | #define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4) | 117 | #define HCSPLT5 (*((uint32_t volatile*)(OTGBASE + 0x5A4))) |
| 116 | #define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8) | 118 | #define HCINT5 (*((uint32_t volatile*)(OTGBASE + 0x5A8))) |
| 117 | #define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC) | 119 | #define HCINTMSK5 (*((uint32_t volatile*)(OTGBASE + 0x5AC))) |
| 118 | #define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0) | 120 | #define HCTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x5B0))) |
| 119 | #define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4) | 121 | #define HCDMA5 (*((uint32_t volatile*)(OTGBASE + 0x5B4))) |
| 120 | #define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0) | 122 | #define HCCHAR6 (*((uint32_t volatile*)(OTGBASE + 0x5C0))) |
| 121 | #define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4) | 123 | #define HCSPLT6 (*((uint32_t volatile*)(OTGBASE + 0x5C4))) |
| 122 | #define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8) | 124 | #define HCINT6 (*((uint32_t volatile*)(OTGBASE + 0x5C8))) |
| 123 | #define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC) | 125 | #define HCINTMSK6 (*((uint32_t volatile*)(OTGBASE + 0x5CC))) |
| 124 | #define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0) | 126 | #define HCTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x5D0))) |
| 125 | #define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4) | 127 | #define HCDMA6 (*((uint32_t volatile*)(OTGBASE + 0x5D4))) |
| 126 | #define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0) | 128 | #define HCCHAR7 (*((uint32_t volatile*)(OTGBASE + 0x5E0))) |
| 127 | #define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4) | 129 | #define HCSPLT7 (*((uint32_t volatile*)(OTGBASE + 0x5E4))) |
| 128 | #define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8) | 130 | #define HCINT7 (*((uint32_t volatile*)(OTGBASE + 0x5E8))) |
| 129 | #define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC) | 131 | #define HCINTMSK7 (*((uint32_t volatile*)(OTGBASE + 0x5EC))) |
| 130 | #define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0) | 132 | #define HCTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x5F0))) |
| 131 | #define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4) | 133 | #define HCDMA7 (*((uint32_t volatile*)(OTGBASE + 0x5F4))) |
| 132 | #define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600) | 134 | #define HCCHAR8 (*((uint32_t volatile*)(OTGBASE + 0x600))) |
| 133 | #define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604) | 135 | #define HCSPLT8 (*((uint32_t volatile*)(OTGBASE + 0x604))) |
| 134 | #define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608) | 136 | #define HCINT8 (*((uint32_t volatile*)(OTGBASE + 0x608))) |
| 135 | #define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C) | 137 | #define HCINTMSK8 (*((uint32_t volatile*)(OTGBASE + 0x60C))) |
| 136 | #define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610) | 138 | #define HCTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x610))) |
| 137 | #define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614) | 139 | #define HCDMA8 (*((uint32_t volatile*)(OTGBASE + 0x614))) |
| 138 | #define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620) | 140 | #define HCCHAR9 (*((uint32_t volatile*)(OTGBASE + 0x620))) |
| 139 | #define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624) | 141 | #define HCSPLT9 (*((uint32_t volatile*)(OTGBASE + 0x624))) |
| 140 | #define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628) | 142 | #define HCINT9 (*((uint32_t volatile*)(OTGBASE + 0x628))) |
| 141 | #define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C) | 143 | #define HCINTMSK9 (*((uint32_t volatile*)(OTGBASE + 0x62C))) |
| 142 | #define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630) | 144 | #define HCTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x630))) |
| 143 | #define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634) | 145 | #define HCDMA9 (*((uint32_t volatile*)(OTGBASE + 0x634))) |
| 144 | #define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640) | 146 | #define HCCHAR10 (*((uint32_t volatile*)(OTGBASE + 0x640))) |
| 145 | #define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644) | 147 | #define HCSPLT10 (*((uint32_t volatile*)(OTGBASE + 0x644))) |
| 146 | #define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648) | 148 | #define HCINT10 (*((uint32_t volatile*)(OTGBASE + 0x648))) |
| 147 | #define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C) | 149 | #define HCINTMSK10 (*((uint32_t volatile*)(OTGBASE + 0x64C))) |
| 148 | #define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650) | 150 | #define HCTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x650))) |
| 149 | #define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654) | 151 | #define HCDMA10 (*((uint32_t volatile*)(OTGBASE + 0x654))) |
| 150 | #define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660) | 152 | #define HCCHAR11 (*((uint32_t volatile*)(OTGBASE + 0x660))) |
| 151 | #define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664) | 153 | #define HCSPLT11 (*((uint32_t volatile*)(OTGBASE + 0x664))) |
| 152 | #define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668) | 154 | #define HCINT11 (*((uint32_t volatile*)(OTGBASE + 0x668))) |
| 153 | #define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C) | 155 | #define HCINTMSK11 (*((uint32_t volatile*)(OTGBASE + 0x66C))) |
| 154 | #define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670) | 156 | #define HCTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x670))) |
| 155 | #define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674) | 157 | #define HCDMA11 (*((uint32_t volatile*)(OTGBASE + 0x674))) |
| 156 | #define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680) | 158 | #define HCCHAR12 (*((uint32_t volatile*)(OTGBASE + 0x680))) |
| 157 | #define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684) | 159 | #define HCSPLT12 (*((uint32_t volatile*)(OTGBASE + 0x684))) |
| 158 | #define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688) | 160 | #define HCINT12 (*((uint32_t volatile*)(OTGBASE + 0x688))) |
| 159 | #define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C) | 161 | #define HCINTMSK12 (*((uint32_t volatile*)(OTGBASE + 0x68C))) |
| 160 | #define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690) | 162 | #define HCTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x690))) |
| 161 | #define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694) | 163 | #define HCDMA12 (*((uint32_t volatile*)(OTGBASE + 0x694))) |
| 162 | #define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0) | 164 | #define HCCHAR13 (*((uint32_t volatile*)(OTGBASE + 0x6A0))) |
| 163 | #define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4) | 165 | #define HCSPLT13 (*((uint32_t volatile*)(OTGBASE + 0x6A4))) |
| 164 | #define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8) | 166 | #define HCINT13 (*((uint32_t volatile*)(OTGBASE + 0x6A8))) |
| 165 | #define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC) | 167 | #define HCINTMSK13 (*((uint32_t volatile*)(OTGBASE + 0x6AC))) |
| 166 | #define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0) | 168 | #define HCTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x6B0))) |
| 167 | #define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4) | 169 | #define HCDMA13 (*((uint32_t volatile*)(OTGBASE + 0x6B4))) |
| 168 | #define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0) | 170 | #define HCCHAR14 (*((uint32_t volatile*)(OTGBASE + 0x6C0))) |
| 169 | #define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4) | 171 | #define HCSPLT14 (*((uint32_t volatile*)(OTGBASE + 0x6C4))) |
| 170 | #define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8) | 172 | #define HCINT14 (*((uint32_t volatile*)(OTGBASE + 0x6C8))) |
| 171 | #define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC) | 173 | #define HCINTMSK14 (*((uint32_t volatile*)(OTGBASE + 0x6CC))) |
| 172 | #define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0) | 174 | #define HCTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x6D0))) |
| 173 | #define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4) | 175 | #define HCDMA14 (*((uint32_t volatile*)(OTGBASE + 0x6D4))) |
| 174 | #define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0) | 176 | #define HCCHAR15 (*((uint32_t volatile*)(OTGBASE + 0x6E0))) |
| 175 | #define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4) | 177 | #define HCSPLT15 (*((uint32_t volatile*)(OTGBASE + 0x6E4))) |
| 176 | #define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8) | 178 | #define HCINT15 (*((uint32_t volatile*)(OTGBASE + 0x6E8))) |
| 177 | #define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC) | 179 | #define HCINTMSK15 (*((uint32_t volatile*)(OTGBASE + 0x6EC))) |
| 178 | #define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0) | 180 | #define HCTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x6F0))) |
| 179 | #define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4) | 181 | #define HCDMA15 (*((uint32_t volatile*)(OTGBASE + 0x6F4))) |
| 180 | 182 | ||
| 181 | /*** DEVICE MODE REGISTERS ***/ | 183 | /*** DEVICE MODE REGISTERS ***/ |
| 182 | /* Device Global Registers */ | 184 | /* Device Global Registers */ |
| 183 | #define DCFG *(REG32_PTR_T)(OTGBASE + 0x800) | 185 | #define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800))) |
| 184 | #define DCTL *(REG32_PTR_T)(OTGBASE + 0x804) | 186 | #define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804))) |
| 185 | #define DSTS *(REG32_PTR_T)(OTGBASE + 0x808) | 187 | #define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808))) |
| 186 | #define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810) | 188 | #define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810))) |
| 187 | #define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814) | 189 | #define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814))) |
| 188 | #define DAINT *(REG32_PTR_T)(OTGBASE + 0x818) | 190 | #define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818))) |
| 189 | #define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C) | 191 | #define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C))) |
| 190 | #define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820) | 192 | #define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820))) |
| 191 | #define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824) | 193 | #define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824))) |
| 192 | #define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828) | 194 | #define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828))) |
| 193 | #define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C) | 195 | #define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C))) |
| 194 | #define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830) | 196 | #define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830))) |
| 195 | #define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834) | 197 | #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) |
| 196 | 198 | ||
| 197 | /* Device Logical IN Endpoint-Specific Registers */ | 199 | /* Device Logical IN Endpoint-Specific Registers */ |
| 198 | #define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x) | 200 | #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x)))) |
| 199 | #define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x) | 201 | #define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) |
| 200 | #define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x) | 202 | #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) |
| 201 | #define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x) | 203 | #define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) |
| 202 | #define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900) | 204 | #define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900))) |
| 203 | #define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908) | 205 | #define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908))) |
| 204 | #define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910) | 206 | #define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910))) |
| 205 | #define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914) | 207 | #define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914))) |
| 206 | #define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920) | 208 | #define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920))) |
| 207 | #define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928) | 209 | #define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928))) |
| 208 | #define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930) | 210 | #define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930))) |
| 209 | #define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934) | 211 | #define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934))) |
| 210 | #define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940) | 212 | #define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940))) |
| 211 | #define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948) | 213 | #define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948))) |
| 212 | #define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950) | 214 | #define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950))) |
| 213 | #define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954) | 215 | #define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954))) |
| 214 | #define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960) | 216 | #define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960))) |
| 215 | #define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968) | 217 | #define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968))) |
| 216 | #define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970) | 218 | #define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970))) |
| 217 | #define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974) | 219 | #define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974))) |
| 218 | #define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980) | 220 | #define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980))) |
| 219 | #define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988) | 221 | #define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988))) |
| 220 | #define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990) | 222 | #define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990))) |
| 221 | #define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994) | 223 | #define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994))) |
| 222 | #define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0) | 224 | #define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0))) |
| 223 | #define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8) | 225 | #define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8))) |
| 224 | #define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0) | 226 | #define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0))) |
| 225 | #define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4) | 227 | #define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4))) |
| 226 | #define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0) | 228 | #define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0))) |
| 227 | #define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8) | 229 | #define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8))) |
| 228 | #define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0) | 230 | #define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0))) |
| 229 | #define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4) | 231 | #define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4))) |
| 230 | #define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0) | 232 | #define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0))) |
| 231 | #define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8) | 233 | #define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8))) |
| 232 | #define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0) | 234 | #define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0))) |
| 233 | #define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4) | 235 | #define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4))) |
| 234 | #define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00) | 236 | #define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00))) |
| 235 | #define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08) | 237 | #define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08))) |
| 236 | #define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10) | 238 | #define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10))) |
| 237 | #define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14) | 239 | #define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14))) |
| 238 | #define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20) | 240 | #define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20))) |
| 239 | #define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28) | 241 | #define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28))) |
| 240 | #define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30) | 242 | #define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30))) |
| 241 | #define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34) | 243 | #define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34))) |
| 242 | #define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40) | 244 | #define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40))) |
| 243 | #define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48) | 245 | #define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48))) |
| 244 | #define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50) | 246 | #define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50))) |
| 245 | #define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54) | 247 | #define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54))) |
| 246 | #define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60) | 248 | #define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60))) |
| 247 | #define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68) | 249 | #define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68))) |
| 248 | #define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70) | 250 | #define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70))) |
| 249 | #define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74) | 251 | #define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74))) |
| 250 | #define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80) | 252 | #define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80))) |
| 251 | #define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88) | 253 | #define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88))) |
| 252 | #define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90) | 254 | #define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90))) |
| 253 | #define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94) | 255 | #define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94))) |
| 254 | #define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0) | 256 | #define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0))) |
| 255 | #define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8) | 257 | #define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8))) |
| 256 | #define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0) | 258 | #define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0))) |
| 257 | #define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4) | 259 | #define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4))) |
| 258 | #define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0) | 260 | #define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0))) |
| 259 | #define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8) | 261 | #define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8))) |
| 260 | #define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0) | 262 | #define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0))) |
| 261 | #define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4) | 263 | #define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4))) |
| 262 | #define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0) | 264 | #define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0))) |
| 263 | #define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8) | 265 | #define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8))) |
| 264 | #define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0) | 266 | #define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0))) |
| 265 | #define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4) | 267 | #define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4))) |
| 266 | 268 | ||
| 267 | /* Device Logical OUT Endpoint-Specific Registers */ | 269 | /* Device Logical OUT Endpoint-Specific Registers */ |
| 268 | #define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x) | 270 | #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x)))) |
| 269 | #define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x) | 271 | #define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) |
| 270 | #define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x) | 272 | #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x)))) |
| 271 | #define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x) | 273 | #define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) |
| 272 | #define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00) | 274 | #define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00))) |
| 273 | #define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08) | 275 | #define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08))) |
| 274 | #define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10) | 276 | #define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10))) |
| 275 | #define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14) | 277 | #define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14))) |
| 276 | #define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20) | 278 | #define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20))) |
| 277 | #define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28) | 279 | #define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28))) |
| 278 | #define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30) | 280 | #define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30))) |
| 279 | #define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34) | 281 | #define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34))) |
| 280 | #define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40) | 282 | #define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40))) |
| 281 | #define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48) | 283 | #define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48))) |
| 282 | #define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50) | 284 | #define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50))) |
| 283 | #define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54) | 285 | #define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54))) |
| 284 | #define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60) | 286 | #define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60))) |
| 285 | #define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68) | 287 | #define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68))) |
| 286 | #define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70) | 288 | #define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70))) |
| 287 | #define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74) | 289 | #define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74))) |
| 288 | #define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80) | 290 | #define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80))) |
| 289 | #define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88) | 291 | #define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88))) |
| 290 | #define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90) | 292 | #define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90))) |
| 291 | #define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94) | 293 | #define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94))) |
| 292 | #define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0) | 294 | #define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0))) |
| 293 | #define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8) | 295 | #define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8))) |
| 294 | #define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0) | 296 | #define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0))) |
| 295 | #define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4) | 297 | #define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4))) |
| 296 | #define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0) | 298 | #define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0))) |
| 297 | #define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8) | 299 | #define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8))) |
| 298 | #define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0) | 300 | #define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0))) |
| 299 | #define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4) | 301 | #define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4))) |
| 300 | #define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0) | 302 | #define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0))) |
| 301 | #define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8) | 303 | #define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8))) |
| 302 | #define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0) | 304 | #define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0))) |
| 303 | #define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4) | 305 | #define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4))) |
| 304 | #define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00) | 306 | #define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00))) |
| 305 | #define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08) | 307 | #define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08))) |
| 306 | #define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10) | 308 | #define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10))) |
| 307 | #define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14) | 309 | #define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14))) |
| 308 | #define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20) | 310 | #define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20))) |
| 309 | #define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28) | 311 | #define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28))) |
| 310 | #define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30) | 312 | #define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30))) |
| 311 | #define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34) | 313 | #define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34))) |
| 312 | #define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40) | 314 | #define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40))) |
| 313 | #define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48) | 315 | #define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48))) |
| 314 | #define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50) | 316 | #define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50))) |
| 315 | #define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54) | 317 | #define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54))) |
| 316 | #define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60) | 318 | #define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60))) |
| 317 | #define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68) | 319 | #define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68))) |
| 318 | #define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70) | 320 | #define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70))) |
| 319 | #define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74) | 321 | #define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74))) |
| 320 | #define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80) | 322 | #define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80))) |
| 321 | #define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88) | 323 | #define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88))) |
| 322 | #define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90) | 324 | #define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90))) |
| 323 | #define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94) | 325 | #define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94))) |
| 324 | #define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0) | 326 | #define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0))) |
| 325 | #define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8) | 327 | #define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8))) |
| 326 | #define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0) | 328 | #define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0))) |
| 327 | #define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4) | 329 | #define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4))) |
| 328 | #define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0) | 330 | #define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0))) |
| 329 | #define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8) | 331 | #define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8))) |
| 330 | #define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0) | 332 | #define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0))) |
| 331 | #define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4) | 333 | #define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4))) |
| 332 | #define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0) | 334 | #define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0))) |
| 333 | #define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8) | 335 | #define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8))) |
| 334 | #define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0) | 336 | #define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0))) |
| 335 | #define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4) | 337 | #define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4))) |
| 336 | 338 | ||
| 337 | /* Power and Clock Gating Register */ | 339 | /* Power and Clock Gating Register */ |
| 338 | #define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00) | 340 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) |
| 339 | 341 | ||
| 340 | 342 | ||
| 341 | #endif /* USB_S3C6400X_H */ | 343 | #endif /* USB_S3C6400X_H */ |