diff options
Diffstat (limited to 'firmware/export/s5l8700.h')
-rw-r--r-- | firmware/export/s5l8700.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index e8f4bc70c7..6494787f5c 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
@@ -571,6 +571,8 @@ | |||
571 | #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ | 571 | #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ |
572 | #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ | 572 | #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ |
573 | #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ | 573 | #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ |
574 | #define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */ | ||
575 | #define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */ | ||
574 | #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ | 576 | #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ |
575 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ | 577 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ |
576 | 578 | ||
@@ -686,9 +688,9 @@ | |||
686 | #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ | 688 | #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ |
687 | 689 | ||
688 | 690 | ||
689 | /* Hardware AES crypto unit - S5L8701 only */ | ||
690 | #if CONFIG_CPU==S5L8701 | 691 | #if CONFIG_CPU==S5L8701 |
691 | 692 | ||
693 | /* Hardware AES crypto unit - S5L8701 only */ | ||
692 | #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000)) | 694 | #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000)) |
693 | #define ICONINTPND (*(REG32_PTR_T)(0x39C00010)) | 695 | #define ICONINTPND (*(REG32_PTR_T)(0x39C00010)) |
694 | #define AESCONTROL (*(REG32_PTR_T)(0x39800000)) | 696 | #define AESCONTROL (*(REG32_PTR_T)(0x39800000)) |
@@ -709,4 +711,20 @@ | |||
709 | #define HASHRESULT ((REG32_PTR_T)(0x3C600020)) | 711 | #define HASHRESULT ((REG32_PTR_T)(0x3C600020)) |
710 | #define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) | 712 | #define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) |
711 | 713 | ||
714 | /* Clickwheel controller - S5L8701 only */ | ||
715 | #define WHEEL00 (*((uint32_t volatile*)(0x3C200000))) | ||
716 | #define WHEEL04 (*((uint32_t volatile*)(0x3C200004))) | ||
717 | #define WHEEL08 (*((uint32_t volatile*)(0x3C200008))) | ||
718 | #define WHEEL0C (*((uint32_t volatile*)(0x3C20000C))) | ||
719 | #define WHEEL10 (*((uint32_t volatile*)(0x3C200010))) | ||
720 | #define WHEELINT (*((uint32_t volatile*)(0x3C200014))) | ||
721 | #define WHEELRX (*((uint32_t volatile*)(0x3C200018))) | ||
722 | #define WHEELTX (*((uint32_t volatile*)(0x3C20001C))) | ||
723 | |||
724 | /* Synopsys OTG - S5L8701 only */ | ||
725 | #define OTGBASE 0x38800000 | ||
726 | #define PHYBASE 0x3C400000 | ||
727 | #define SYNOPSYSOTG_CLOCK 0 | ||
728 | #define SYNOPSYSOTG_AHBCFG 0x27 | ||
729 | |||
712 | #endif /* CONFIG_CPU==S5L8701 */ | 730 | #endif /* CONFIG_CPU==S5L8701 */ |