diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/arcotg_udc.h (renamed from firmware/export/mx31.h) | 174 | ||||
-rw-r--r-- | firmware/export/pp5020.h | 3 |
2 files changed, 64 insertions, 113 deletions
diff --git a/firmware/export/mx31.h b/firmware/export/arcotg_udc.h index 5af3bb052a..e3bf93a52e 100644 --- a/firmware/export/mx31.h +++ b/firmware/export/arcotg_udc.h | |||
@@ -5,12 +5,12 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Barry Wardell | 10 | * Copyright (C) 2007 by Barry Wardell |
11 | * | 11 | * |
12 | * i.MX31 driver based on code from the Linux Target Image Builder from | 12 | * ARC OTG USB device driver based on code from the Linux Target Image Builder |
13 | * Freescale - http://www.bitshrine.org/ and | 13 | * from Freescale - http://www.bitshrine.org/ and |
14 | * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch | 14 | * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch |
15 | * Adapted for Rockbox in January 2007 | 15 | * Adapted for Rockbox in January 2007 |
16 | * Original file: drivers/usb/gadget/arcotg_udc.h | 16 | * Original file: drivers/usb/gadget/arcotg_udc.h |
@@ -32,119 +32,62 @@ | |||
32 | /* | 32 | /* |
33 | * Freescale USB device/endpoint management registers | 33 | * Freescale USB device/endpoint management registers |
34 | */ | 34 | */ |
35 | #ifndef __MX31_H | 35 | #ifndef __ARCOTG_UDC_H |
36 | #define __MX31_H | 36 | #define __ARCOTG_UDC_H |
37 | 37 | ||
38 | /* Register addresses - from Freescale i.MX31 reference manual */ | 38 | #include "cpu.h" |
39 | /* The PortalPlayer USB controller usec base address 0xc5000000 */ | 39 | |
40 | #define USB_BASE 0xc5000000 | 40 | #define ETIMEDOUT 1 |
41 | 41 | ||
42 | /* OTG */ | ||
43 | #define UOG_ID (*(volatile unsigned int *)(USB_BASE+0x000)) | ||
44 | #define UOG_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004)) | ||
45 | #define UOG_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008)) | ||
46 | #define UOG_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010)) | ||
47 | #define UOG_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014)) | ||
48 | #define UOG_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100)) | ||
49 | #define UOG_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102)) | ||
50 | #define UOG_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104)) | ||
51 | #define UOG_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108)) | ||
52 | #define UOG_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120)) | ||
53 | #define UOG_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124)) | ||
54 | #define UOG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) | ||
55 | #define UOG_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144)) | ||
56 | #define UOG_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148)) | ||
57 | #define UOG_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c)) | ||
58 | #define UOG_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x154)) | ||
59 | #define UOG_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) | ||
60 | #define UOG_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160)) | ||
61 | #define UOG_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164)) | ||
62 | #define UOG_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170)) | ||
63 | #define UOG_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180)) | ||
64 | #define UOG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) | ||
65 | /*#define UOG_PORTSC2 (*(volatile unsigned int *)(USB_BASE+0x188)) | ||
66 | #define UOG_PORTSC3 (*(volatile unsigned int *)(USB_BASE+0x18c)) | ||
67 | #define UOG_PORTSC4 (*(volatile unsigned int *)(USB_BASE+0x190)) | ||
68 | #define UOG_PORTSC5 (*(volatile unsigned int *)(USB_BASE+0x194)) | ||
69 | #define UOG_PORTSC6 (*(volatile unsigned int *)(USB_BASE+0x198)) | ||
70 | #define UOG_PORTSC7 (*(volatile unsigned int *)(USB_BASE+0x19c)) | ||
71 | #define UOG_PORTSC8 (*(volatile unsigned int *)(USB_BASE+0x1a0))*/ | ||
72 | #define UOG_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4)) | ||
73 | #define UOG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) | ||
74 | #define UOG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) | ||
75 | #define UOG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) | ||
76 | #define UOG_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4)) | ||
77 | #define UOG_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8)) | ||
78 | #define UOG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) | ||
79 | #define ENDPTCRTL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) | ||
80 | #define ENDPTCRTL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) | ||
81 | #define ENDPTCRTL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) | ||
82 | #define ENDPTCRTL3 (*(volatile unsigned int *)(USB_BASE+0x1cc)) | ||
83 | #define ENDPTCRTL4 (*(volatile unsigned int *)(USB_BASE+0x1d0)) | ||
84 | #define ENDPTCRTL5 (*(volatile unsigned int *)(USB_BASE+0x1d4)) | ||
85 | #define ENDPTCRTL6 (*(volatile unsigned int *)(USB_BASE+0x1d8)) | ||
86 | #define ENDPTCRTL7 (*(volatile unsigned int *)(USB_BASE+0x1dc)) | ||
87 | /*#define ENDPTCRTL8 (*(volatile unsigned int *)(USB_BASE+0x1e0)) | ||
88 | #define ENDPTCRTL9 (*(volatile unsigned int *)(USB_BASE+0x1e4)) | ||
89 | #define ENDPTCRTL10 (*(volatile unsigned int *)(USB_BASE+0x1e8)) | ||
90 | #define ENDPTCRTL11 (*(volatile unsigned int *)(USB_BASE+0x1ec)) | ||
91 | #define ENDPTCRTL12 (*(volatile unsigned int *)(USB_BASE+0x1f0)) | ||
92 | #define ENDPTCRTL13 (*(volatile unsigned int *)(USB_BASE+0x1f4)) | ||
93 | #define ENDPTCRTL14 (*(volatile unsigned int *)(USB_BASE+0x1f8)) | ||
94 | #define ENDPTCRTL15 (*(volatile unsigned int *)(USB_BASE+0x1fc))*/ | ||
95 | |||
96 | /* Host 1 */ | ||
97 | #define UH1_ID (*(volatile unsigned int *)(USB_BASE+0x200)) | ||
98 | #define UH1_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x204)) | ||
99 | #define UH1_HWHOST (*(volatile unsigned int *)(USB_BASE+0x208)) | ||
100 | #define UH1_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x210)) | ||
101 | #define UH1_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x214)) | ||
102 | #define UH1_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x300)) | ||
103 | #define UH1_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x302)) | ||
104 | #define UH1_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x304)) | ||
105 | #define UH1_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x308)) | ||
106 | #define UH1_USBCMD (*(volatile unsigned int *)(USB_BASE+0x340)) | ||
107 | #define UH1_USBSTS (*(volatile unsigned int *)(USB_BASE+0x344)) | ||
108 | #define UH1_USBINTR (*(volatile unsigned int *)(USB_BASE+0x348)) | ||
109 | #define UH1_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x34c)) | ||
110 | #define UH1_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x354)) | ||
111 | #define UH1_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x358)) | ||
112 | #define UH1_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x360)) | ||
113 | #define UH1_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x364)) | ||
114 | #define UH1_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x384)) | ||
115 | #define UH1_USBMODE (*(volatile unsigned int *)(USB_BASE+0x3a8)) | ||
116 | |||
117 | /* Host 2 */ | ||
118 | #define UH2_ID (*(volatile unsigned int *)(USB_BASE+0x400)) | ||
119 | #define UH2_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x404)) | ||
120 | #define UH2_HWHOST (*(volatile unsigned int *)(USB_BASE+0x408)) | ||
121 | #define UH2_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x410)) | ||
122 | #define UH2_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x414)) | ||
123 | #define UH2_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x500)) | ||
124 | #define UH2_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x502)) | ||
125 | #define UH2_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x504)) | ||
126 | #define UH2_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x508)) | ||
127 | #define UH2_USBCMD (*(volatile unsigned int *)(USB_BASE+0x540)) | ||
128 | #define UH2_USBSTS (*(volatile unsigned int *)(USB_BASE+0x544)) | ||
129 | #define UH2_USBINTR (*(volatile unsigned int *)(USB_BASE+0x548)) | ||
130 | #define UH2_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x54c)) | ||
131 | #define UH2_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x554)) | ||
132 | #define UH2_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x558)) | ||
133 | #define UH2_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x560)) | ||
134 | #define UH2_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x564)) | ||
135 | #define UH2_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x570)) | ||
136 | #define UH2_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x584)) | ||
137 | #define UH2_USBMODE (*(volatile unsigned int *)(USB_BASE+0x5a8)) | ||
138 | |||
139 | /* General */ | ||
140 | #define USB_CTRL (*(volatile unsigned int *)(USB_BASE+0x600)) | ||
141 | #define USB_OTG_MIRROR (*(volatile unsigned int *)(USB_BASE+0x604)) | ||
142 | |||
143 | /* Maximum values */ | ||
144 | #define USB_MAX_ENDPOINTS 8 | 42 | #define USB_MAX_ENDPOINTS 8 |
145 | #define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2) | 43 | #define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2) |
146 | #define USB_MAX_CTRL_PAYLOAD 64 | 44 | #define USB_MAX_CTRL_PAYLOAD 64 |
147 | 45 | ||
46 | /* USB DR device mode registers (Little Endian) */ | ||
47 | /* Identification registers */ | ||
48 | #define UDC_ID (*(volatile unsigned int *)(USB_BASE+0x000)) | ||
49 | #define UDC_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004)) | ||
50 | #define UDC_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008)) | ||
51 | #define UDC_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010)) | ||
52 | #define UDC_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014)) | ||
53 | |||
54 | /* Capability registers */ | ||
55 | #define UDC_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100)) /* Capability Register Length */ | ||
56 | #define UDC_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102)) /* Host Controller Interface Version */ | ||
57 | #define UDC_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104)) /* Host Controller Structual Parameters */ | ||
58 | #define UDC_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108)) /* Host Controller Capability Parameters */ | ||
59 | #define UDC_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120)) /* Device Controller Interface Version */ | ||
60 | #define UDC_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124)) /* Device Controller Capability Parameters */ | ||
61 | |||
62 | /* Operation registers */ | ||
63 | #define UDC_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) /* USB Command Register */ | ||
64 | #define UDC_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144)) /* USB Status Register */ | ||
65 | #define UDC_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148)) /* USB Interrupt Enable Register */ | ||
66 | #define UDC_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c)) /* Frame Index Register */ | ||
67 | #define UDC_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154)) /* Device Address */ | ||
68 | #define UDC_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) /* Endpoint List Address Register */ | ||
69 | #define UDC_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160)) /* Master Interface Data Burst Size Register */ | ||
70 | #define UDC_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164)) /* Transmit FIFO Tuning Controls Register */ | ||
71 | #define UDC_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170)) | ||
72 | #define UDC_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180)) /* Configure Flag Register */ | ||
73 | #define UDC_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) /* Port 1 Status and Control Register */ | ||
74 | #define UDC_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4)) /* On-The-Go Status and Control */ | ||
75 | #define UDC_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) /* USB Mode Register */ | ||
76 | #define UDC_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) /* Endpoint Setup Status Register */ | ||
77 | #define UDC_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) /* Endpoint Initialization Register */ | ||
78 | #define UDC_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4)) /* Endpoint Flush Register */ | ||
79 | #define UDC_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8)) /* Endpoint Status Register */ | ||
80 | #define UDC_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) /* Endpoint Complete Register */ | ||
81 | #define UDC_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) /* Endpoint 0 Control Register */ | ||
82 | #define UDC_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) /* Endpoint 1 Control Register */ | ||
83 | #define UDC_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) /* Endpoint 2 Control Register */ | ||
84 | #define UDC_ENDPTCTRL3 (*(volatile unsigned int *)(USB_BASE+0x1cc)) /* Endpoint 3 Control Register */ | ||
85 | #define UDC_ENDPTCTRL4 (*(volatile unsigned int *)(USB_BASE+0x1d0)) /* Endpoint 4 Control Register */ | ||
86 | #define UDC_ENDPTCTRL5 (*(volatile unsigned int *)(USB_BASE+0x1d4)) /* Endpoint 5 Control Register */ | ||
87 | #define UDC_ENDPTCTRL6 (*(volatile unsigned int *)(USB_BASE+0x1d8)) /* Endpoint 6 Control Register */ | ||
88 | #define UDC_ENDPTCTRL7 (*(volatile unsigned int *)(USB_BASE+0x1dc)) /* Endpoint 7 Control Register */ | ||
89 | #define UDC_ENDPTCTRL(x) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(x))) /* Endpoint X Control Register */ | ||
90 | |||
148 | /* ep0 transfer state */ | 91 | /* ep0 transfer state */ |
149 | #define WAIT_FOR_SETUP 0 | 92 | #define WAIT_FOR_SETUP 0 |
150 | #define DATA_STATE_XMIT 1 | 93 | #define DATA_STATE_XMIT 1 |
@@ -369,4 +312,9 @@ | |||
369 | #define USB_CTRL_IOENB (0x00000004) | 312 | #define USB_CTRL_IOENB (0x00000004) |
370 | #define USB_CTRL_ULPI_INT0EN (0x00000001) | 313 | #define USB_CTRL_ULPI_INT0EN (0x00000001) |
371 | 314 | ||
372 | #endif /* __MX31_H */ | 315 | /* Externally used functions */ |
316 | int dr_controller_setup(void); | ||
317 | void dr_controller_run(void); | ||
318 | void dr_controller_stop(void); | ||
319 | |||
320 | #endif /* __ARCOTG_UDC_H */ | ||
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 4e0e6eac2a..d30489526a 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
@@ -174,6 +174,9 @@ | |||
174 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) | 174 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) |
175 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) | 175 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) |
176 | 176 | ||
177 | /* The PortalPlayer USB controller uses base address 0xc5000000 */ | ||
178 | #define USB_BASE 0xc5000000 | ||
179 | |||
177 | #define PROC_SLEEP 0x80000000 | 180 | #define PROC_SLEEP 0x80000000 |
178 | #define PROC_WAKE 0x0 | 181 | #define PROC_WAKE 0x0 |
179 | 182 | ||