1 files changed, 320 insertions, 0 deletions
diff --git a/firmware/export/arcotg_udc.h b/firmware/export/arcotg_udc.h
new file mode 100644
index 0000000000..e3bf93a52e
--- /dev/null
+++ b/firmware/export/arcotg_udc.h
@@ -0,0 +1,320 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Barry Wardell
+ *
+ * ARC OTG USB device driver based on code from the Linux Target Image Builder
+ * from Freescale - http://www.bitshrine.org/ and 
+ * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
+ * Adapted for Rockbox in January 2007
+ * Original file: drivers/usb/gadget/arcotg_udc.h
+ *
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Based on mpc-udc.h
+ * Author: Li Yang (leoli@freescale.com)
+ *         Jiang Bo (Tanya.jiang@freescale.com)
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+/*
+ * Freescale USB device/endpoint management registers
+ */
+#ifndef __ARCOTG_UDC_H
+#define __ARCOTG_UDC_H
+#include "cpu.h"
+#define ETIMEDOUT               1
+#define USB_MAX_ENDPOINTS       8
+#define USB_MAX_PIPES           (USB_MAX_ENDPOINTS*2)
+#define USB_MAX_CTRL_PAYLOAD    64
+/* USB DR device mode registers (Little Endian) */
+/* Identification registers */
+#define UDC_ID                  (*(volatile unsigned int *)(USB_BASE+0x000))
+#define UDC_HWGENERAL           (*(volatile unsigned int *)(USB_BASE+0x004))
+#define UDC_HWHOST              (*(volatile unsigned int *)(USB_BASE+0x008))
+#define UDC_HWTXBUF             (*(volatile unsigned int *)(USB_BASE+0x010))
+#define UDC_HWRXBUF             (*(volatile unsigned int *)(USB_BASE+0x014))
+/* Capability registers */
+#define UDC_CAPLENGTH           (*(volatile unsigned char *)(USB_BASE+0x100))   /* Capability Register Length */
+#define UDC_HCIVERSION          (*(volatile unsigned short *)(USB_BASE+0x102))  /* Host Controller Interface Version */
+#define UDC_HCSPARAMS           (*(volatile unsigned int *)(USB_BASE+0x104))    /* Host Controller Structual Parameters */
+#define UDC_HCCPARAMS           (*(volatile unsigned int *)(USB_BASE+0x108))    /* Host Controller Capability Parameters */
+#define UDC_DCIVERSION          (*(volatile unsigned short *)(USB_BASE+0x120))  /* Device Controller Interface Version */
+#define UDC_DCCPARAMS           (*(volatile unsigned int *)(USB_BASE+0x124))    /* Device Controller Capability Parameters */
+/* Operation registers */
+#define UDC_USBCMD              (*(volatile unsigned int *)(USB_BASE+0x140))    /* USB Command Register */
+#define UDC_USBSTS              (*(volatile unsigned int *)(USB_BASE+0x144))    /* USB Status Register */
+#define UDC_USBINTR             (*(volatile unsigned int *)(USB_BASE+0x148))    /* USB Interrupt Enable Register */
+#define UDC_FRINDEX             (*(volatile unsigned int *)(USB_BASE+0x14c))    /* Frame Index Register */
+#define UDC_DEVICEADDR          (*(volatile unsigned int *)(USB_BASE+0x154))    /* Device Address */
+#define UDC_ENDPOINTLISTADDR    (*(volatile unsigned int *)(USB_BASE+0x158))    /* Endpoint List Address Register */
+#define UDC_BURSTSIZE           (*(volatile unsigned int *)(USB_BASE+0x160))    /* Master Interface Data Burst Size Register */
+#define UDC_TXFILLTUNING        (*(volatile unsigned int *)(USB_BASE+0x164))    /* Transmit FIFO Tuning Controls Register */
+#define UDC_ULPIVIEW            (*(volatile unsigned int *)(USB_BASE+0x170))    
+#define UDC_CFGFLAG             (*(volatile unsigned int *)(USB_BASE+0x180))    /* Configure Flag Register */
+#define UDC_PORTSC1             (*(volatile unsigned int *)(USB_BASE+0x184))    /* Port 1 Status and Control Register */
+#define UDC_OTGSC               (*(volatile unsigned int *)(USB_BASE+0x1a4))    /* On-The-Go Status and Control */
+#define UDC_USBMODE             (*(volatile unsigned int *)(USB_BASE+0x1a8))    /* USB Mode Register */
+#define UDC_ENDPTSETUPSTAT      (*(volatile unsigned int *)(USB_BASE+0x1ac))    /* Endpoint Setup Status Register */
+#define UDC_ENDPTPRIME          (*(volatile unsigned int *)(USB_BASE+0x1b0))    /* Endpoint Initialization Register */
+#define UDC_ENDPTFLUSH          (*(volatile unsigned int *)(USB_BASE+0x1b4))    /* Endpoint Flush Register */
+#define UDC_ENDPTSTAT           (*(volatile unsigned int *)(USB_BASE+0x1b8))    /* Endpoint Status Register */
+#define UDC_ENDPTCOMPLETE       (*(volatile unsigned int *)(USB_BASE+0x1bc))    /* Endpoint Complete Register */
+#define UDC_ENDPTCTRL0          (*(volatile unsigned int *)(USB_BASE+0x1c0))    /* Endpoint 0 Control Register */
+#define UDC_ENDPTCTRL1          (*(volatile unsigned int *)(USB_BASE+0x1c4))    /* Endpoint 1 Control Register */
+#define UDC_ENDPTCTRL2          (*(volatile unsigned int *)(USB_BASE+0x1c8))    /* Endpoint 2 Control Register */
+#define UDC_ENDPTCTRL3          (*(volatile unsigned int *)(USB_BASE+0x1cc))    /* Endpoint 3 Control Register */
+#define UDC_ENDPTCTRL4          (*(volatile unsigned int *)(USB_BASE+0x1d0))    /* Endpoint 4 Control Register */
+#define UDC_ENDPTCTRL5          (*(volatile unsigned int *)(USB_BASE+0x1d4))    /* Endpoint 5 Control Register */
+#define UDC_ENDPTCTRL6          (*(volatile unsigned int *)(USB_BASE+0x1d8))    /* Endpoint 6 Control Register */
+#define UDC_ENDPTCTRL7          (*(volatile unsigned int *)(USB_BASE+0x1dc))    /* Endpoint 7 Control Register */
+#define UDC_ENDPTCTRL(x)        (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(x)))      /* Endpoint X Control Register */
+/* ep0 transfer state */
+#define WAIT_FOR_SETUP          0
+#define DATA_STATE_XMIT         1
+#define DATA_STATE_NEED_ZLP     2
+#define WAIT_FOR_OUT_STATUS     3
+#define DATA_STATE_RECV         4
+/* Frame Index Register Bit Masks */
+#define  USB_FRINDEX_MASKS                      (0x3fff)
+/* USB CMD  Register Bit Masks */
+#define  USB_CMD_RUN_STOP                       (0x00000001)
+#define  USB_CMD_CTRL_RESET                     (0x00000002)
+#define  USB_CMD_PERIODIC_SCHEDULE_EN           (0x00000010)
+#define  USB_CMD_ASYNC_SCHEDULE_EN              (0x00000020)
+#define  USB_CMD_INT_AA_DOORBELL                (0x00000040)
+#define  USB_CMD_ASP                            (0x00000300)
+#define  USB_CMD_ASYNC_SCH_PARK_EN              (0x00000800)
+#define  USB_CMD_SUTW                           (0x00002000)
+#define  USB_CMD_ATDTW                          (0x00004000)
+#define  USB_CMD_ITC                            (0x00FF0000)
+/* bit 15,3,2 are frame list size */
+#define  USB_CMD_FRAME_SIZE_1024                (0x00000000)
+#define  USB_CMD_FRAME_SIZE_512                 (0x00000004)
+#define  USB_CMD_FRAME_SIZE_256                 (0x00000008)
+#define  USB_CMD_FRAME_SIZE_128                 (0x0000000C)
+#define  USB_CMD_FRAME_SIZE_64                  (0x00008000)
+#define  USB_CMD_FRAME_SIZE_32                  (0x00008004)
+#define  USB_CMD_FRAME_SIZE_16                  (0x00008008)
+#define  USB_CMD_FRAME_SIZE_8                   (0x0000800C)
+/* bit 9-8 are async schedule park mode count */
+#define  USB_CMD_ASP_00                         (0x00000000)
+#define  USB_CMD_ASP_01                         (0x00000100)
+#define  USB_CMD_ASP_10                         (0x00000200)
+#define  USB_CMD_ASP_11                         (0x00000300)
+#define  USB_CMD_ASP_BIT_POS                    (8)
+/* bit 23-16 are interrupt threshold control */
+#define  USB_CMD_ITC_NO_THRESHOLD               (0x00000000)
+#define  USB_CMD_ITC_1_MICRO_FRM                (0x00010000)
+#define  USB_CMD_ITC_2_MICRO_FRM                (0x00020000)
+#define  USB_CMD_ITC_4_MICRO_FRM                (0x00040000)
+#define  USB_CMD_ITC_8_MICRO_FRM                (0x00080000)
+#define  USB_CMD_ITC_16_MICRO_FRM               (0x00100000)
+#define  USB_CMD_ITC_32_MICRO_FRM               (0x00200000)
+#define  USB_CMD_ITC_64_MICRO_FRM               (0x00400000)
+#define  USB_CMD_ITC_BIT_POS                    (16)
+/* USB STS Register Bit Masks */
+#define  USB_STS_INT                            (0x00000001)
+#define  USB_STS_ERR                            (0x00000002)
+#define  USB_STS_PORT_CHANGE                    (0x00000004)
+#define  USB_STS_FRM_LST_ROLL                   (0x00000008)
+#define  USB_STS_SYS_ERR                        (0x00000010)
+#define  USB_STS_IAA                            (0x00000020)
+#define  USB_STS_RESET                          (0x00000040)
+#define  USB_STS_SOF                            (0x00000080)
+#define  USB_STS_SUSPEND                        (0x00000100)
+#define  USB_STS_HC_HALTED                      (0x00001000)
+#define  USB_STS_RCL                            (0x00002000)
+#define  USB_STS_PERIODIC_SCHEDULE              (0x00004000)
+#define  USB_STS_ASYNC_SCHEDULE                 (0x00008000)
+/* USB INTR Register Bit Masks */
+#define  USB_INTR_INT_EN                        (0x00000001)
+#define  USB_INTR_ERR_INT_EN                    (0x00000002)
+#define  USB_INTR_PTC_DETECT_EN                 (0x00000004)
+#define  USB_INTR_FRM_LST_ROLL_EN               (0x00000008)
+#define  USB_INTR_SYS_ERR_EN                    (0x00000010)
+#define  USB_INTR_ASYN_ADV_EN                   (0x00000020)
+#define  USB_INTR_RESET_EN                      (0x00000040)
+#define  USB_INTR_SOF_EN                        (0x00000080)
+#define  USB_INTR_DEVICE_SUSPEND                (0x00000100)
+/* Device Address bit masks */
+#define  USB_DEVICE_ADDRESS_MASK                (0xFE000000)
+#define  USB_DEVICE_ADDRESS_BIT_POS             (25)
+/* endpoint list address bit masks */
+#define  USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
+/* PORTSCX  Register Bit Masks */
+#define  PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
+#define  PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
+#define  PORTSCX_PORT_ENABLE                    (0x00000004)
+#define  PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
+#define  PORTSCX_OVER_CURRENT_ACT               (0x00000010)
+#define  PORTSCX_OVER_CURRENT_CHG               (0x00000020)
+#define  PORTSCX_PORT_FORCE_RESUME              (0x00000040)
+#define  PORTSCX_PORT_SUSPEND                   (0x00000080)
+#define  PORTSCX_PORT_RESET                     (0x00000100)
+#define  PORTSCX_LINE_STATUS_BITS               (0x00000C00)
+#define  PORTSCX_PORT_POWER                     (0x00001000)
+#define  PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
+#define  PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
+#define  PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
+#define  PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
+#define  PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
+#define  PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
+#define  PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
+#define  PORTSCX_PORT_SPEED_MASK                (0x0C000000)
+#define  PORTSCX_PORT_WIDTH                     (0x10000000)
+#define  PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
+/* bit 11-10 are line status */
+#define  PORTSCX_LINE_STATUS_SE0                (0x00000000)
+#define  PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
+#define  PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
+#define  PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
+#define  PORTSCX_LINE_STATUS_BIT_POS            (10)
+/* bit 15-14 are port indicator control */
+#define  PORTSCX_PIC_OFF                        (0x00000000)
+#define  PORTSCX_PIC_AMBER                      (0x00004000)
+#define  PORTSCX_PIC_GREEN                      (0x00008000)
+#define  PORTSCX_PIC_UNDEF                      (0x0000C000)
+#define  PORTSCX_PIC_BIT_POS                    (14)
+/* bit 19-16 are port test control */
+#define  PORTSCX_PTC_DISABLE                    (0x00000000)
+#define  PORTSCX_PTC_JSTATE                     (0x00010000)
+#define  PORTSCX_PTC_KSTATE                     (0x00020000)
+#define  PORTSCX_PTC_SEQNAK                     (0x00030000)
+#define  PORTSCX_PTC_PACKET                     (0x00040000)
+#define  PORTSCX_PTC_FORCE_EN                   (0x00050000)
+#define  PORTSCX_PTC_BIT_POS                    (16)
+/* bit 27-26 are port speed */
+#define  PORTSCX_PORT_SPEED_FULL                (0x00000000)
+#define  PORTSCX_PORT_SPEED_LOW                 (0x04000000)
+#define  PORTSCX_PORT_SPEED_HIGH                (0x08000000)
+#define  PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
+#define  PORTSCX_SPEED_BIT_POS                  (26)
+/* bit 28 is parallel transceiver width for UTMI interface */
+#define  PORTSCX_PTW                            (0x10000000)
+#define  PORTSCX_PTW_8BIT                       (0x00000000)
+#define  PORTSCX_PTW_16BIT                      (0x10000000)
+/* bit 31-30 are port transceiver select */
+#define  PORTSCX_PTS_UTMI                       (0x00000000)
+#define  PORTSCX_PTS_ULPI                       (0x80000000)
+#define  PORTSCX_PTS_FSLS                       (0xC0000000)
+#define  PORTSCX_PTS_BIT_POS                    (30)
+/* USB MODE Register Bit Masks */
+#define  USB_MODE_CTRL_MODE_IDLE                (0x00000000)
+#define  USB_MODE_CTRL_MODE_DEVICE              (0x00000002)
+#define  USB_MODE_CTRL_MODE_HOST                (0x00000003)
+#define  USB_MODE_CTRL_MODE_RSV                 (0x00000001)
+#define  USB_MODE_SETUP_LOCK_OFF                (0x00000008)
+#define  USB_MODE_STREAM_DISABLE                (0x00000010)
+/* Endpoint Flush Register */
+#define  EPFLUSH_TX_OFFSET                      (0x00010000)
+#define  EPFLUSH_RX_OFFSET                      (0x00000000)
+/* Endpoint Setup Status bit masks */
+#define  EP_SETUP_STATUS_MASK                   (0x0000003F)
+#define  EP_SETUP_STATUS_EP0                    (0x00000001)
+/* ENDPOINTCTRLx  Register Bit Masks */
+#define  EPCTRL_TX_ENABLE                       (0x00800000)
+#define  EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
+#define  EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
+#define  EPCTRL_TX_TYPE                         (0x000C0000)
+#define  EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
+#define  EPCTRL_TX_EP_STALL                     (0x00010000)
+#define  EPCTRL_RX_ENABLE                       (0x00000080)
+#define  EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
+#define  EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
+#define  EPCTRL_RX_TYPE                         (0x0000000C)
+#define  EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
+#define  EPCTRL_RX_EP_STALL                     (0x00000001)
+/* bit 19-18 and 3-2 are endpoint type */
+#define  EPCTRL_EP_TYPE_CONTROL                 (0)
+#define  EPCTRL_EP_TYPE_ISO                     (1)
+#define  EPCTRL_EP_TYPE_BULK                    (2)
+#define  EPCTRL_EP_TYPE_INTERRUPT               (3)
+#define  EPCTRL_TX_EP_TYPE_SHIFT                (18)
+#define  EPCTRL_RX_EP_TYPE_SHIFT                (2)
+/* SNOOPn Register Bit Masks */
+#define  SNOOP_ADDRESS_MASK                     (0xFFFFF000)
+#define  SNOOP_SIZE_ZERO                        (0x00)    /* snooping disable */
+#define  SNOOP_SIZE_4KB                         (0x0B)    /* 4KB snoop size */
+#define  SNOOP_SIZE_8KB                         (0x0C)
+#define  SNOOP_SIZE_16KB                        (0x0D)
+#define  SNOOP_SIZE_32KB                        (0x0E)
+#define  SNOOP_SIZE_64KB                        (0x0F)
+#define  SNOOP_SIZE_128KB                       (0x10)
+#define  SNOOP_SIZE_256KB                       (0x11)
+#define  SNOOP_SIZE_512KB                       (0x12)
+#define  SNOOP_SIZE_1MB                         (0x13)
+#define  SNOOP_SIZE_2MB                         (0x14)
+#define  SNOOP_SIZE_4MB                         (0x15)
+#define  SNOOP_SIZE_8MB                         (0x16)
+#define  SNOOP_SIZE_16MB                        (0x17)
+#define  SNOOP_SIZE_32MB                        (0x18)
+#define  SNOOP_SIZE_64MB                        (0x19)
+#define  SNOOP_SIZE_128MB                       (0x1A)
+#define  SNOOP_SIZE_256MB                       (0x1B)
+#define  SNOOP_SIZE_512MB                       (0x1C)
+#define  SNOOP_SIZE_1GB                         (0x1D)
+#define  SNOOP_SIZE_2GB                         (0x1E)    /* 2GB snoop size */
+/* pri_ctrl Register Bit Masks */
+#define  PRI_CTRL_PRI_LVL1                      (0x0000000C)
+#define  PRI_CTRL_PRI_LVL0                      (0x00000003)
+/* si_ctrl Register Bit Masks */
+#define  SI_CTRL_ERR_DISABLE                    (0x00000010)
+#define  SI_CTRL_IDRC_DISABLE                   (0x00000008)
+#define  SI_CTRL_RD_SAFE_EN                     (0x00000004)
+#define  SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
+#define  SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
+/* control Register Bit Masks */
+#define  USB_CTRL_IOENB                         (0x00000004)
+#define  USB_CTRL_ULPI_INT0EN                   (0x00000001)
+/* Externally used functions */
+int dr_controller_setup(void);
+void dr_controller_run(void);
+void dr_controller_stop(void);
+#endif                /* __ARCOTG_UDC_H */

diff --git a/firmware/export/arcotg_udc.h b/firmware/export/arcotg_udc.h new file mode 100644 index 0000000000..e3bf93a52e --- /dev/null +++ b/firmware/export/arcotg_udc.h
@@ -0,0 +1,320 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* $Id$
	9	*
	10	* Copyright (C) 2007 by Barry Wardell
	11	*
	12	* ARC OTG USB device driver based on code from the Linux Target Image Builder
	13	* from Freescale - http://www.bitshrine.org/ and
	14	* http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
	15	* Adapted for Rockbox in January 2007
	16	* Original file: drivers/usb/gadget/arcotg_udc.h
	17	*
	18	* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
	19	*
	20	* Based on mpc-udc.h
	21	* Author: Li Yang (leoli@freescale.com)
	22	* Jiang Bo (Tanya.jiang@freescale.com)
	23	*
	24	* All files in this archive are subject to the GNU General Public License.
	25	* See the file COPYING in the source tree root for full license agreement.
	26	*
	27	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	28	* KIND, either express or implied.
	29	*
	30	****************************************************************************/
	31
	32	/*
	33	* Freescale USB device/endpoint management registers
	34	*/
	35	#ifndef __ARCOTG_UDC_H
	36	#define __ARCOTG_UDC_H
	37
	38	#include "cpu.h"
	39
	40	#define ETIMEDOUT 1
	41
	42	#define USB_MAX_ENDPOINTS 8
	43	#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2)
	44	#define USB_MAX_CTRL_PAYLOAD 64
	45
	46	/* USB DR device mode registers (Little Endian) */
	47	/* Identification registers */
	48	#define UDC_ID ((volatile unsigned int )(USB_BASE+0x000))
	49	#define UDC_HWGENERAL ((volatile unsigned int )(USB_BASE+0x004))
	50	#define UDC_HWHOST ((volatile unsigned int )(USB_BASE+0x008))
	51	#define UDC_HWTXBUF ((volatile unsigned int )(USB_BASE+0x010))
	52	#define UDC_HWRXBUF ((volatile unsigned int )(USB_BASE+0x014))
	53
	54	/* Capability registers */
	55	#define UDC_CAPLENGTH ((volatile unsigned char )(USB_BASE+0x100)) /* Capability Register Length */
	56	#define UDC_HCIVERSION ((volatile unsigned short )(USB_BASE+0x102)) /* Host Controller Interface Version */
	57	#define UDC_HCSPARAMS ((volatile unsigned int )(USB_BASE+0x104)) /* Host Controller Structual Parameters */
	58	#define UDC_HCCPARAMS ((volatile unsigned int )(USB_BASE+0x108)) /* Host Controller Capability Parameters */
	59	#define UDC_DCIVERSION ((volatile unsigned short )(USB_BASE+0x120)) /* Device Controller Interface Version */
	60	#define UDC_DCCPARAMS ((volatile unsigned int )(USB_BASE+0x124)) /* Device Controller Capability Parameters */
	61
	62	/* Operation registers */
	63	#define UDC_USBCMD ((volatile unsigned int )(USB_BASE+0x140)) /* USB Command Register */
	64	#define UDC_USBSTS ((volatile unsigned int )(USB_BASE+0x144)) /* USB Status Register */
	65	#define UDC_USBINTR ((volatile unsigned int )(USB_BASE+0x148)) /* USB Interrupt Enable Register */
	66	#define UDC_FRINDEX ((volatile unsigned int )(USB_BASE+0x14c)) /* Frame Index Register */
	67	#define UDC_DEVICEADDR ((volatile unsigned int )(USB_BASE+0x154)) /* Device Address */
	68	#define UDC_ENDPOINTLISTADDR ((volatile unsigned int )(USB_BASE+0x158)) /* Endpoint List Address Register */
	69	#define UDC_BURSTSIZE ((volatile unsigned int )(USB_BASE+0x160)) /* Master Interface Data Burst Size Register */
	70	#define UDC_TXFILLTUNING ((volatile unsigned int )(USB_BASE+0x164)) /* Transmit FIFO Tuning Controls Register */
	71	#define UDC_ULPIVIEW ((volatile unsigned int )(USB_BASE+0x170))
	72	#define UDC_CFGFLAG ((volatile unsigned int )(USB_BASE+0x180)) /* Configure Flag Register */
	73	#define UDC_PORTSC1 ((volatile unsigned int )(USB_BASE+0x184)) /* Port 1 Status and Control Register */
	74	#define UDC_OTGSC ((volatile unsigned int )(USB_BASE+0x1a4)) /* On-The-Go Status and Control */
	75	#define UDC_USBMODE ((volatile unsigned int )(USB_BASE+0x1a8)) /* USB Mode Register */
	76	#define UDC_ENDPTSETUPSTAT ((volatile unsigned int )(USB_BASE+0x1ac)) /* Endpoint Setup Status Register */
	77	#define UDC_ENDPTPRIME ((volatile unsigned int )(USB_BASE+0x1b0)) /* Endpoint Initialization Register */
	78	#define UDC_ENDPTFLUSH ((volatile unsigned int )(USB_BASE+0x1b4)) /* Endpoint Flush Register */
	79	#define UDC_ENDPTSTAT ((volatile unsigned int )(USB_BASE+0x1b8)) /* Endpoint Status Register */
	80	#define UDC_ENDPTCOMPLETE ((volatile unsigned int )(USB_BASE+0x1bc)) /* Endpoint Complete Register */
	81	#define UDC_ENDPTCTRL0 ((volatile unsigned int )(USB_BASE+0x1c0)) /* Endpoint 0 Control Register */
	82	#define UDC_ENDPTCTRL1 ((volatile unsigned int )(USB_BASE+0x1c4)) /* Endpoint 1 Control Register */
	83	#define UDC_ENDPTCTRL2 ((volatile unsigned int )(USB_BASE+0x1c8)) /* Endpoint 2 Control Register */
	84	#define UDC_ENDPTCTRL3 ((volatile unsigned int )(USB_BASE+0x1cc)) /* Endpoint 3 Control Register */
	85	#define UDC_ENDPTCTRL4 ((volatile unsigned int )(USB_BASE+0x1d0)) /* Endpoint 4 Control Register */
	86	#define UDC_ENDPTCTRL5 ((volatile unsigned int )(USB_BASE+0x1d4)) /* Endpoint 5 Control Register */
	87	#define UDC_ENDPTCTRL6 ((volatile unsigned int )(USB_BASE+0x1d8)) /* Endpoint 6 Control Register */
	88	#define UDC_ENDPTCTRL7 ((volatile unsigned int )(USB_BASE+0x1dc)) /* Endpoint 7 Control Register */
	89	#define UDC_ENDPTCTRL(x) ((volatile unsigned int )(USB_BASE+0x1c0+4(x))) / Endpoint X Control Register */
	90
	91	/* ep0 transfer state */
	92	#define WAIT_FOR_SETUP 0
	93	#define DATA_STATE_XMIT 1
	94	#define DATA_STATE_NEED_ZLP 2
	95	#define WAIT_FOR_OUT_STATUS 3
	96	#define DATA_STATE_RECV 4
	97
	98	/* Frame Index Register Bit Masks */
	99	#define USB_FRINDEX_MASKS (0x3fff)
	100
	101	/* USB CMD Register Bit Masks */
	102	#define USB_CMD_RUN_STOP (0x00000001)
	103	#define USB_CMD_CTRL_RESET (0x00000002)
	104	#define USB_CMD_PERIODIC_SCHEDULE_EN (0x00000010)
	105	#define USB_CMD_ASYNC_SCHEDULE_EN (0x00000020)
	106	#define USB_CMD_INT_AA_DOORBELL (0x00000040)
	107	#define USB_CMD_ASP (0x00000300)
	108	#define USB_CMD_ASYNC_SCH_PARK_EN (0x00000800)
	109	#define USB_CMD_SUTW (0x00002000)
	110	#define USB_CMD_ATDTW (0x00004000)
	111	#define USB_CMD_ITC (0x00FF0000)
	112
	113	/* bit 15,3,2 are frame list size */
	114	#define USB_CMD_FRAME_SIZE_1024 (0x00000000)
	115	#define USB_CMD_FRAME_SIZE_512 (0x00000004)
	116	#define USB_CMD_FRAME_SIZE_256 (0x00000008)
	117	#define USB_CMD_FRAME_SIZE_128 (0x0000000C)
	118	#define USB_CMD_FRAME_SIZE_64 (0x00008000)
	119	#define USB_CMD_FRAME_SIZE_32 (0x00008004)
	120	#define USB_CMD_FRAME_SIZE_16 (0x00008008)
	121	#define USB_CMD_FRAME_SIZE_8 (0x0000800C)
	122
	123	/* bit 9-8 are async schedule park mode count */
	124	#define USB_CMD_ASP_00 (0x00000000)
	125	#define USB_CMD_ASP_01 (0x00000100)
	126	#define USB_CMD_ASP_10 (0x00000200)
	127	#define USB_CMD_ASP_11 (0x00000300)
	128	#define USB_CMD_ASP_BIT_POS (8)
	129
	130	/* bit 23-16 are interrupt threshold control */
	131	#define USB_CMD_ITC_NO_THRESHOLD (0x00000000)
	132	#define USB_CMD_ITC_1_MICRO_FRM (0x00010000)
	133	#define USB_CMD_ITC_2_MICRO_FRM (0x00020000)
	134	#define USB_CMD_ITC_4_MICRO_FRM (0x00040000)
	135	#define USB_CMD_ITC_8_MICRO_FRM (0x00080000)
	136	#define USB_CMD_ITC_16_MICRO_FRM (0x00100000)
	137	#define USB_CMD_ITC_32_MICRO_FRM (0x00200000)
	138	#define USB_CMD_ITC_64_MICRO_FRM (0x00400000)
	139	#define USB_CMD_ITC_BIT_POS (16)
	140
	141	/* USB STS Register Bit Masks */
	142	#define USB_STS_INT (0x00000001)
	143	#define USB_STS_ERR (0x00000002)
	144	#define USB_STS_PORT_CHANGE (0x00000004)
	145	#define USB_STS_FRM_LST_ROLL (0x00000008)
	146	#define USB_STS_SYS_ERR (0x00000010)
	147	#define USB_STS_IAA (0x00000020)
	148	#define USB_STS_RESET (0x00000040)
	149	#define USB_STS_SOF (0x00000080)
	150	#define USB_STS_SUSPEND (0x00000100)
	151	#define USB_STS_HC_HALTED (0x00001000)
	152	#define USB_STS_RCL (0x00002000)
	153	#define USB_STS_PERIODIC_SCHEDULE (0x00004000)
	154	#define USB_STS_ASYNC_SCHEDULE (0x00008000)
	155
	156	/* USB INTR Register Bit Masks */
	157	#define USB_INTR_INT_EN (0x00000001)
	158	#define USB_INTR_ERR_INT_EN (0x00000002)
	159	#define USB_INTR_PTC_DETECT_EN (0x00000004)
	160	#define USB_INTR_FRM_LST_ROLL_EN (0x00000008)
	161	#define USB_INTR_SYS_ERR_EN (0x00000010)
	162	#define USB_INTR_ASYN_ADV_EN (0x00000020)
	163	#define USB_INTR_RESET_EN (0x00000040)
	164	#define USB_INTR_SOF_EN (0x00000080)
	165	#define USB_INTR_DEVICE_SUSPEND (0x00000100)
	166
	167	/* Device Address bit masks */
	168	#define USB_DEVICE_ADDRESS_MASK (0xFE000000)
	169	#define USB_DEVICE_ADDRESS_BIT_POS (25)
	170
	171	/* endpoint list address bit masks */
	172	#define USB_EP_LIST_ADDRESS_MASK (0xfffff800)
	173
	174	/* PORTSCX Register Bit Masks */
	175	#define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001)
	176	#define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002)
	177	#define PORTSCX_PORT_ENABLE (0x00000004)
	178	#define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008)
	179	#define PORTSCX_OVER_CURRENT_ACT (0x00000010)
	180	#define PORTSCX_OVER_CURRENT_CHG (0x00000020)
	181	#define PORTSCX_PORT_FORCE_RESUME (0x00000040)
	182	#define PORTSCX_PORT_SUSPEND (0x00000080)
	183	#define PORTSCX_PORT_RESET (0x00000100)
	184	#define PORTSCX_LINE_STATUS_BITS (0x00000C00)
	185	#define PORTSCX_PORT_POWER (0x00001000)
	186	#define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000)
	187	#define PORTSCX_PORT_TEST_CTRL (0x000F0000)
	188	#define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000)
	189	#define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000)
	190	#define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000)
	191	#define PORTSCX_PHY_LOW_POWER_SPD (0x00800000)
	192	#define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000)
	193	#define PORTSCX_PORT_SPEED_MASK (0x0C000000)
	194	#define PORTSCX_PORT_WIDTH (0x10000000)
	195	#define PORTSCX_PHY_TYPE_SEL (0xC0000000)
	196
	197	/* bit 11-10 are line status */
	198	#define PORTSCX_LINE_STATUS_SE0 (0x00000000)
	199	#define PORTSCX_LINE_STATUS_JSTATE (0x00000400)
	200	#define PORTSCX_LINE_STATUS_KSTATE (0x00000800)
	201	#define PORTSCX_LINE_STATUS_UNDEF (0x00000C00)
	202	#define PORTSCX_LINE_STATUS_BIT_POS (10)
	203
	204	/* bit 15-14 are port indicator control */
	205	#define PORTSCX_PIC_OFF (0x00000000)
	206	#define PORTSCX_PIC_AMBER (0x00004000)
	207	#define PORTSCX_PIC_GREEN (0x00008000)
	208	#define PORTSCX_PIC_UNDEF (0x0000C000)
	209	#define PORTSCX_PIC_BIT_POS (14)
	210
	211	/* bit 19-16 are port test control */
	212	#define PORTSCX_PTC_DISABLE (0x00000000)
	213	#define PORTSCX_PTC_JSTATE (0x00010000)
	214	#define PORTSCX_PTC_KSTATE (0x00020000)
	215	#define PORTSCX_PTC_SEQNAK (0x00030000)
	216	#define PORTSCX_PTC_PACKET (0x00040000)
	217	#define PORTSCX_PTC_FORCE_EN (0x00050000)
	218	#define PORTSCX_PTC_BIT_POS (16)
	219
	220	/* bit 27-26 are port speed */
	221	#define PORTSCX_PORT_SPEED_FULL (0x00000000)
	222	#define PORTSCX_PORT_SPEED_LOW (0x04000000)
	223	#define PORTSCX_PORT_SPEED_HIGH (0x08000000)
	224	#define PORTSCX_PORT_SPEED_UNDEF (0x0C000000)
	225	#define PORTSCX_SPEED_BIT_POS (26)
	226
	227	/* bit 28 is parallel transceiver width for UTMI interface */
	228	#define PORTSCX_PTW (0x10000000)
	229	#define PORTSCX_PTW_8BIT (0x00000000)
	230	#define PORTSCX_PTW_16BIT (0x10000000)
	231
	232	/* bit 31-30 are port transceiver select */
	233	#define PORTSCX_PTS_UTMI (0x00000000)
	234	#define PORTSCX_PTS_ULPI (0x80000000)
	235	#define PORTSCX_PTS_FSLS (0xC0000000)
	236	#define PORTSCX_PTS_BIT_POS (30)
	237
	238	/* USB MODE Register Bit Masks */
	239	#define USB_MODE_CTRL_MODE_IDLE (0x00000000)
	240	#define USB_MODE_CTRL_MODE_DEVICE (0x00000002)
	241	#define USB_MODE_CTRL_MODE_HOST (0x00000003)
	242	#define USB_MODE_CTRL_MODE_RSV (0x00000001)
	243	#define USB_MODE_SETUP_LOCK_OFF (0x00000008)
	244	#define USB_MODE_STREAM_DISABLE (0x00000010)
	245
	246	/* Endpoint Flush Register */
	247	#define EPFLUSH_TX_OFFSET (0x00010000)
	248	#define EPFLUSH_RX_OFFSET (0x00000000)
	249
	250	/* Endpoint Setup Status bit masks */
	251	#define EP_SETUP_STATUS_MASK (0x0000003F)
	252	#define EP_SETUP_STATUS_EP0 (0x00000001)
	253
	254	/* ENDPOINTCTRLx Register Bit Masks */
	255	#define EPCTRL_TX_ENABLE (0x00800000)
	256	#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */
	257	#define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */
	258	#define EPCTRL_TX_TYPE (0x000C0000)
	259	#define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */
	260	#define EPCTRL_TX_EP_STALL (0x00010000)
	261	#define EPCTRL_RX_ENABLE (0x00000080)
	262	#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */
	263	#define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */
	264	#define EPCTRL_RX_TYPE (0x0000000C)
	265	#define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */
	266	#define EPCTRL_RX_EP_STALL (0x00000001)
	267
	268	/* bit 19-18 and 3-2 are endpoint type */
	269	#define EPCTRL_EP_TYPE_CONTROL (0)
	270	#define EPCTRL_EP_TYPE_ISO (1)
	271	#define EPCTRL_EP_TYPE_BULK (2)
	272	#define EPCTRL_EP_TYPE_INTERRUPT (3)
	273	#define EPCTRL_TX_EP_TYPE_SHIFT (18)
	274	#define EPCTRL_RX_EP_TYPE_SHIFT (2)
	275
	276	/* SNOOPn Register Bit Masks */
	277	#define SNOOP_ADDRESS_MASK (0xFFFFF000)
	278	#define SNOOP_SIZE_ZERO (0x00) /* snooping disable */
	279	#define SNOOP_SIZE_4KB (0x0B) /* 4KB snoop size */
	280	#define SNOOP_SIZE_8KB (0x0C)
	281	#define SNOOP_SIZE_16KB (0x0D)
	282	#define SNOOP_SIZE_32KB (0x0E)
	283	#define SNOOP_SIZE_64KB (0x0F)
	284	#define SNOOP_SIZE_128KB (0x10)
	285	#define SNOOP_SIZE_256KB (0x11)
	286	#define SNOOP_SIZE_512KB (0x12)
	287	#define SNOOP_SIZE_1MB (0x13)
	288	#define SNOOP_SIZE_2MB (0x14)
	289	#define SNOOP_SIZE_4MB (0x15)
	290	#define SNOOP_SIZE_8MB (0x16)
	291	#define SNOOP_SIZE_16MB (0x17)
	292	#define SNOOP_SIZE_32MB (0x18)
	293	#define SNOOP_SIZE_64MB (0x19)
	294	#define SNOOP_SIZE_128MB (0x1A)
	295	#define SNOOP_SIZE_256MB (0x1B)
	296	#define SNOOP_SIZE_512MB (0x1C)
	297	#define SNOOP_SIZE_1GB (0x1D)
	298	#define SNOOP_SIZE_2GB (0x1E) /* 2GB snoop size */
	299
	300	/* pri_ctrl Register Bit Masks */
	301	#define PRI_CTRL_PRI_LVL1 (0x0000000C)
	302	#define PRI_CTRL_PRI_LVL0 (0x00000003)
	303
	304	/* si_ctrl Register Bit Masks */
	305	#define SI_CTRL_ERR_DISABLE (0x00000010)
	306	#define SI_CTRL_IDRC_DISABLE (0x00000008)
	307	#define SI_CTRL_RD_SAFE_EN (0x00000004)
	308	#define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002)
	309	#define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001)
	310
	311	/* control Register Bit Masks */
	312	#define USB_CTRL_IOENB (0x00000004)
	313	#define USB_CTRL_ULPI_INT0EN (0x00000001)
	314
	315	/* Externally used functions */
	316	int dr_controller_setup(void);
	317	void dr_controller_run(void);
	318	void dr_controller_stop(void);
	319
	320	#endif /* __ARCOTG_UDC_H */