diff options
Diffstat (limited to 'firmware/export/wm8978.h')
| -rw-r--r-- | firmware/export/wm8978.h | 945 |
1 files changed, 452 insertions, 493 deletions
diff --git a/firmware/export/wm8978.h b/firmware/export/wm8978.h index aca1250665..33a7c9d4f1 100644 --- a/firmware/export/wm8978.h +++ b/firmware/export/wm8978.h | |||
| @@ -21,551 +21,510 @@ | |||
| 21 | #ifndef _WM8978_H | 21 | #ifndef _WM8978_H |
| 22 | #define _WM8978_H | 22 | #define _WM8978_H |
| 23 | 23 | ||
| 24 | #define VOLUME_MIN -570 | 24 | #define VOLUME_MIN -900 |
| 25 | #define VOLUME_MAX 60 | 25 | #define VOLUME_MAX 60 |
| 26 | 26 | ||
| 27 | #define WM8978_I2C_ADDR 0x34 | 27 | int tenthdb2master(int db); |
| 28 | void audiohw_set_headphone_vol(int vol_l, int vol_r); | ||
| 29 | |||
| 30 | #define WMC_I2C_ADDR 0x34 | ||
| 28 | 31 | ||
| 29 | /* Registers */ | 32 | /* Registers */ |
| 30 | #define WM8978_SOFTWARE_RESET 0x00 | 33 | #define WMC_SOFTWARE_RESET 0x00 |
| 31 | #define WM8978_POWER_MANAGEMENT1 0x01 | 34 | #define WMC_POWER_MANAGEMENT1 0x01 |
| 32 | #define WM8978_POWER_MANAGEMENT2 0x02 | 35 | #define WMC_POWER_MANAGEMENT2 0x02 |
| 33 | #define WM8978_POWER_MANAGEMENT3 0x03 | 36 | #define WMC_POWER_MANAGEMENT3 0x03 |
| 34 | #define WM8978_AUDIO_INTERFACE 0x04 | 37 | #define WMC_AUDIO_INTERFACE 0x04 |
| 35 | #define WM8978_COMPANDING_CTRL 0x05 | 38 | #define WMC_COMPANDING_CTRL 0x05 |
| 36 | #define WM8978_CLOCK_GEN_CTRL 0x06 | 39 | #define WMC_CLOCK_GEN_CTRL 0x06 |
| 37 | #define WM8978_ADDITIONAL_CTRL 0x07 | 40 | #define WMC_ADDITIONAL_CTRL 0x07 |
| 38 | #define WM8978_GPIO 0x08 | 41 | #define WMC_GPIO 0x08 |
| 39 | #define WM8978_JACK_DETECT_CONTROL1 0x09 | 42 | #define WMC_JACK_DETECT_CONTROL1 0x09 |
| 40 | #define WM8978_DAC_CONTROL 0x0a | 43 | #define WMC_DAC_CONTROL 0x0a |
| 41 | #define WM8978_LEFT_DAC_DIGITAL_VOL 0x0b | 44 | #define WMC_LEFT_DAC_DIGITAL_VOL 0x0b |
| 42 | #define WM8978_RIGHT_DAC_DIGITAL_VOL 0x0c | 45 | #define WMC_RIGHT_DAC_DIGITAL_VOL 0x0c |
| 43 | #define WM8978_JACK_DETECT_CONTROL2 0x0d | 46 | #define WMC_JACK_DETECT_CONTROL2 0x0d |
| 44 | #define WM8978_ADC_CONTROL 0x0e | 47 | #define WMC_ADC_CONTROL 0x0e |
| 45 | #define WM8978_LEFT_ADC_DIGITAL_VOL 0x0f | 48 | #define WMC_LEFT_ADC_DIGITAL_VOL 0x0f |
| 46 | #define WM8978_RIGHT_ADC_DITIGAL_VOL 0x10 | 49 | #define WMC_RIGHT_ADC_DIGITAL_VOL 0x10 |
| 47 | #define WM8978_EQ1_LOW_SHELF 0x12 | 50 | #define WMC_EQ1_LOW_SHELF 0x12 |
| 48 | #define WM8978_EQ2_PEAK1 0x13 | 51 | #define WMC_EQ2_PEAK1 0x13 |
| 49 | #define WM8978_EQ3_PEAK2 0x14 | 52 | #define WMC_EQ3_PEAK2 0x14 |
| 50 | #define WM8978_EQ4_PEAK3 0x15 | 53 | #define WMC_EQ4_PEAK3 0x15 |
| 51 | #define WM8978_EQ5_HIGH_SHELF 0x16 | 54 | #define WMC_EQ5_HIGH_SHELF 0x16 |
| 52 | #define WM8978_DAC_LIMITER1 0x18 | 55 | #define WMC_DAC_LIMITER1 0x18 |
| 53 | #define WM8978_DAC_LIMITER2 0x19 | 56 | #define WMC_DAC_LIMITER2 0x19 |
| 54 | #define WM8978_NOTCH_FILTER1 0x1b | 57 | #define WMC_NOTCH_FILTER1 0x1b |
| 55 | #define WM8978_NOTCH_FILTER2 0x1c | 58 | #define WMC_NOTCH_FILTER2 0x1c |
| 56 | #define WM8978_NOTCH_FILTER3 0x1d | 59 | #define WMC_NOTCH_FILTER3 0x1d |
| 57 | #define WM8978_NOTCH_FILTER4 0x1e | 60 | #define WMC_NOTCH_FILTER4 0x1e |
| 58 | #define WM8978_ALC_CONTROL1 0x20 | 61 | #define WMC_ALC_CONTROL1 0x20 |
| 59 | #define WM8978_ALC_CONTROL2 0x21 | 62 | #define WMC_ALC_CONTROL2 0x21 |
| 60 | #define WM8978_ALC_CONTROL3 0x22 | 63 | #define WMC_ALC_CONTROL3 0x22 |
| 61 | #define WM8978_NOISE_GATE 0x23 | 64 | #define WMC_NOISE_GATE 0x23 |
| 62 | #define WM8978_PLL_N 0x24 | 65 | #define WMC_PLL_N 0x24 |
| 63 | #define WM8978_PLL_K1 0x25 | 66 | #define WMC_PLL_K1 0x25 |
| 64 | #define WM8978_PLL_K2 0x26 | 67 | #define WMC_PLL_K2 0x26 |
| 65 | #define WM8978_PLL_K3 0x27 | 68 | #define WMC_PLL_K3 0x27 |
| 66 | #define WM8978_3D_CONTROL 0x29 | 69 | #define WMC_3D_CONTROL 0x29 |
| 67 | #define WM8978_BEEP_CONTROL 0x2b | 70 | #define WMC_BEEP_CONTROL 0x2b |
| 68 | #define WM8978_INPUT_CTRL 0x2c | 71 | #define WMC_INPUT_CTRL 0x2c |
| 69 | #define WM8978_LEFT_INP_PGA_GAIN_CTRL 0x2d | 72 | #define WMC_LEFT_INP_PGA_GAIN_CTRL 0x2d |
| 70 | #define WM8978_RIGHT_INP_PGA_GAIN_CTRL 0x2e | 73 | #define WMC_RIGHT_INP_PGA_GAIN_CTRL 0x2e |
| 71 | #define WM8978_LEFT_ADC_BOOST_CTRL 0x2f | 74 | #define WMC_LEFT_ADC_BOOST_CTRL 0x2f |
| 72 | #define WM8978_RIGHT_ADC_BOOST_CTRL 0x30 | 75 | #define WMC_RIGHT_ADC_BOOST_CTRL 0x30 |
| 73 | #define WM8978_OUTPUT_CTRL 0x31 | 76 | #define WMC_OUTPUT_CTRL 0x31 |
| 74 | #define WM8978_LEFT_MIXER_CTRL 0x32 | 77 | #define WMC_LEFT_MIXER_CTRL 0x32 |
| 75 | #define WM8978_RIGHT_MIXER_CTRL 0x33 | 78 | #define WMC_RIGHT_MIXER_CTRL 0x33 |
| 76 | #define WM8978_LOUT1_HP_VOLUME_CTRL 0x34 | 79 | #define WMC_LOUT1_HP_VOLUME_CTRL 0x34 |
| 77 | #define WM8978_ROUT1_HP_VOLUME_CTRL 0x35 | 80 | #define WMC_ROUT1_HP_VOLUME_CTRL 0x35 |
| 78 | #define WM8978_LOUT2_SPK_VOLUME_CTRL 0x36 | 81 | #define WMC_LOUT2_SPK_VOLUME_CTRL 0x36 |
| 79 | #define WM8978_ROUT2_SPK_VOLUME_CTRL 0x37 | 82 | #define WMC_ROUT2_SPK_VOLUME_CTRL 0x37 |
| 80 | #define WM8978_OUT3_MIXER_CTRL 0x38 | 83 | #define WMC_OUT3_MIXER_CTRL 0x38 |
| 81 | #define WM8978_OUT4_MONO_MIXER_CTRL 0x39 | 84 | #define WMC_OUT4_MONO_MIXER_CTRL 0x39 |
| 85 | #define WMC_NUM_REGISTERS 0x3a | ||
| 82 | 86 | ||
| 83 | /* Register bitmasks */ | 87 | /* Register bitmasks */ |
| 84 | 88 | ||
| 85 | /* WM8978_SOFTWARE_RESET (0x00) */ | 89 | /* Volume update bit for volume registers */ |
| 86 | #define WM8978_RESET | 90 | #define WMC_VU (1 << 8) |
| 87 | /* Write any value */ | ||
| 88 | 91 | ||
| 89 | /* WM8978_POWER_MANAGEMENT1 (0x01) */ | 92 | /* Zero-crossing bit for volume registers */ |
| 90 | #define WM8978_BUFDCOMPEN (1 << 8) | 93 | #define WMC_ZC (1 << 7) |
| 91 | #define WM8978_OUT4MIXEN (1 << 7) | 94 | |
| 92 | #define WM8978_OUT3MIXEN (1 << 6) | 95 | /* Mute bit for volume registers */ |
| 93 | #define WM8978_PLLEN (1 << 5) | 96 | #define WMC_MUTE (1 << 6) |
| 94 | #define WM8978_MICBEN (1 << 4) | 97 | |
| 95 | #define WM8978_BIASEN (1 << 3) | 98 | /* Volume masks and macros for digital volumes */ |
| 96 | #define WM8978_BUFIOEN (1 << 2) | 99 | #define WMC_DVOL 0xff |
| 97 | #define WM8978_VMIDSEL (3 << 0) | 100 | #define WMC_DVOLr(x) ((x) & WMC_DVOL) |
| 98 | #define WM8978_VMIDSEL_OFF (0 << 0) | 101 | #define WMC_DVOLw(x) ((x) & WMC_DVOL) |
| 99 | #define WM8978_VMIDSEL_75K (1 << 0) | 102 | |
| 100 | #define WM8978_VMIDSEL_300K (2 << 0) | 103 | /* Volums masks and macros for analogue volumes */ |
| 101 | #define WM8978_VMIDSEL_5K (3 << 0) | 104 | #define WMC_AVOL 0x3f |
| 102 | 105 | #define WMC_AVOLr(x) ((x) & WMC_AVOLUME_MASK) | |
| 103 | /* WM8978_POWER_MANAGEMENT2 (0x02) */ | 106 | #define WMC_AVOLw(x) ((x) & WMC_AVOLUME_MASK) |
| 104 | #define WM8978_ROUT1EN (1 << 8) | 107 | |
| 105 | #define WM8978_LOUT1EN (1 << 7) | 108 | /* WMC_SOFTWARE_RESET (0x00) */ |
| 106 | #define WM8978_SLEEP (1 << 6) | 109 | #define WMC_RESET |
| 107 | #define WM8978_BOOSTENR (1 << 5) | 110 | /* Write any value */ |
| 108 | #define WM8978_BOOSTENL (1 << 4) | ||
| 109 | #define WM8978_INPPGAENR (1 << 3) | ||
| 110 | #define WM8978_INPPGAENL (1 << 2) | ||
| 111 | #define WM8978_ADCENR (1 << 1) | ||
| 112 | #define WM8978_ADCENL (1 << 0) | ||
| 113 | |||
| 114 | /* WM8978_POWER_MANAGEMENT3 (0x03) */ | ||
| 115 | #define WM8978_OUT4EN (1 << 8) | ||
| 116 | #define WM8978_OUT3EN (1 << 7) | ||
| 117 | #define WM8978_LOUT2EN (1 << 6) | ||
| 118 | #define WM8978_ROUT2EN (1 << 5) | ||
| 119 | #define WM8978_RMIXEN (1 << 3) | ||
| 120 | #define WM8978_LMIXEN (1 << 2) | ||
| 121 | #define WM8978_DACENR (1 << 1) | ||
| 122 | #define WM8978_DACENL (1 << 0) | ||
| 123 | |||
| 124 | /* WM8978_AUDIO_INTERFACE (0x04) */ | ||
| 125 | #define WM8978_BCP (1 << 8) | ||
| 126 | #define WM8978_LRP (1 << 7) | ||
| 127 | #define WM8978_WL (3 << 5) | ||
| 128 | #define WM8978_WL_16 (0 << 5) | ||
| 129 | #define WM8978_WL_20 (1 << 5) | ||
| 130 | #define WM8978_WL_24 (2 << 5) | ||
| 131 | #define WM8978_WL_32 (3 << 5) | ||
| 132 | #define WM8978_FMT (3 << 3) | ||
| 133 | #define WM8978_FMT_RJUST (0 << 3) | ||
| 134 | #define WM8978_FMT_LJUST (1 << 3) | ||
| 135 | #define WM8978_FMT_I2S (2 << 3) | ||
| 136 | #define WM8978_FMT_DSP_PCM (3 << 3) | ||
| 137 | #define WM8978_DACLRSWAP (1 << 2) | ||
| 138 | #define WM8978_ADCLRSWAP (1 << 1) | ||
| 139 | #define WM8978_MONO (1 << 0) | ||
| 140 | |||
| 141 | /* WM8978_COMPANDING_CTRL (0x05) */ | ||
| 142 | #define WM8978_WL8 (1 << 5) | ||
| 143 | #define WM8978_DAC_COMP (3 << 3) | ||
| 144 | #define WM8978_DAC_COMP_OFF (0 << 3) | ||
| 145 | #define WM8978_DAC_COMP_U_LAW (2 << 3) | ||
| 146 | #define WM8978_DAC_COMP_A_LAW (3 << 3) | ||
| 147 | #define WM8978_ADC_COMP (3 << 1) | ||
| 148 | #define WM8978_ADC_COMP_OFF (0 << 1) | ||
| 149 | #define WM8978_ADC_COMP_U_LAW (2 << 1) | ||
| 150 | #define WM8978_ADC_COMP_A_LAW (3 << 1) | ||
| 151 | #define WM8978_LOOPBACK (1 << 0) | ||
| 152 | |||
| 153 | /* WM8978_CLOCK_GEN_CTRL (0x06) */ | ||
| 154 | #define WM8978_CLKSEL (1 << 8) | ||
| 155 | #define WM8978_MCLKDIV (7 << 5) | ||
| 156 | #define WM8978_MCLKDIV_1 (0 << 5) | ||
| 157 | #define WM8978_MCLKDIV_1_5 (1 << 5) | ||
| 158 | #define WM8978_MCLKDIV_2 (2 << 5) | ||
| 159 | #define WM8978_MCLKDIV_3 (3 << 5) | ||
| 160 | #define WM8978_MCLKDIV_4 (4 << 5) | ||
| 161 | #define WM8978_MCLKDIV_6 (5 << 5) | ||
| 162 | #define WM8978_MCLKDIV_8 (6 << 5) | ||
| 163 | #define WM8978_MCLKDIV_12 (7 << 5) | ||
| 164 | #define WM8978_BCLKDIV (7 << 2) | ||
| 165 | #define WM8978_BCLKDIV_1 (0 << 2) | ||
| 166 | #define WM8978_BCLKDIV_2 (1 << 2) | ||
| 167 | #define WM8978_BCLKDIV_4 (2 << 2) | ||
| 168 | #define WM8978_BCLKDIV_8 (3 << 2) | ||
| 169 | #define WM8978_BCLKDIV_16 (4 << 2) | ||
| 170 | #define WM8978_BCLKDIV_32 (5 << 2) | ||
| 171 | #define WM8978_MS (1 << 0) | ||
| 172 | |||
| 173 | /* WM8978_ADDITIONAL_CTRL (0x07) */ | ||
| 174 | #define WM8978_SR (7 << 1) | ||
| 175 | #define WM8978_SLOWCLKEN (1 << 0) | ||
| 176 | |||
| 177 | /* WM8978_GPIO (0x08) */ | ||
| 178 | #define WM8978_OPCLKDIV (3 << 4) | ||
| 179 | #define WM8978_OPCLKDIV_1 (0 << 4) | ||
| 180 | #define WM8978_OPCLKDIV_2 (1 << 4) | ||
| 181 | #define WM8978_OPCLKDIV_3 (2 << 4) | ||
| 182 | #define WM8978_OPCLKDIV_4 (3 << 4) | ||
| 183 | #define WM8978_GPIO1POL (1 << 3) | ||
| 184 | #define WM8978_GPIO1SEL (7 << 0) | ||
| 185 | #define WM8978_GPIO1SEL_TEMP_OK (2 << 0) | ||
| 186 | #define WM8978_GPIO1SEL_AMUTE_ACTIVE (3 << 0) | ||
| 187 | #define WM8978_GPIO1SEL_PLL_CLK_OP (4 << 0) | ||
| 188 | #define WM8978_GPIO1SEL_PLL_LOCK (5 << 0) | ||
| 189 | #define WM8978_GPIO1SEL_LOGIC_1 (6 << 0) | ||
| 190 | #define WM8978_GPIO1SEL_LOGIC_0 (7 << 0) | ||
| 191 | |||
| 192 | /* WM8978_JACK_DETECT_CONTROL1 (0x09) */ | ||
| 193 | #define WM8978_JD_VMID (3 << 7) | ||
| 194 | #define WM8978_JD_VMID_EN_0 (1 << 7) | ||
| 195 | #define WM8978_JD_VMID_EN_1 (2 << 7) | ||
| 196 | #define WM8978_JD_EN (1 << 6) | ||
| 197 | #define WM8978_JD_SEL (3 << 4) | ||
| 198 | #define WM8978_JD_SEL_GPIO1 (0 << 4) | ||
| 199 | #define WM8978_JD_SEL_GPIO2 (1 << 4) | ||
| 200 | #define WM8978_JD_SEL_GPIO3 (2 << 4) | ||
| 201 | |||
| 202 | /* WM8978_DAC_CONTROL (0x0a) */ | ||
| 203 | #define WM8978_SOFT_MUTE (1 << 6) | ||
| 204 | #define WM8978_DACOSR_128 (1 << 3) | ||
| 205 | #define WM8978_AMUTE (1 << 2) | ||
| 206 | #define WM8978_DACPOLR (1 << 1) | ||
| 207 | #define WM8978_DACPOLL (1 << 0) | ||
| 208 | |||
| 209 | /* WM8978_LEFT_DAC_DIGITAL_VOL (0x0b) */ | ||
| 210 | #define WM8978_DACVUL (1 << 8) | ||
| 211 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ | ||
| 212 | #define WM8978_DACVOLL (0xff << 0) | ||
| 213 | #define WM8978_DACVOLLr(x) ((x) & WM8978_DACVOLL) | ||
| 214 | #define WM8978_DACVOLLw(x) ((x) & WM8978_DACVOLL) | ||
| 215 | 111 | ||
| 216 | /* WM8978_RIGHT_DAC_DIGITAL_VOL (0x0c) */ | 112 | /* WMC_POWER_MANAGEMENT1 (0x01) */ |
| 217 | #define WM8978_DACVUR (1 << 8) | 113 | #define WMC_BUFDCOMPEN (1 << 8) |
| 114 | #define WMC_OUT4MIXEN (1 << 7) | ||
| 115 | #define WMC_OUT3MIXEN (1 << 6) | ||
| 116 | #define WMC_PLLEN (1 << 5) | ||
| 117 | #define WMC_MICBEN (1 << 4) | ||
| 118 | #define WMC_BIASEN (1 << 3) | ||
| 119 | #define WMC_BUFIOEN (1 << 2) | ||
| 120 | #define WMC_VMIDSEL (3 << 0) | ||
| 121 | #define WMC_VMIDSEL_OFF (0 << 0) | ||
| 122 | #define WMC_VMIDSEL_75K (1 << 0) | ||
| 123 | #define WMC_VMIDSEL_300K (2 << 0) | ||
| 124 | #define WMC_VMIDSEL_5K (3 << 0) | ||
| 125 | |||
| 126 | /* WMC_POWER_MANAGEMENT2 (0x02) */ | ||
| 127 | #define WMC_ROUT1EN (1 << 8) | ||
| 128 | #define WMC_LOUT1EN (1 << 7) | ||
| 129 | #define WMC_SLEEP (1 << 6) | ||
| 130 | #define WMC_BOOSTENR (1 << 5) | ||
| 131 | #define WMC_BOOSTENL (1 << 4) | ||
| 132 | #define WMC_INPPGAENR (1 << 3) | ||
| 133 | #define WMC_INPPGAENL (1 << 2) | ||
| 134 | #define WMC_ADCENR (1 << 1) | ||
| 135 | #define WMC_ADCENL (1 << 0) | ||
| 136 | |||
| 137 | /* WMC_POWER_MANAGEMENT3 (0x03) */ | ||
| 138 | #define WMC_OUT4EN (1 << 8) | ||
| 139 | #define WMC_OUT3EN (1 << 7) | ||
| 140 | #define WMC_LOUT2EN (1 << 6) | ||
| 141 | #define WMC_ROUT2EN (1 << 5) | ||
| 142 | #define WMC_RMIXEN (1 << 3) | ||
| 143 | #define WMC_LMIXEN (1 << 2) | ||
| 144 | #define WMC_DACENR (1 << 1) | ||
| 145 | #define WMC_DACENL (1 << 0) | ||
| 146 | |||
| 147 | /* WMC_AUDIO_INTERFACE (0x04) */ | ||
| 148 | #define WMC_BCP (1 << 8) | ||
| 149 | #define WMC_LRP (1 << 7) | ||
| 150 | #define WMC_WL (3 << 5) | ||
| 151 | #define WMC_WL_16 (0 << 5) | ||
| 152 | #define WMC_WL_20 (1 << 5) | ||
| 153 | #define WMC_WL_24 (2 << 5) | ||
| 154 | #define WMC_WL_32 (3 << 5) | ||
| 155 | #define WMC_FMT (3 << 3) | ||
| 156 | #define WMC_FMT_RJUST (0 << 3) | ||
| 157 | #define WMC_FMT_LJUST (1 << 3) | ||
| 158 | #define WMC_FMT_I2S (2 << 3) | ||
| 159 | #define WMC_FMT_DSP_PCM (3 << 3) | ||
| 160 | #define WMC_DACLRSWAP (1 << 2) | ||
| 161 | #define WMC_ADCLRSWAP (1 << 1) | ||
| 162 | #define WMC_MONO (1 << 0) | ||
| 163 | |||
| 164 | /* WMC_COMPANDING_CTRL (0x05) */ | ||
| 165 | #define WMC_WL8 (1 << 5) | ||
| 166 | #define WMC_DAC_COMP (3 << 3) | ||
| 167 | #define WMC_DAC_COMP_OFF (0 << 3) | ||
| 168 | #define WMC_DAC_COMP_U_LAW (2 << 3) | ||
| 169 | #define WMC_DAC_COMP_A_LAW (3 << 3) | ||
| 170 | #define WMC_ADC_COMP (3 << 1) | ||
| 171 | #define WMC_ADC_COMP_OFF (0 << 1) | ||
| 172 | #define WMC_ADC_COMP_U_LAW (2 << 1) | ||
| 173 | #define WMC_ADC_COMP_A_LAW (3 << 1) | ||
| 174 | #define WMC_LOOPBACK (1 << 0) | ||
| 175 | |||
| 176 | /* WMC_CLOCK_GEN_CTRL (0x06) */ | ||
| 177 | #define WMC_CLKSEL (1 << 8) | ||
| 178 | #define WMC_MCLKDIV (7 << 5) | ||
| 179 | #define WMC_MCLKDIV_1 (0 << 5) | ||
| 180 | #define WMC_MCLKDIV_1_5 (1 << 5) | ||
| 181 | #define WMC_MCLKDIV_2 (2 << 5) | ||
| 182 | #define WMC_MCLKDIV_3 (3 << 5) | ||
| 183 | #define WMC_MCLKDIV_4 (4 << 5) | ||
| 184 | #define WMC_MCLKDIV_6 (5 << 5) | ||
| 185 | #define WMC_MCLKDIV_8 (6 << 5) | ||
| 186 | #define WMC_MCLKDIV_12 (7 << 5) | ||
| 187 | #define WMC_BCLKDIV (7 << 2) | ||
| 188 | #define WMC_BCLKDIV_1 (0 << 2) | ||
| 189 | #define WMC_BCLKDIV_2 (1 << 2) | ||
| 190 | #define WMC_BCLKDIV_4 (2 << 2) | ||
| 191 | #define WMC_BCLKDIV_8 (3 << 2) | ||
| 192 | #define WMC_BCLKDIV_16 (4 << 2) | ||
| 193 | #define WMC_BCLKDIV_32 (5 << 2) | ||
| 194 | #define WMC_MS (1 << 0) | ||
| 195 | |||
| 196 | /* WMC_ADDITIONAL_CTRL (0x07) */ | ||
| 197 | /* This configure the digital filter coefficients - pick the closest | ||
| 198 | * to what's really being used (greater than or equal). */ | ||
| 199 | #define WMC_SR (7 << 1) | ||
| 200 | #define WMC_SR_48KHZ (0 << 1) | ||
| 201 | #define WMC_SR_32KHZ (1 << 1) | ||
| 202 | #define WMC_SR_24KHZ (2 << 1) | ||
| 203 | #define WMC_SR_16KHZ (3 << 1) | ||
| 204 | #define WMC_SR_12KHZ (4 << 1) | ||
| 205 | #define WMC_SR_8KHZ (5 << 1) | ||
| 206 | /* 110-111=reserved */ | ||
| 207 | #define WMC_SLOWCLKEN (1 << 0) | ||
| 208 | |||
| 209 | /* WMC_GPIO (0x08) */ | ||
| 210 | #define WMC_OPCLKDIV (3 << 4) | ||
| 211 | #define WMC_OPCLKDIV_1 (0 << 4) | ||
| 212 | #define WMC_OPCLKDIV_2 (1 << 4) | ||
| 213 | #define WMC_OPCLKDIV_3 (2 << 4) | ||
| 214 | #define WMC_OPCLKDIV_4 (3 << 4) | ||
| 215 | #define WMC_GPIO1POL (1 << 3) | ||
| 216 | #define WMC_GPIO1SEL (7 << 0) | ||
| 217 | #define WMC_GPIO1SEL_TEMP_OK (2 << 0) | ||
| 218 | #define WMC_GPIO1SEL_AMUTE_ACTIVE (3 << 0) | ||
| 219 | #define WMC_GPIO1SEL_PLL_CLK_OP (4 << 0) | ||
| 220 | #define WMC_GPIO1SEL_PLL_LOCK (5 << 0) | ||
| 221 | #define WMC_GPIO1SEL_LOGIC_1 (6 << 0) | ||
| 222 | #define WMC_GPIO1SEL_LOGIC_0 (7 << 0) | ||
| 223 | |||
| 224 | /* WMC_JACK_DETECT_CONTROL1 (0x09) */ | ||
| 225 | #define WMC_JD_VMID (3 << 7) | ||
| 226 | #define WMC_JD_VMID_EN_0 (1 << 7) | ||
| 227 | #define WMC_JD_VMID_EN_1 (2 << 7) | ||
| 228 | #define WMC_JD_EN (1 << 6) | ||
| 229 | #define WMC_JD_SEL (3 << 4) | ||
| 230 | #define WMC_JD_SEL_GPIO1 (0 << 4) | ||
| 231 | #define WMC_JD_SEL_GPIO2 (1 << 4) | ||
| 232 | #define WMC_JD_SEL_GPIO3 (2 << 4) | ||
| 233 | |||
| 234 | /* WMC_DAC_CONTROL (0x0a) */ | ||
| 235 | #define WMC_SOFT_MUTE (1 << 6) | ||
| 236 | #define WMC_DACOSR_128 (1 << 3) | ||
| 237 | #define WMC_AMUTE (1 << 2) | ||
| 238 | #define WMC_DACPOLR (1 << 1) | ||
| 239 | #define WMC_DACPOLL (1 << 0) | ||
| 240 | |||
| 241 | /* WMC_LEFT_DAC_DIGITAL_VOL (0x0b) */ | ||
| 242 | /* WMC_RIGHT_DAC_DIGITAL_VOL (0x0c) */ | ||
| 218 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ | 243 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ |
| 219 | #define WM8978_DACVOLR (0xff << 0) | 244 | /* Use WMC_DVOL* macros */ |
| 220 | #define WM8978_DACVOLRr(x) ((x) & WM8978_DACVOLR) | 245 | |
| 221 | #define WM8978_DACVOLRw(x) ((x) & WM8978_DACVOLR) | 246 | /* WMC_JACK_DETECT_CONTROL2 (0x0d) */ |
| 222 | 247 | #define WMC_JD_EN1 (0xf << 4) | |
| 223 | /* WM8978_JACK_DETECT_CONTROL2 (0x0d) */ | 248 | #define WMC_OUT1_EN1 (1 << 4) |
| 224 | #define WM8978_JD_EN1 (0xf << 4) | 249 | #define WMC_OUT2_EN1 (2 << 4) |
| 225 | #define WM8978_OUT1_EN1 (1 << 4) | 250 | #define WMC_OUT3_EN1 (4 << 4) |
| 226 | #define WM8978_OUT2_EN1 (2 << 4) | 251 | #define WMC_OUT4_EN1 (8 << 4) |
| 227 | #define WM8978_OUT3_EN1 (4 << 4) | 252 | #define WMC_JD_EN0 (0xf << 0) |
| 228 | #define WM8978_OUT4_EN1 (8 << 4) | 253 | #define WMC_OUT1_EN0 (1 << 0) |
| 229 | #define WM8978_JD_EN0 (0xf << 0) | 254 | #define WMC_OUT2_EN0 (2 << 0) |
| 230 | #define WM8978_OUT1_EN0 (1 << 0) | 255 | #define WMC_OUT3_EN0 (4 << 0) |
| 231 | #define WM8978_OUT2_EN0 (2 << 0) | 256 | #define WMC_OUT4_EN0 (8 << 0) |
| 232 | #define WM8978_OUT3_EN0 (4 << 0) | 257 | |
| 233 | #define WM8978_OUT4_EN0 (8 << 0) | 258 | /* WMC_ADC_CONTROL (0x0e) */ |
| 234 | 259 | #define WMC_HPFEN (1 << 8) | |
| 235 | /* WM8978_ADC_CONTROL (0x0e) */ | 260 | #define WMC_HPFAPP (1 << 7) |
| 236 | #define WM8978_HPFEN (1 << 8) | 261 | #define WMC_HPFCUT (7 << 4) |
| 237 | #define WM8978_HPFAPP (1 << 7) | 262 | #define WMC_ADCOSR (1 << 3) |
| 238 | #define WM8978_HPFCUT (7 << 4) | 263 | #define WMC_ADCRPOL (1 << 1) |
| 239 | #define WM8978_ADCOSR (1 << 3) | 264 | #define WMC_ADCLPOL (1 << 0) |
| 240 | #define WM8978_ADCRPOL (1 << 1) | 265 | |
| 241 | #define WM8978_ADCLPOL (1 << 0) | 266 | /* WMC_LEFT_ADC_DIGITAL_VOL (0x0f) */ |
| 242 | 267 | /* WMC_RIGHT_ADC_DITIGAL_VOL (0x10) */ | |
| 243 | /* WM8978_LEFT_ADC_DIGITAL_VOL (0x0f) */ | ||
| 244 | /* WM8978_RIGHT_ADC_DITIGAL_VOL (0x10) */ | ||
| 245 | #define WM8978_ADCVU (1 << 8) | ||
| 246 | /* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */ | 268 | /* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */ |
| 247 | #define WM8978_ADCVOL (0xff << 0) | 269 | /*Use WMC_DVOL* macros */ |
| 248 | #define WM8978_ADCVOLr(x) ((x) & 0xff) | 270 | |
| 249 | #define WM8978_ADCVOLw(x) ((x) & 0xff) | 271 | /* Macros for EQ gain and cutoff */ |
| 250 | 272 | #define WMC_EQGC 0x1f | |
| 251 | /* WM8978_EQ1_LOW_SHELF (0x12) */ | 273 | #define WMC_EQGCr(x) ((x) & WMC_EQGC) |
| 252 | #define WM8978_EQ3DMODE (1 << 8) | 274 | #define WMC_EQGCw(x) ((x) & WMC_EQGC) |
| 253 | #define WM8978_EQ1C (3 << 5) /* Cutoff */ | 275 | |
| 254 | #define WM8978_EQ1C_80HZ (0 << 5) /* 80Hz */ | 276 | /* WMC_EQ1_LOW_SHELF (0x12) */ |
| 255 | #define WM8978_EQ1C_105HZ (1 << 5) /* 105Hz */ | 277 | #define WMC_EQ3DMODE (1 << 8) |
| 256 | #define WM8978_EQ1C_135HZ (2 << 5) /* 135Hz */ | 278 | #define WMC_EQ1C (3 << 5) /* Cutoff */ |
| 257 | #define WM8978_EQ1C_175HZ (3 << 5) /* 175Hz */ | 279 | #define WMC_EQ1C_80HZ (0 << 5) /* 80Hz */ |
| 280 | #define WMC_EQ1C_105HZ (1 << 5) /* 105Hz */ | ||
| 281 | #define WMC_EQ1C_135HZ (2 << 5) /* 135Hz */ | ||
| 282 | #define WMC_EQ1C_175HZ (3 << 5) /* 175Hz */ | ||
| 258 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */ | 283 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */ |
| 259 | #define WM8978_EQ1G (0x1f << 0) | 284 | |
| 260 | #define WM8978_EQ1Gr(x) ((x) & WM8978_EQ1G) | 285 | /* WMC_EQ2_PEAK1 (0x13) */ |
| 261 | #define WM8978_EQ1Gw(x) ((x) & WM8978_EQ1G) | 286 | #define WMC_EQ2BW (1 << 8) |
| 262 | 287 | #define WMC_EQ2C (3 << 5) /* Center */ | |
| 263 | /* WM8978_EQ2_PEAK1 (0x13) */ | 288 | #define WMC_EQ2C_230HZ (0 << 5) /* 230Hz */ |
| 264 | #define WM8978_EQ2BW (1 << 8) | 289 | #define WMC_EQ2C_300HZ (1 << 5) /* 300Hz */ |
| 265 | #define WM8978_EQ2C (3 << 5) /* Center */ | 290 | #define WMC_EQ2C_385HZ (2 << 5) /* 385Hz */ |
| 266 | #define WM8978_EQ2C_230HZ (0 << 5) /* 230Hz */ | 291 | #define WMC_EQ2C_500HZ (3 << 5) /* 500Hz */ |
| 267 | #define WM8978_EQ2C_300HZ (1 << 5) /* 300Hz */ | ||
| 268 | #define WM8978_EQ2C_385HZ (2 << 5) /* 385Hz */ | ||
| 269 | #define WM8978_EQ2C_500HZ (3 << 5) /* 500Hz */ | ||
| 270 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 292 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
| 271 | 11001-11111=reserved */ | 293 | 11001-11111=reserved */ |
| 272 | #define WM8978_EQ2G (0x1f << 0) | 294 | |
| 273 | #define WM8978_EQ2Gr(x) ((x) & WM8978_EQ2G) | 295 | /* WMC_EQ3_PEAK2 (0x14) */ |
| 274 | #define WM8978_EQ2Gw(x) ((x) & WM8978_EQ2G) | 296 | #define WMC_EQ3BW (1 << 8) |
| 275 | 297 | #define WMC_EQ3C (3 << 5) /* Center */ | |
| 276 | /* WM8978_EQ3_PEAK2 (0x14) */ | 298 | #define WMC_EQ3C_650HZ (0 << 5) /* 650Hz */ |
| 277 | #define WM8978_EQ3BW (1 << 8) | 299 | #define WMC_EQ3C_850HZ (1 << 5) /* 850Hz */ |
| 278 | #define WM8978_EQ3C (3 << 5) /* Center */ | 300 | #define WMC_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */ |
| 279 | #define WM8978_EQ3C_650HZ (0 << 5) /* 650Hz */ | 301 | #define WMC_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */ |
| 280 | #define WM8978_EQ3C_850HZ (1 << 5) /* 850Hz */ | ||
| 281 | #define WM8978_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */ | ||
| 282 | #define WM8978_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */ | ||
| 283 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 302 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
| 284 | 11001-11111=reserved */ | 303 | 11001-11111=reserved */ |
| 285 | #define WM8978_EQ3G (0x1f << 0) | 304 | |
| 286 | #define WM8978_EQ3Gr(x) ((x) & WM8978_EQ3G) | 305 | /* WMC_EQ4_PEAK3 (0x15) */ |
| 287 | #define WM8978_EQ3Gw(x) ((x) & WM8978_EQ3G) | 306 | #define WMC_EQ4BW (1 << 8) |
| 288 | 307 | #define WMC_EQ4C (3 << 5) /* Center */ | |
| 289 | /* WM8978_EQ4_PEAK3 (0x15) */ | 308 | #define WMC_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */ |
| 290 | #define WM8978_EQ4BW (1 << 8) | 309 | #define WMC_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */ |
| 291 | #define WM8978_EQ4C (3 << 5) /* Center */ | 310 | #define WMC_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */ |
| 292 | #define WM8978_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */ | 311 | #define WMC_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */ |
| 293 | #define WM8978_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */ | ||
| 294 | #define WM8978_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */ | ||
| 295 | #define WM8978_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */ | ||
| 296 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 312 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
| 297 | 11001-11111=reserved */ | 313 | 11001-11111=reserved */ |
| 298 | #define WM8978_EQ4G (0x1f << 0) | 314 | |
| 299 | #define WM8978_EQ4Gr(x) ((x) & WM8978_EQ4G) | 315 | /* WMC_EQ5_HIGH_SHELF (0x16) */ |
| 300 | #define WM8978_EQ4Gw(x) ((x) & WM8978_EQ4G) | 316 | #define WMC_EQ5C (3 << 5) /* Cutoff */ |
| 301 | 317 | #define WMC_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */ | |
| 302 | /* WM8978_EQ5_HIGH_SHELF (0x16) */ | 318 | #define WMC_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */ |
| 303 | #define WM8978_EQ5C (3 << 5) /* Cutoff */ | 319 | #define WMC_EQ5C_9KHZ (2 << 5) /* 9.0kHz */ |
| 304 | #define WM8978_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */ | 320 | #define WMC_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */ |
| 305 | #define WM8978_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */ | ||
| 306 | #define WM8978_EQ5C_9KHZ (2 << 5) /* 9.0kHz */ | ||
| 307 | #define WM8978_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */ | ||
| 308 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 321 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
| 309 | 11001-11111=reserved */ | 322 | 11001-11111=reserved */ |
| 310 | #define WM8978_EQ5G (0x1f << 0) | ||
| 311 | #define WM8978_EQ5Gr(x) ((x) & WM8978_EQ5G) | ||
| 312 | #define WM8978_EQ5Gw(x) ((x) & WM8978_EQ5G) | ||
| 313 | 323 | ||
| 314 | /* WM8978_DAC_LIMITER1 (0x18) */ | 324 | /* WMC_DAC_LIMITER1 (0x18) */ |
| 315 | #define WM8978_LIMEN (1 << 8) | 325 | #define WMC_LIMEN (1 << 8) |
| 316 | /* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */ | 326 | /* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */ |
| 317 | #define WM8978_LIMDCY (0xf << 4) | 327 | #define WMC_LIMDCY (0xf << 4) |
| 318 | #define WM8978_LIMDCYr(x) (((x) & WM8978_LIMDCY) >> 4) | 328 | #define WMC_LIMDCYr(x) (((x) & WMC_LIMDCY) >> 4) |
| 319 | #define WM8978_LIMDCYw(x) (((x) << 4) & WM8978_LIMDCY) | 329 | #define WMC_LIMDCYw(x) (((x) << 4) & WMC_LIMDCY) |
| 320 | /* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */ | 330 | /* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */ |
| 321 | #define WM8978_LIMATK (0xf << 0) | 331 | #define WMC_LIMATK (0xf << 0) |
| 322 | #define WM8978_LIMATKr(x) ((x) & WM8978_LIMATK) | 332 | #define WMC_LIMATKr(x) ((x) & WMC_LIMATK) |
| 323 | #define WM8978_LIMATKw(x) ((x) & WM8978_LIMATK) | 333 | #define WMC_LIMATKw(x) ((x) & WMC_LIMATK) |
| 324 | 334 | ||
| 325 | /* WM8978_DAC_LIMITER2 (0x19) */ | 335 | /* WMC_DAC_LIMITER2 (0x19) */ |
| 326 | #define WM8978_LIMLVL (7 << 4) | 336 | #define WMC_LIMLVL (7 << 4) |
| 327 | /* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */ | 337 | /* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */ |
| 328 | #define WM8978_LIMLVLr(x) (((x) & WM8978_LIMLVL) >> 4) | 338 | #define WMC_LIMLVLr(x) (((x) & WMC_LIMLVL) >> 4) |
| 329 | #define WM8978_LIMLVLw(x) (((x) << 4) & WM8978_LIMLVL) | 339 | #define WMC_LIMLVLw(x) (((x) << 4) & WMC_LIMLVL) |
| 330 | #define WM8978_LIMBOOST (0xf << 0) | 340 | #define WMC_LIMBOOST (0xf << 0) |
| 331 | /* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */ | 341 | /* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */ |
| 332 | #define WM8978_LIMBOOSTr(x) (((x) & WM8978_LIMBOOST) | 342 | #define WMC_LIMBOOSTr(x) (((x) & WMC_LIMBOOST) |
| 333 | #define WM8978_LIMBOOSTw(x) (((x) & WM8978_LIMBOOST) | 343 | #define WMC_LIMBOOSTw(x) (((x) & WMC_LIMBOOST) |
| 334 | 344 | ||
| 335 | /* WM8978_NOTCH_FILTER1 (0x1b) */ | 345 | |
| 336 | #define WM8978_NFU1 (1 << 8) | 346 | /* Generic notch filter bits and macros */ |
| 337 | #define WM8978_NFEN (1 << 7) | 347 | #define WMC_NFU (1 << 8) |
| 338 | #define WM8978_NFA0_13_7 (0x7f << 0) | 348 | #define WMC_NFA (0x7f << 0) |
| 339 | #define WM8978_NFA0_13_7r(x) ((x) & WM8978_NFA0_13_7) | 349 | #define WMC_NFAr(x) ((x) & WMC_NFA) |
| 340 | #define WM8978_NFA0_13_7w(x) ((x) & WM8978_NFA0_13_7) | 350 | #define WMC_NFAw(x) ((x) & WMC_NFA) |
| 341 | 351 | ||
| 342 | /* WM8978_NOTCH_FILTER2 (0x1c) */ | 352 | /* WMC_NOTCH_FILTER1 (0x1b) */ |
| 343 | #define WM8978_NFU2 (1 << 8) | 353 | #define WMC_NFEN (1 << 7) |
| 344 | #define WM8978_NFA0_6_0 (0x7f << 0) | 354 | /* WMC_NOTCH_FILTER2 (0x1c) */ |
| 345 | #define WM8978_NFA0_6_0r(x) ((x) & WM8978_NFA0_6_0) | 355 | /* WMC_NOTCH_FILTER3 (0x1d) */ |
| 346 | #define WM8978_NFA0_6_0w(x) ((x) & WM8978_NFA0_6_0) | 356 | /* WMC_NOTCH_FILTER4 (0x1e) */ |
| 347 | 357 | ||
| 348 | /* WM8978_NOTCH_FILTER3 (0x1d) */ | 358 | /* WMC_ALC_CONTROL1 (0x20) */ |
| 349 | #define WM8978_NFU3 (1 << 8) | 359 | #define WMC_ALCSEL (3 << 7) |
| 350 | #define WM8978_NFA1_13_7 (0x7f << 0) | 360 | #define WMC_ALCSEL_OFF (0 << 7) |
| 351 | #define WM8978_NFA1_13_7r(x) ((x) & WM8978_NFA1_13_7) | 361 | #define WMC_ALCSEL_RIGHT_ONLY (1 << 7) |
| 352 | #define WM8978_NFA1_13_7w(x) ((x) & WM8978_NFA1_13_7) | 362 | #define WMC_ALCSEL_LEFT_ONLY (2 << 7) |
| 353 | 363 | #define WMC_ALCSEL_BOTH_ON (3 << 7) | |
| 354 | /* WM8978_NOTCH_FILTER4 (0x1e) */ | ||
| 355 | #define WM8978_NFU4 (1 << 8) | ||
| 356 | #define WM8978_NFA1_6_0 (0x7f << 0) | ||
| 357 | #define WM8978_NFA1_6_0r(x) ((x) & WM8978_NFA1_6_0) | ||
| 358 | #define WM8978_NFA1_6_0w(x) ((x) & WM8978_NFA1_6_0) | ||
| 359 | |||
| 360 | /* WM8978_ALC_CONTROL1 (0x20) */ | ||
| 361 | #define WM8978_ALCSEL (3 << 7) | ||
| 362 | #define WM8978_ALCSEL_OFF (0 << 7) | ||
| 363 | #define WM8978_ALCSEL_RIGHT_ONLY (1 << 7) | ||
| 364 | #define WM8978_ALCSEL_LEFT_ONLY (2 << 7) | ||
| 365 | #define WM8978_ALCSEL_BOTH_ON (3 << 7) | ||
| 366 | /* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */ | 364 | /* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */ |
| 367 | #define WM8978_ALCMAXGAIN (7 << 3) | 365 | #define WMC_ALCMAXGAIN (7 << 3) |
| 368 | #define WM8978_ALCMAXGAINr(x) (((x) & WM8978_ALCMAXGAIN) >> 3) | 366 | #define WMC_ALCMAXGAINr(x) (((x) & WMC_ALCMAXGAIN) >> 3) |
| 369 | #define WM8978_ALCMAXGAINw(x) (((x) << 3) & WM8978_ALCMAXGAIN) | 367 | #define WMC_ALCMAXGAINw(x) (((x) << 3) & WMC_ALCMAXGAIN) |
| 370 | /* 000:-12dB...(6dB steps)...111:+30dB */ | 368 | /* 000:-12dB...(6dB steps)...111:+30dB */ |
| 371 | #define WM8978_ALCMINGAIN (7 << 0) | 369 | #define WMC_ALCMINGAIN (7 << 0) |
| 372 | #define WM8978_ALCMINGAINr(x) ((x) & WM8978_ALCMINGAIN) | 370 | #define WMC_ALCMINGAINr(x) ((x) & WMC_ALCMINGAIN) |
| 373 | #define WM8978_ALCMINGAINw(x) ((x) & WM8978_ALCMINGAIN) | 371 | #define WMC_ALCMINGAINw(x) ((x) & WMC_ALCMINGAIN) |
| 374 | 372 | ||
| 375 | /* WM8978_ALC_CONTROL2 (0x21) */ | 373 | /* WMC_ALC_CONTROL2 (0x21) */ |
| 376 | /* 0000=0ms, 0001=2.67ms, 0010=5.33ms... | 374 | /* 0000=0ms, 0001=2.67ms, 0010=5.33ms... |
| 377 | (2x with every step)...43.691s */ | 375 | (2x with every step)...43.691s */ |
| 378 | #define WM8978_ALCHLD (0xf << 4) | 376 | #define WMC_ALCHLD (0xf << 4) |
| 379 | #define WM8978_ALCHLDr(x) (((x) & WM8978_ALCHLD) >> 4) | 377 | #define WMC_ALCHLDr(x) (((x) & WMC_ALCHLD) >> 4) |
| 380 | #define WM8978_ALCHLDw(x) (((x) << 4) & WM8978_ALCHLD) | 378 | #define WMC_ALCHLDw(x) (((x) << 4) & WMC_ALCHLD) |
| 381 | /* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS... | 379 | /* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS... |
| 382 | (-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */ | 380 | (-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */ |
| 383 | #define WM8978_ALCLVL (0xf << 0) | 381 | #define WMC_ALCLVL (0xf << 0) |
| 384 | #define WM8978_ALCLVLr(x) ((x) & WM8978_ALCLVL) | 382 | #define WMC_ALCLVLr(x) ((x) & WMC_ALCLVL) |
| 385 | #define WM8978_ALCLVLw(x) ((x) & WM8978_ALCLVL) | 383 | #define WMC_ALCLVLw(x) ((x) & WMC_ALCLVL) |
| 386 | 384 | ||
| 387 | /* WM8978_ALC_CONTROL3 (0x22) */ | 385 | /* WMC_ALC_CONTROL3 (0x22) */ |
| 388 | #define WM8978_ALCMODE (1 << 8) | 386 | #define WMC_ALCMODE (1 << 8) |
| 389 | #define WM8978_ALCDCY (0xf << 4) | 387 | #define WMC_ALCDCY (0xf << 4) |
| 390 | #define WM8978_ALCATK (0xf << 0) | 388 | #define WMC_ALCATK (0xf << 0) |
| 391 | 389 | ||
| 392 | /* WM8978_NOISE_GATE (0x23) */ | 390 | /* WMC_NOISE_GATE (0x23) */ |
| 393 | #define WM8978_NGEN (1 << 3) | 391 | #define WMC_NGEN (1 << 3) |
| 394 | /* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */ | 392 | /* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */ |
| 395 | #define WM8978_NGTH (7 << 0) | 393 | #define WMC_NGTH (7 << 0) |
| 396 | #define WM8978_NGTHr(x) ((x) & WM8978_NGTH) | 394 | #define WMC_NGTHr(x) ((x) & WMC_NGTH) |
| 397 | #define WM8978_NGTHw(x) ((x) & WM8978_NGTH) | 395 | #define WMC_NGTHw(x) ((x) & WMC_NGTH) |
| 398 | 396 | ||
| 399 | /* WM8978_PLL_N (0x24) */ | 397 | /* WMC_PLL_N (0x24) */ |
| 400 | #define WM8978_PLL_PRESCALE (1 << 4) | 398 | #define WMC_PLL_PRESCALE (1 << 4) |
| 401 | #define WM8978_PLLN (0xf << 0) | 399 | #define WMC_PLLN (0xf << 0) |
| 402 | #define WM8978_PLLNr(x) ((x) & WM8978_PLLN) | 400 | #define WMC_PLLNr(x) ((x) & WMC_PLLN) |
| 403 | #define WM8978_PLLNw(x) ((x) & WM8978_PLLN) | 401 | #define WMC_PLLNw(x) ((x) & WMC_PLLN) |
| 404 | 402 | ||
| 405 | /* WM8978_PLL_K1 (0x25) */ | 403 | /* WMC_PLL_K1 (0x25) */ |
| 406 | #define WM8978_PLLK_23_18 (0x3f << 0) | 404 | #define WMC_PLLK_23_18 (0x3f << 0) |
| 407 | #define WM8978_PLLK_23_18r(x) ((x) & WM8978_PLLK_23_18) | 405 | #define WMC_PLLK_23_18r(x) ((x) & WMC_PLLK_23_18) |
| 408 | #define WM8978_PLLK_23_18w(x) ((x) & WM8978_PLLK_23_18) | 406 | #define WMC_PLLK_23_18w(x) ((x) & WMC_PLLK_23_18) |
| 409 | 407 | ||
| 410 | /* WM8978_PLL_K2 (0x26) */ | 408 | /* WMC_PLL_K2 (0x26) */ |
| 411 | #define WM8978_PLLK_17_9 (0x1ff << 0) | 409 | #define WMC_PLLK_17_9 (0x1ff << 0) |
| 412 | #define WM8978_PLLK_17_9r(x) ((x) & WM8978_PLLK_17_9) | 410 | #define WMC_PLLK_17_9r(x) ((x) & WMC_PLLK_17_9) |
| 413 | #define WM8978_PLLK_17_9w(x) ((x) & WM8978_PLLK_17_9) | 411 | #define WMC_PLLK_17_9w(x) ((x) & WMC_PLLK_17_9) |
| 414 | 412 | ||
| 415 | /* WM8978_PLL_K3 (0x27) */ | 413 | /* WMC_PLL_K3 (0x27) */ |
| 416 | #define WM8978_PLLK_8_0 (0x1ff << 0) | 414 | #define WMC_PLLK_8_0 (0x1ff << 0) |
| 417 | #define WM8978_PLLK_8_0r(x) ((x) & WM8978_PLLK_8_0) | 415 | #define WMC_PLLK_8_0r(x) ((x) & WMC_PLLK_8_0) |
| 418 | #define WM8978_PLLK_8_0w(x) ((x) & WM8978_PLLK_8_0) | 416 | #define WMC_PLLK_8_0w(x) ((x) & WMC_PLLK_8_0) |
| 419 | 417 | ||
| 420 | /* WM8978_3D_CONTROL (0x29) */ | 418 | /* WMC_3D_CONTROL (0x29) */ |
| 421 | /* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */ | 419 | /* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */ |
| 422 | #define WM8978_DEPTH3D (0xf << 0) | 420 | #define WMC_DEPTH3D (0xf << 0) |
| 423 | #define WM8978_DEPTH3Dw(x) ((x) & WM8978_DEPTH3D) | 421 | #define WMC_DEPTH3Dw(x) ((x) & WMC_DEPTH3D) |
| 424 | #define WM8978_DEPTH3Dr(x) ((x) & WM8978_DEPTH3D) | 422 | #define WMC_DEPTH3Dr(x) ((x) & WMC_DEPTH3D) |
| 425 | 423 | ||
| 426 | /* WM8978_BEEP_CONTROL (0x2b) */ | 424 | /* WMC_BEEP_CONTROL (0x2b) */ |
| 427 | #define WM8978_MUTERPGA2INV (1 << 5) | 425 | #define WMC_MUTERPGA2INV (1 << 5) |
| 428 | #define WM8978_INVROUT2 (1 << 4) | 426 | #define WMC_INVROUT2 (1 << 4) |
| 429 | /* 000=-15dB, 001=-12dB...111=+6dB */ | 427 | /* 000=-15dB, 001=-12dB...111=+6dB */ |
| 430 | #define WM8978_BEEPVOL (7 << 1) | 428 | #define WMC_BEEPVOL (7 << 1) |
| 431 | #define WM8978_BEEPVOLr(x) (((x) & WM8978_BEEPVOL) >> 1) | 429 | #define WMC_BEEPVOLr(x) (((x) & WMC_BEEPVOL) >> 1) |
| 432 | #define WM8978_BEEPVOLw(x) (((x) << 1) & WM8978_BEEPVOL) | 430 | #define WMC_BEEPVOLw(x) (((x) << 1) & WMC_BEEPVOL) |
| 433 | #define WM8978_BEEPEN (1 << 0) | 431 | #define WMC_BEEPEN (1 << 0) |
| 434 | 432 | ||
| 435 | /* WM8978_INPUT_CTRL (0x2c) */ | 433 | /* WMC_INPUT_CTRL (0x2c) */ |
| 436 | #define WM8978_MBVSEL (1 << 8) | 434 | #define WMC_MBVSEL (1 << 8) |
| 437 | #define WM8978_R2_2INPPGA (1 << 6) | 435 | #define WMC_R2_2INPPGA (1 << 6) |
| 438 | #define WM8978_RIN2INPPGA (1 << 5) | 436 | #define WMC_RIN2INPPGA (1 << 5) |
| 439 | #define WM8978_RIP2INPPGA (1 << 4) | 437 | #define WMC_RIP2INPPGA (1 << 4) |
| 440 | #define WM8978_L2_2INPPGA (1 << 2) | 438 | #define WMC_L2_2INPPGA (1 << 2) |
| 441 | #define WM8978_LIN2INPPGA (1 << 1) | 439 | #define WMC_LIN2INPPGA (1 << 1) |
| 442 | #define WM8978_LIP2INPPGA (1 << 0) | 440 | #define WMC_LIP2INPPGA (1 << 0) |
| 443 | 441 | ||
| 444 | /* WM8978_LEFT_INP_PGA_GAIN_CTRL (0x2d) */ | 442 | /* WMC_LEFT_INP_PGA_GAIN_CTRL (0x2d) */ |
| 445 | #define WM8978_INPPGAUPDATEL (1 << 8) | ||
| 446 | #define WM8978_NPPGAZCL (1 << 7) | ||
| 447 | #define WM8978_INPPGAMUTEL (1 << 6) | ||
| 448 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ | 443 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ |
| 449 | #define WM8978_INPPGAVOLL (0x3f << 0) | 444 | /* Uses WMC_AVOL* macros */ |
| 450 | #define WM8978_INPPGAVOLLr(x) ((x) & WM8978_INPPGAVOLL) | 445 | |
| 451 | #define WM8978_INPPGAVOLLw(x) ((x) & WM8978_INPPGAVOLL) | 446 | /* WMC_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */ |
| 452 | |||
| 453 | /* WM8978_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */ | ||
| 454 | #define WM8978_INPPGAUPDATER (1 << 8) | ||
| 455 | #define WM8978_NPPGAZCR (1 << 7) | ||
| 456 | #define WM8978_INPPGAMUTER (1 << 6) | ||
| 457 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ | 447 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ |
| 458 | #define WM8978_INPPGAVOLR (0x3f << 0) | 448 | /* Uses WMC_AVOL* macros */ |
| 459 | #define WM8978_INPPGAVOLRr(x) ((x) & WM8978_INPPGAVOLR) | ||
| 460 | #define WM8978_INPPGAVOLRw(x) ((x) & WM8978_INPPGAVOLR) | ||
| 461 | 449 | ||
| 462 | /* WM8978_LEFT_ADC_BOOST_CTRL (0x2f) */ | 450 | /* WMC_LEFT_ADC_BOOST_CTRL (0x2f) */ |
| 463 | #define WM8978_PGABOOSTL (1 << 8) | 451 | #define WMC_PGABOOSTL (1 << 8) |
| 464 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 452 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
| 465 | #define WM8978_L2_2BOOSTVOL (7 << 4) | 453 | #define WMC_L2_2BOOSTVOL (7 << 4) |
| 466 | #define WM8978_L2_2BOOSTVOLr(x) ((x) & WM8978_L2_2_BOOSTVOL) >> 4) | 454 | #define WMC_L2_2BOOSTVOLr(x) ((x) & WMC_L2_2_BOOSTVOL) >> 4) |
| 467 | #define WM8978_L2_2BOOSTVOLw(x) ((x) << 4) & WM8978_L2_2_BOOSTVOL) | 455 | #define WMC_L2_2BOOSTVOLw(x) ((x) << 4) & WMC_L2_2_BOOSTVOL) |
| 468 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 456 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
| 469 | #define WM8978_AUXL2BOOSTVOL (7 << 0) | 457 | #define WMC_AUXL2BOOSTVOL (7 << 0) |
| 470 | #define WM8978_AUXL2BOOSTVOLr(x) ((x) & WM8978_AUXL2BOOSTVOL) | 458 | #define WMC_AUXL2BOOSTVOLr(x) ((x) & WMC_AUXL2BOOSTVOL) |
| 471 | #define WM8978_AUXL2BOOSTVOLw(x) ((x) & WM8978_AUXL2BOOSTVOL) | 459 | #define WMC_AUXL2BOOSTVOLw(x) ((x) & WMC_AUXL2BOOSTVOL) |
| 472 | 460 | ||
| 473 | /* WM8978_RIGHT_ADC_BOOST_CTRL (0x30) */ | 461 | /* WMC_RIGHT_ADC_BOOST_CTRL (0x30) */ |
| 474 | #define WM8978_PGABOOSTR (1 << 8) | 462 | #define WMC_PGABOOSTR (1 << 8) |
| 475 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 463 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
| 476 | #define WM8978_R2_2_BOOSTVOL (7 << 4) | 464 | #define WMC_R2_2_BOOSTVOL (7 << 4) |
| 477 | #define WM8978_R2_2BOOSTVOLr(x) ((x) & WM8978_R2_2_BOOSTVOL) >> 4) | 465 | #define WMC_R2_2BOOSTVOLr(x) ((x) & WMC_R2_2_BOOSTVOL) >> 4) |
| 478 | #define WM8978_R2_2BOOSTVOLw(x) ((x) << 4) & WM8978_R2_2_BOOSTVOL) | 466 | #define WMC_R2_2BOOSTVOLw(x) ((x) << 4) & WMC_R2_2_BOOSTVOL) |
| 479 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 467 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
| 480 | #define WM8978_AUXR2BOOSTVOL (7 << 0) | 468 | #define WMC_AUXR2BOOSTVOL (7 << 0) |
| 481 | #define WM8978_AUXR2BOOSTVOLr(x) ((x) & WM8978_AUXR2BOOSTVOL) | 469 | #define WMC_AUXR2BOOSTVOLr(x) ((x) & WMC_AUXR2BOOSTVOL) |
| 482 | #define WM8978_AUXR2BOOSTVOLw(x) ((x) & WM8978_AUXR2BOOSTVOL) | 470 | #define WMC_AUXR2BOOSTVOLw(x) ((x) & WMC_AUXR2BOOSTVOL) |
| 483 | 471 | ||
| 484 | /* WM8978_OUTPUT_CTRL (0x31) */ | 472 | /* WMC_OUTPUT_CTRL (0x31) */ |
| 485 | #define WM8978_DACL2RMIX (1 << 6) | 473 | #define WMC_DACL2RMIX (1 << 6) |
| 486 | #define WM8978_DACR2LMIX (1 << 5) | 474 | #define WMC_DACR2LMIX (1 << 5) |
| 487 | #define WM8978_OUT4BOOST (1 << 4) | 475 | #define WMC_OUT4BOOST (1 << 4) |
| 488 | #define WM8978_OUT3BOOST (1 << 3) | 476 | #define WMC_OUT3BOOST (1 << 3) |
| 489 | #define WM8978_SPKBOOST (1 << 2) | 477 | #define WMC_SPKBOOST (1 << 2) |
| 490 | #define WM8978_TSDEN (1 << 1) | 478 | #define WMC_TSDEN (1 << 1) |
| 491 | #define WM8978_VROI (1 << 0) | 479 | #define WMC_VROI (1 << 0) |
| 492 | 480 | ||
| 493 | /* WM8978_LEFT_MIXER_CTRL (0x32) */ | 481 | /* WMC_LEFT_MIXER_CTRL (0x32) */ |
| 494 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 482 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
| 495 | #define WM8978_AUXLMIXVOL (7 << 6) | 483 | #define WMC_AUXLMIXVOL (7 << 6) |
| 496 | #define WM8978_AUXLMIXVOLr(x) ((x) & WM8978_AUXLMIXVOL) >> 6) | 484 | #define WMC_AUXLMIXVOLr(x) ((x) & WMC_AUXLMIXVOL) >> 6) |
| 497 | #define WM8978_AUXLMIXVOLw(x) ((x) << 6) & WM8978_AUXLMIXVOL) | 485 | #define WMC_AUXLMIXVOLw(x) ((x) << 6) & WMC_AUXLMIXVOL) |
| 498 | #define WM8978_AUXL2LMIX (1 << 5) | 486 | #define WMC_AUXL2LMIX (1 << 5) |
| 499 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 487 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
| 500 | #define WM8978_BYPLMIXVOL (7 << 2) | 488 | #define WMC_BYPLMIXVOL (7 << 2) |
| 501 | #define WM8978_BYPLMIXVOLr(x) ((x) & WM8978_BYPLMIXVOL) >> 2) | 489 | #define WMC_BYPLMIXVOLr(x) ((x) & WMC_BYPLMIXVOL) >> 2) |
| 502 | #define WM8978_BYPLMIXVOLw(x) ((x) << 2) & WM8978_BYPLMIXVOL) | 490 | #define WMC_BYPLMIXVOLw(x) ((x) << 2) & WMC_BYPLMIXVOL) |
| 503 | #define WM8978_BYPL2LMIX (1 << 1) | 491 | #define WMC_BYPL2LMIX (1 << 1) |
| 504 | #define WM8978_DACL2LMIX (1 << 0) | 492 | #define WMC_DACL2LMIX (1 << 0) |
| 505 | 493 | ||
| 506 | /* WM8978_RIGHT_MIXER_CTRL (0x33) */ | 494 | /* WMC_RIGHT_MIXER_CTRL (0x33) */ |
| 507 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 495 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
| 508 | #define WM8978_AUXRMIXVOL (7 << 6) | 496 | #define WMC_AUXRMIXVOL (7 << 6) |
| 509 | #define WM8978_AUXRMIXVOLr(x) ((x) & WM8978_AUXRMIXVOL) >> 6) | 497 | #define WMC_AUXRMIXVOLr(x) ((x) & WMC_AUXRMIXVOL) >> 6) |
| 510 | #define WM8978_AUXRMIXVOLw(x) ((x) << 6) & WM8978_AUXRMIXVOL) | 498 | #define WMC_AUXRMIXVOLw(x) ((x) << 6) & WMC_AUXRMIXVOL) |
| 511 | #define WM8978_AUXR2RMIX (1 << 5) | 499 | #define WMC_AUXR2RMIX (1 << 5) |
| 512 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 500 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
| 513 | #define WM8978_BYPRMIXVOL (7 << 2) | 501 | #define WMC_BYPRMIXVOL (7 << 2) |
| 514 | #define WM8978_BYPRMIXVOLr(x) ((x) & WM8978_BYPRMIXVOL) >> 2) | 502 | #define WMC_BYPRMIXVOLr(x) ((x) & WMC_BYPRMIXVOL) >> 2) |
| 515 | #define WM8978_BYPRMIXVOLw(x) ((x) << 2) & WM8978_BYPRMIXVOL) | 503 | #define WMC_BYPRMIXVOLw(x) ((x) << 2) & WMC_BYPRMIXVOL) |
| 516 | #define WM8978_BYPR2RMIX (1 << 1) | 504 | #define WMC_BYPR2RMIX (1 << 1) |
| 517 | #define WM8978_DACR2RMIX (1 << 0) | 505 | #define WMC_DACR2RMIX (1 << 0) |
| 518 | 506 | ||
| 519 | /* WM8978_LOUT1_HP_VOLUME_CTRL (0x34) */ | 507 | /* WMC_LOUT1_HP_VOLUME_CTRL (0x34) */ |
| 520 | #define WM8978_LHPVU (1 << 8) | 508 | /* WMC_ROUT1_HP_VOLUME_CTRL (0x35) */ |
| 521 | #define WM8978_LOUT1ZC (1 << 7) | 509 | /* WMC_LOUT2_SPK_VOLUME_CTRL (0x36) */ |
| 522 | #define WM8978_LOUT1MUTE (1 << 6) | 510 | /* WMC_ROUT2_SPK_VOLUME_CTRL (0x37) */ |
| 523 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
| 524 | #define WM8978_LOUT1VOL (0x3f << 0) | ||
| 525 | #define WM8978_LOUT1VOLr(x) ((x) & WM8978_LOUT1VOL) | ||
| 526 | #define WM8978_LOUT1VOLw(x) ((x) & WM8978_LOUT1VOL) | ||
| 527 | |||
| 528 | /* WM8978_ROUT1_HP_VOLUME_CTRL (0x35) */ | ||
| 529 | #define WM8978_RHPVU (1 << 8) | ||
| 530 | #define WM8978_ROUT1ZC (1 << 7) | ||
| 531 | #define WM8978_ROUT1MUTE (1 << 6) | ||
| 532 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
| 533 | #define WM8978_ROUT1VOL (0x3f << 0) | ||
| 534 | #define WM8978_ROUT1VOLr(x) ((x) & WM8978_ROUT1VOL) | ||
| 535 | #define WM8978_ROUT1VOLw(x) ((x) & WM8978_ROUT1VOL) | ||
| 536 | |||
| 537 | /* WM8978_LOUT2_SPK_VOLUME_CTRL (0x36) */ | ||
| 538 | #define WM8978_LSPKVU (1 << 8) | ||
| 539 | #define WM8978_LOUT2ZC (1 << 7) | ||
| 540 | #define WM8978_LOUT2MUTE (1 << 6) | ||
| 541 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
| 542 | #define WM8978_LOUT2VOL (0x3f << 0) | ||
| 543 | #define WM8978_LOUT2VOLr(x) ((x) & WM8978_LOUT2VOL) | ||
| 544 | #define WM8978_LOUT2VOLw(x) ((x) & WM8978_LOUT2VOL) | ||
| 545 | |||
| 546 | /* WM8978_ROUT2_SPK_VOLUME_CTRL (0x37) */ | ||
| 547 | #define WM8978_RSPKVU (1 << 8) | ||
| 548 | #define WM8978_ROUT2ZC (1 << 7) | ||
| 549 | #define WM8978_ROUT2MUTE (1 << 6) | ||
| 550 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | 511 | /* 000000=-57dB...111001=0dB...111111=+6dB */ |
| 551 | #define WM8978_ROUT2VOL (0x3f << 0) | 512 | /* Uses WMC_AVOL* macros */ |
| 552 | #define WM8978_ROUT2VOLr(x) ((x) & WM8978_ROUT2VOL) | 513 | |
| 553 | #define WM8978_ROUT2VOLw(x) ((x) & WM8978_ROUT2VOL) | 514 | /* WMC_OUT3_MIXER_CTRL (0x38) */ |
| 554 | 515 | #define WMC_OUT3MUTE (1 << 6) | |
| 555 | /* WM8978_OUT3_MIXER_CTRL (0x38) */ | 516 | #define WMC_OUT42OUT3 (1 << 3) |
| 556 | #define WM8978_OUT3MUTE (1 << 6) | 517 | #define WMC_BYPL2OUT3 (1 << 2) |
| 557 | #define WM8978_OUT42OUT3 (1 << 3) | 518 | #define WMC_LMIX2OUT3 (1 << 1) |
| 558 | #define WM8978_BYPL2OUT3 (1 << 2) | 519 | #define WMC_LDAC2OUT3 (1 << 0) |
| 559 | #define WM8978_LMIX2OUT3 (1 << 1) | 520 | |
| 560 | #define WM8978_LDAC2OUT3 (1 << 0) | 521 | /* WMC_OUT4_MONO_MIXER_CTRL (0x39) */ |
| 561 | 522 | #define WMC_OUT4MUTE (1 << 6) | |
| 562 | /* WM8978_OUT4_MONO_MIXER_CTRL (0x39) */ | 523 | #define WMC_HALFSIG (1 << 5) |
| 563 | #define WM8978_OUT4MUTE (1 << 6) | 524 | #define WMC_LMIX2OUT4 (1 << 4) |
| 564 | #define WM8978_HALFSIG (1 << 5) | 525 | #define WMC_LDAC2OUT4 (1 << 3) |
| 565 | #define WM8978_LMIX2OUT4 (1 << 4) | 526 | #define WMC_BYPR2OUT4 (1 << 2) |
| 566 | #define WM8978_LDAC2OUT4 (1 << 3) | 527 | #define WMC_RMIX2OUT4 (1 << 1) |
| 567 | #define WM8978_BYPR2OUT4 (1 << 2) | 528 | #define WMC_RDAC2OUT4 (1 << 0) |
| 568 | #define WM8978_RMIX2OUT4 (1 << 1) | ||
| 569 | #define WM8978_RDAC2OUT4 (1 << 0) | ||
| 570 | 529 | ||
| 571 | #endif /* _WM8978_H */ | 530 | #endif /* _WM8978_H */ |