diff options
-rw-r--r-- | firmware/drivers/audio/wm8978.c | 309 | ||||
-rwxr-xr-x | firmware/export/imx31l.h | 407 | ||||
-rw-r--r-- | firmware/export/wm8978.h | 945 | ||||
-rw-r--r-- | firmware/sound.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/imx31/debug-imx31.c | 121 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c | 228 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-imx31.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-target.h | 5 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | 36 |
9 files changed, 1538 insertions, 531 deletions
diff --git a/firmware/drivers/audio/wm8978.c b/firmware/drivers/audio/wm8978.c index 01f3d331bb..f94f1db87f 100644 --- a/firmware/drivers/audio/wm8978.c +++ b/firmware/drivers/audio/wm8978.c | |||
@@ -23,9 +23,20 @@ | |||
23 | #include "audiohw.h" | 23 | #include "audiohw.h" |
24 | #include "wmcodec.h" | 24 | #include "wmcodec.h" |
25 | #include "audio.h" | 25 | #include "audio.h" |
26 | //#define LOGF_ENABLE | ||
27 | #include "logf.h" | ||
26 | 28 | ||
27 | const struct sound_settings_info audiohw_settings[] = { | 29 | #define HW_VOL_MIN 0 |
28 | [SOUND_VOLUME] = {"dB", 0, 1, -58, 6, -25}, | 30 | #define HW_VOL_MUTE 0 |
31 | #define HW_VOL_MAX 96 | ||
32 | |||
33 | /* TODO: Define/refine an API for special hardware steps outside the | ||
34 | * main codec driver such as special GPIO handling. */ | ||
35 | extern void audiohw_enable_headphone_jack(bool enable); | ||
36 | |||
37 | const struct sound_settings_info audiohw_settings[] = | ||
38 | { | ||
39 | [SOUND_VOLUME] = {"dB", 0, 1, -90, 6, -25}, | ||
29 | [SOUND_BASS] = {"dB", 0, 1, -12, 12, 0}, | 40 | [SOUND_BASS] = {"dB", 0, 1, -12, 12, 0}, |
30 | [SOUND_TREBLE] = {"dB", 0, 1, -12, 12, 0}, | 41 | [SOUND_TREBLE] = {"dB", 0, 1, -12, 12, 0}, |
31 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, | 42 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, |
@@ -33,28 +44,318 @@ const struct sound_settings_info audiohw_settings[] = { | |||
33 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, | 44 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, |
34 | [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0}, | 45 | [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0}, |
35 | [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0}, | 46 | [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0}, |
47 | #if 0 | ||
36 | [SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16}, | 48 | [SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16}, |
49 | #endif | ||
37 | #if 0 | 50 | #if 0 |
38 | [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1}, | 51 | [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1}, |
39 | [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1}, | 52 | [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1}, |
40 | #endif | 53 | #endif |
41 | }; | 54 | }; |
42 | 55 | ||
56 | static uint16_t wmc_regs[WMC_NUM_REGISTERS] = | ||
57 | { | ||
58 | /* Initialized with post-reset default values - the 2-wire interface | ||
59 | * cannot be read. Or-in additional bits desired for some registers. */ | ||
60 | [0 ... WMC_NUM_REGISTERS-1] = 0x8000, /* To ID invalids in gaps */ | ||
61 | [WMC_SOFTWARE_RESET] = 0x000, | ||
62 | [WMC_POWER_MANAGEMENT1] = 0x000, | ||
63 | [WMC_POWER_MANAGEMENT2] = 0x000, | ||
64 | [WMC_POWER_MANAGEMENT3] = 0x000, | ||
65 | [WMC_AUDIO_INTERFACE] = 0x050, | ||
66 | [WMC_COMPANDING_CTRL] = 0x000, | ||
67 | [WMC_CLOCK_GEN_CTRL] = 0x140, | ||
68 | [WMC_ADDITIONAL_CTRL] = 0x000, | ||
69 | [WMC_GPIO] = 0x000, | ||
70 | [WMC_JACK_DETECT_CONTROL1] = 0x000, | ||
71 | [WMC_DAC_CONTROL] = 0x000, | ||
72 | [WMC_LEFT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU, | ||
73 | [WMC_RIGHT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU, | ||
74 | [WMC_JACK_DETECT_CONTROL2] = 0x000, | ||
75 | [WMC_ADC_CONTROL] = 0x100, | ||
76 | [WMC_LEFT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU, | ||
77 | [WMC_RIGHT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU, | ||
78 | [WMC_EQ1_LOW_SHELF] = 0x12c, | ||
79 | [WMC_EQ2_PEAK1] = 0x02c, | ||
80 | [WMC_EQ3_PEAK2] = 0x02c, | ||
81 | [WMC_EQ4_PEAK3] = 0x02c, | ||
82 | [WMC_EQ5_HIGH_SHELF] = 0x02c, | ||
83 | [WMC_DAC_LIMITER1] = 0x032, | ||
84 | [WMC_DAC_LIMITER2] = 0x000, | ||
85 | [WMC_NOTCH_FILTER1] = 0x000, | ||
86 | [WMC_NOTCH_FILTER2] = 0x000, | ||
87 | [WMC_NOTCH_FILTER3] = 0x000, | ||
88 | [WMC_NOTCH_FILTER4] = 0x000, | ||
89 | [WMC_ALC_CONTROL1] = 0x038, | ||
90 | [WMC_ALC_CONTROL2] = 0x00b, | ||
91 | [WMC_ALC_CONTROL3] = 0x032, | ||
92 | [WMC_NOISE_GATE] = 0x000, | ||
93 | [WMC_PLL_N] = 0x008, | ||
94 | [WMC_PLL_K1] = 0x00c, | ||
95 | [WMC_PLL_K2] = 0x093, | ||
96 | [WMC_PLL_K3] = 0x0e9, | ||
97 | [WMC_3D_CONTROL] = 0x000, | ||
98 | [WMC_BEEP_CONTROL] = 0x000, | ||
99 | [WMC_INPUT_CTRL] = 0x033, | ||
100 | [WMC_LEFT_INP_PGA_GAIN_CTRL] = 0x010, | ||
101 | [WMC_RIGHT_INP_PGA_GAIN_CTRL] = 0x010, | ||
102 | [WMC_LEFT_ADC_BOOST_CTRL] = 0x100, | ||
103 | [WMC_RIGHT_ADC_BOOST_CTRL] = 0x100, | ||
104 | [WMC_OUTPUT_CTRL] = 0x002, | ||
105 | [WMC_LEFT_MIXER_CTRL] = 0x001, | ||
106 | [WMC_RIGHT_MIXER_CTRL] = 0x001, | ||
107 | [WMC_LOUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC, | ||
108 | [WMC_ROUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC, | ||
109 | [WMC_LOUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC, | ||
110 | [WMC_ROUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC, | ||
111 | [WMC_OUT3_MIXER_CTRL] = 0x001, | ||
112 | [WMC_OUT4_MONO_MIXER_CTRL] = 0x001, | ||
113 | }; | ||
114 | |||
115 | struct | ||
116 | { | ||
117 | int vol_l; | ||
118 | int vol_r; | ||
119 | bool ahw_mute; | ||
120 | } wmc_vol = | ||
121 | { | ||
122 | 0, 0, false | ||
123 | }; | ||
124 | |||
125 | static void wmc_write(unsigned int reg, unsigned int val) | ||
126 | { | ||
127 | if (reg >= WMC_NUM_REGISTERS || (wmc_regs[reg] & 0x8000)) | ||
128 | { | ||
129 | logf("wm8978 invalid register: %d", reg); | ||
130 | return; | ||
131 | } | ||
132 | |||
133 | wmc_regs[reg] = val & ~0x8000; | ||
134 | wmcodec_write(reg, val); | ||
135 | } | ||
136 | |||
137 | static void wmc_set(unsigned int reg, unsigned int bits) | ||
138 | { | ||
139 | wmc_write(reg, wmc_regs[reg] | bits); | ||
140 | } | ||
141 | |||
142 | static void wmc_clear(unsigned int reg, unsigned int bits) | ||
143 | { | ||
144 | wmc_write(reg, wmc_regs[reg] & ~bits); | ||
145 | } | ||
146 | |||
147 | static void wmc_write_masked(unsigned int reg, unsigned int bits, | ||
148 | unsigned int mask) | ||
149 | { | ||
150 | wmc_write(reg, (wmc_regs[reg] & ~mask) | (bits & mask)); | ||
151 | } | ||
152 | |||
153 | /* convert tenth of dB volume (-890..60) to master volume register value | ||
154 | * (000000...111111) */ | ||
155 | int tenthdb2master(int db) | ||
156 | { | ||
157 | /* -90dB to +6dB 1dB steps (96 levels) 7bits */ | ||
158 | /* 1100000 == +6dB (0x60,96) */ | ||
159 | /* 1101010 == 0dB (0x5a,90) */ | ||
160 | /* 1000001 == -57dB (0x21,33,DAC) */ | ||
161 | /* 0000001 == -89dB (0x01,01) */ | ||
162 | /* 0000000 == -90dB (0x00,00,Mute) */ | ||
163 | if (db <= VOLUME_MIN) | ||
164 | { | ||
165 | return 0x0; | ||
166 | } | ||
167 | else | ||
168 | { | ||
169 | return (db - VOLUME_MIN) / 10; | ||
170 | } | ||
171 | } | ||
172 | |||
43 | void audiohw_preinit(void) | 173 | void audiohw_preinit(void) |
44 | { | 174 | { |
45 | wmcodec_write(WM8978_SOFTWARE_RESET, 0); | 175 | /* 1. Turn on external power supplies. Wait for supply voltage to settle. */ |
176 | |||
177 | /* Step 1 should be completed already. Reset and return all registers to | ||
178 | * defaults */ | ||
179 | wmcodec_write(WMC_SOFTWARE_RESET, 0xff); | ||
180 | sleep(HZ/10); | ||
181 | |||
182 | /* 2. Mute all analogue outputs */ | ||
183 | wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
184 | wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
185 | wmc_set(WMC_LOUT2_SPK_VOLUME_CTRL, WMC_MUTE); | ||
186 | wmc_set(WMC_ROUT2_SPK_VOLUME_CTRL, WMC_MUTE); | ||
187 | wmc_set(WMC_OUT3_MIXER_CTRL, WMC_MUTE); | ||
188 | wmc_set(WMC_OUT4_MONO_MIXER_CTRL, WMC_MUTE); | ||
189 | wmc_set(WMC_INPUT_CTRL, 0x000); | ||
190 | |||
191 | /* 3. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. */ | ||
192 | wmc_write(WMC_POWER_MANAGEMENT3, | ||
193 | WMC_RMIXEN | WMC_LMIXEN | WMC_DACENR | WMC_DACENL); | ||
194 | |||
195 | /* 4. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register | ||
196 | * R1. Wait for VMID supply to settle */ | ||
197 | wmc_write(WMC_POWER_MANAGEMENT1, WMC_BUFIOEN | WMC_VMIDSEL_300K); | ||
198 | sleep(HZ/10); | ||
199 | |||
200 | /* 5. Set BIASEN = 1 in register R1. */ | ||
201 | wmc_set(WMC_POWER_MANAGEMENT1, WMC_BIASEN); | ||
46 | } | 202 | } |
47 | 203 | ||
48 | void audiohw_postinit(void) | 204 | void audiohw_postinit(void) |
49 | { | 205 | { |
50 | sleep(HZ); | 206 | sleep(HZ); |
207 | |||
208 | /* 6. Set L/ROUTEN = 1 in register R2. */ | ||
209 | wmc_write(WMC_POWER_MANAGEMENT2, WMC_LOUT1EN | WMC_ROUT1EN); | ||
210 | |||
211 | /* 7. Enable other mixers as required */ | ||
212 | |||
213 | /* 8. Enable other outputs as required */ | ||
214 | |||
215 | /* 9. Set remaining registers */ | ||
216 | wmc_write(WMC_AUDIO_INTERFACE, WMC_WL_16 | WMC_FMT_I2S | ||
217 | | WMC_DACLRSWAP | WMC_ADCLRSWAP); | ||
218 | wmc_write(WMC_DAC_CONTROL, WMC_DACOSR_128 | WMC_AMUTE); | ||
219 | |||
220 | /* Specific to HW clocking */ | ||
221 | wmc_write(WMC_CLOCK_GEN_CTRL, WMC_MCLKDIV_1_5 | WMC_BCLKDIV_8 | WMC_MS); | ||
222 | wmc_write(WMC_ADDITIONAL_CTRL, WMC_SR_48KHZ); /* 44.1 */ | ||
223 | |||
224 | /* Initialize to minimum volume */ | ||
225 | wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, 189, WMC_DVOL); | ||
226 | wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, 0, WMC_AVOL); | ||
227 | wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, 189, WMC_DVOL); | ||
228 | wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, 0, WMC_AVOL); | ||
229 | |||
230 | /* ADC silenced */ | ||
231 | wmc_write_masked(WMC_LEFT_ADC_DIGITAL_VOL, 0x00, WMC_DVOL); | ||
232 | wmc_write_masked(WMC_RIGHT_ADC_DIGITAL_VOL, 0x00, WMC_DVOL); | ||
233 | |||
234 | audiohw_enable_headphone_jack(true); | ||
235 | } | ||
236 | |||
237 | void audiohw_set_headphone_vol(int vol_l, int vol_r) | ||
238 | { | ||
239 | int prev_l = wmc_vol.vol_l; | ||
240 | int prev_r = wmc_vol.vol_r; | ||
241 | int dac_l, dac_r; | ||
242 | |||
243 | wmc_vol.vol_l = vol_l; | ||
244 | wmc_vol.vol_r = vol_r; | ||
245 | |||
246 | /* When analogue volume falls below -57dB (0x00) start attenuating the | ||
247 | * DAC volume */ | ||
248 | if (vol_l >= 33) | ||
249 | { | ||
250 | if (vol_l > HW_VOL_MAX) | ||
251 | vol_l = HW_VOL_MAX; | ||
252 | |||
253 | dac_l = 255; | ||
254 | vol_l -= 33; | ||
255 | } | ||
256 | else | ||
257 | { | ||
258 | if (vol_l < HW_VOL_MIN) | ||
259 | vol_l = HW_VOL_MIN; | ||
260 | |||
261 | dac_l = 2*vol_l + 189; | ||
262 | vol_l = 0; | ||
263 | } | ||
264 | |||
265 | if (vol_r >= 33) | ||
266 | { | ||
267 | if (vol_r > HW_VOL_MAX) | ||
268 | vol_r = HW_VOL_MAX; | ||
269 | |||
270 | dac_r = 255; | ||
271 | vol_r -= 33; | ||
272 | } | ||
273 | else | ||
274 | { | ||
275 | if (vol_r < HW_VOL_MIN) | ||
276 | vol_r = HW_VOL_MIN; | ||
277 | |||
278 | dac_r = 2*vol_r + 189; | ||
279 | vol_r = 0; | ||
280 | } | ||
281 | |||
282 | /* Have to write both channels always to have the latching work */ | ||
283 | wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, dac_l, WMC_DVOL); | ||
284 | wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, vol_l, WMC_AVOL); | ||
285 | wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, dac_r, WMC_DVOL); | ||
286 | wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, vol_r, WMC_AVOL); | ||
287 | |||
288 | if (wmc_vol.vol_l > HW_VOL_MUTE) | ||
289 | { | ||
290 | /* Not muted and going up from mute level? */ | ||
291 | if (prev_l <= HW_VOL_MUTE && !wmc_vol.ahw_mute) | ||
292 | wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
293 | } | ||
294 | else | ||
295 | { | ||
296 | /* Going to mute level? */ | ||
297 | if (prev_l > HW_VOL_MUTE) | ||
298 | wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
299 | } | ||
300 | |||
301 | if (wmc_vol.vol_r > HW_VOL_MUTE) | ||
302 | { | ||
303 | /* Not muted and going up from mute level? */ | ||
304 | if (prev_r <= HW_VOL_MIN && !wmc_vol.ahw_mute) | ||
305 | wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
306 | } | ||
307 | else | ||
308 | { | ||
309 | /* Going to mute level? */ | ||
310 | if (prev_r > HW_VOL_MUTE) | ||
311 | wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
312 | } | ||
51 | } | 313 | } |
52 | 314 | ||
53 | void audiohw_close(void) | 315 | void audiohw_close(void) |
54 | { | 316 | { |
317 | /* 1. Mute all analogue outputs */ | ||
318 | audiohw_mute(true); | ||
319 | audiohw_enable_headphone_jack(false); | ||
320 | |||
321 | /* 2. Disable power management register 1. R1 = 00 */ | ||
322 | wmc_write(WMC_POWER_MANAGEMENT1, 0x000); | ||
323 | |||
324 | /* 3. Disable power management register 2. R2 = 00 */ | ||
325 | wmc_write(WMC_POWER_MANAGEMENT2, 0x000); | ||
326 | |||
327 | /* 4. Disable power management register 3. R3 = 00 */ | ||
328 | wmc_write(WMC_POWER_MANAGEMENT3, 0x000); | ||
329 | |||
330 | /* 5. Remove external power supplies. */ | ||
55 | } | 331 | } |
56 | 332 | ||
57 | void audiohw_mute(bool mute) | 333 | void audiohw_mute(bool mute) |
58 | { | 334 | { |
59 | (void)mute; | 335 | wmc_vol.ahw_mute = mute; |
336 | |||
337 | /* No DAC mute here, please - take care of each enabled output. */ | ||
338 | if (mute) | ||
339 | { | ||
340 | wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
341 | wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
342 | } | ||
343 | else | ||
344 | { | ||
345 | /* Unmute outputs not at mute level */ | ||
346 | if (wmc_vol.vol_l > HW_VOL_MUTE) | ||
347 | wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
348 | |||
349 | if (wmc_vol.vol_r > HW_VOL_MUTE) | ||
350 | wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE); | ||
351 | } | ||
352 | } | ||
353 | |||
354 | |||
355 | #ifdef HAVE_RECORDING | ||
356 | /* TODO */ | ||
357 | void audiohw_set_recvol(int left, int right, int type) | ||
358 | { | ||
359 | (void)left; (void)right; (void)type; | ||
60 | } | 360 | } |
361 | #endif | ||
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 8ea7750ac3..dc4cd99727 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -717,6 +717,296 @@ | |||
717 | 717 | ||
718 | /* I2DR - [7:0] Data */ | 718 | /* I2DR - [7:0] Data */ |
719 | 719 | ||
720 | /* AUDMUX */ | ||
721 | #define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00)) | ||
722 | #define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04)) | ||
723 | #define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08)) | ||
724 | #define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C)) | ||
725 | #define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10)) | ||
726 | #define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14)) | ||
727 | #define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18)) | ||
728 | #define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C)) | ||
729 | #define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20)) | ||
730 | #define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24)) | ||
731 | #define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28)) | ||
732 | #define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C)) | ||
733 | #define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30)) | ||
734 | #define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34)) | ||
735 | #define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38)) | ||
736 | |||
737 | #define AUDMUX_PTCR_TFS_DIR (1 << 31) | ||
738 | |||
739 | #define AUDMUX_PTCR_TFSEL (0xf << 27) | ||
740 | #define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27) | ||
741 | #define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27) | ||
742 | #define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27) | ||
743 | #define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27) | ||
744 | #define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27) | ||
745 | #define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27) | ||
746 | #define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27) | ||
747 | #define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27) | ||
748 | #define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27) | ||
749 | |||
750 | #define AUDMUX_PTCR_TCLKDIR (1 << 26) | ||
751 | |||
752 | #define AUDMUX_PTCR_TCSEL (0xf << 22) | ||
753 | #define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22) | ||
754 | #define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22) | ||
755 | #define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22) | ||
756 | #define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22) | ||
757 | #define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22) | ||
758 | #define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22) | ||
759 | #define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22) | ||
760 | #define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22) | ||
761 | #define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22) | ||
762 | |||
763 | #define AUDMUX_PTCR_RFSDIR (1 << 21) | ||
764 | |||
765 | #define AUDMUX_PTCR_RFSSEL (0xf << 17) | ||
766 | #define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17) | ||
767 | #define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17) | ||
768 | #define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17) | ||
769 | #define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17) | ||
770 | #define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17) | ||
771 | #define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17) | ||
772 | #define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17) | ||
773 | #define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17) | ||
774 | #define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17) | ||
775 | |||
776 | #define AUDMUX_PTCR_RCLKDIR (1 << 16) | ||
777 | |||
778 | #define AUDMUX_PTCR_RCSEL (0xf << 12) | ||
779 | #define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12) | ||
780 | #define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12) | ||
781 | #define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12) | ||
782 | #define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12) | ||
783 | #define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12) | ||
784 | #define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12) | ||
785 | #define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12) | ||
786 | #define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12) | ||
787 | #define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12) | ||
788 | #define AUDMUX_PTCR_SYN (1 << 11) | ||
789 | |||
790 | #define AUDMUX_PDCR_RXDSEL (0x7 << 13) | ||
791 | #define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13) | ||
792 | #define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13) | ||
793 | #define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13) | ||
794 | #define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13) | ||
795 | #define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13) | ||
796 | #define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13) | ||
797 | #define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13) | ||
798 | #define AUDMUX_PDCR_TXRXEN (1 << 12) | ||
799 | |||
800 | #define AUDMUX_CNMCR_BEN (1 << 18) | ||
801 | #define AUDMUX_CNMCR_FSPOL (1 << 17) | ||
802 | #define AUDMUX_CNMCR_CLKPOL (1 << 16) | ||
803 | |||
804 | #define AUDMUX_CNMCR_CNTHI (0xff << 8) | ||
805 | #define AUDMUX_CNMCR_CNTHIw(x) (((x) << 8) & AUDMUX_CNMCR_CNTHI) | ||
806 | |||
807 | #define AUDMUX_CNMCR_CNTLOW (0xff << 0) | ||
808 | #define AUDMUX_CNMCR_CNTLOWw(x) (((x) << 0) & AUDMUX_CNMCR_CNTLOW) | ||
809 | |||
810 | /* SSI */ | ||
811 | #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00)) | ||
812 | #define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04)) | ||
813 | #define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08)) | ||
814 | #define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C)) | ||
815 | #define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10)) | ||
816 | #define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14)) | ||
817 | #define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18)) | ||
818 | #define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C)) | ||
819 | #define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20)) | ||
820 | #define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24)) | ||
821 | #define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28)) | ||
822 | #define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C)) | ||
823 | #define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38)) | ||
824 | #define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C)) | ||
825 | #define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40)) | ||
826 | #define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44)) | ||
827 | #define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48)) | ||
828 | #define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C)) | ||
829 | |||
830 | #define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00)) | ||
831 | #define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04)) | ||
832 | #define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08)) | ||
833 | #define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C)) | ||
834 | #define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10)) | ||
835 | #define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14)) | ||
836 | #define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18)) | ||
837 | #define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C)) | ||
838 | #define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20)) | ||
839 | #define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24)) | ||
840 | #define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28)) | ||
841 | #define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C)) | ||
842 | #define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38)) | ||
843 | #define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C)) | ||
844 | #define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40)) | ||
845 | #define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44)) | ||
846 | #define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48)) | ||
847 | #define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C)) | ||
848 | |||
849 | /* SSI SCR */ | ||
850 | #define SSI_SCR_CLK_IST (0x1 << 9) | ||
851 | #define SSI_SCR_TCHN_EN (0x1 << 8) | ||
852 | #define SSI_SCR_SYS_CLK_EN (0x1 << 7) | ||
853 | |||
854 | #define SSI_SCR_I2S_MODE (0x3 << 5) | ||
855 | #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5) | ||
856 | #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5) | ||
857 | #define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5) | ||
858 | #define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5) | ||
859 | |||
860 | #define SSI_SCR_SYN (0x1 << 4) | ||
861 | #define SSI_SCR_NET (0x1 << 3) | ||
862 | #define SSI_SCR_RE (0x1 << 2) | ||
863 | #define SSI_SCR_TE (0x1 << 1) | ||
864 | #define SSI_SCR_SSIEN (0x1 << 0) | ||
865 | |||
866 | /* SSI SISR */ | ||
867 | #define SSI_SISR_CMDAU (0x1 << 18) | ||
868 | #define SSI_SISR_CMDDU (0x1 << 17) | ||
869 | #define SSI_SISR_RXT (0x1 << 16) | ||
870 | #define SSI_SISR_RDR1 (0x1 << 15) | ||
871 | #define SSI_SISR_RDR0 (0x1 << 14) | ||
872 | #define SSI_SISR_TDE1 (0x1 << 13) | ||
873 | #define SSI_SISR_TDE0 (0x1 << 12) | ||
874 | #define SSI_SISR_ROE1 (0x1 << 11) | ||
875 | #define SSI_SISR_ROE0 (0x1 << 10) | ||
876 | #define SSI_SISR_TUE1 (0x1 << 9) | ||
877 | #define SSI_SISR_TUE0 (0x1 << 8) | ||
878 | #define SSI_SISR_TFS (0x1 << 7) | ||
879 | #define SSI_SISR_RFS (0x1 << 6) | ||
880 | #define SSI_SISR_TLS (0x1 << 5) | ||
881 | #define SSI_SISR_RLS (0x1 << 4) | ||
882 | #define SSI_SISR_RFF1 (0x1 << 3) | ||
883 | #define SSI_SISR_RFF2 (0x1 << 2) | ||
884 | #define SSI_SISR_TFE1 (0x1 << 1) | ||
885 | #define SSI_SISR_TFE0 (0x1 << 0) | ||
886 | |||
887 | /* SSI SIER */ | ||
888 | #define SSI_SIER_RDMAE (0x1 << 22) | ||
889 | #define SSI_SIER_RIE (0x1 << 21) | ||
890 | #define SSI_SIER_TDMAE (0x1 << 20) | ||
891 | #define SSI_SIER_TIE (0x1 << 19) | ||
892 | #define SSI_SIER_CMDAU (0x1 << 18) | ||
893 | #define SSI_SIER_CMDDU (0x1 << 17) | ||
894 | #define SSI_SIER_RXT (0x1 << 16) | ||
895 | #define SSI_SIER_RDR1 (0x1 << 15) | ||
896 | #define SSI_SIER_RDR0 (0x1 << 14) | ||
897 | #define SSI_SIER_TDE1 (0x1 << 13) | ||
898 | #define SSI_SIER_TDE0 (0x1 << 12) | ||
899 | #define SSI_SIER_ROE1 (0x1 << 11) | ||
900 | #define SSI_SIER_ROE0 (0x1 << 10) | ||
901 | #define SSI_SIER_TUE1 (0x1 << 9) | ||
902 | #define SSI_SIER_TUE0 (0x1 << 8) | ||
903 | #define SSI_SIER_TFS (0x1 << 7) | ||
904 | #define SSI_SIER_RFS (0x1 << 6) | ||
905 | #define SSI_SIER_TLS (0x1 << 5) | ||
906 | #define SSI_SIER_RLS (0x1 << 4) | ||
907 | #define SSI_SIER_RFF1 (0x1 << 3) | ||
908 | #define SSI_SIER_RFF2 (0x1 << 2) | ||
909 | #define SSI_SIER_TFE1 (0x1 << 1) | ||
910 | #define SSI_SIER_TFE0 (0x1 << 0) | ||
911 | |||
912 | /* SSI STCR */ | ||
913 | #define SSI_STCR_TXBIT0 (0x1 << 9) | ||
914 | #define SSI_STCR_TFEN1 (0x1 << 8) | ||
915 | #define SSI_STCR_TFEN0 (0x1 << 7) | ||
916 | #define SSI_STCR_TFDIR (0x1 << 6) | ||
917 | #define SSI_STCR_TXDIR (0x1 << 5) | ||
918 | #define SSI_STCR_TSHFD (0x1 << 4) | ||
919 | #define SSI_STCR_TSCKP (0x1 << 3) | ||
920 | #define SSI_STCR_TFSI (0x1 << 2) | ||
921 | #define SSI_STCR_TFSL (0x1 << 1) | ||
922 | #define SSI_STCR_TEFS (0x1 << 0) | ||
923 | |||
924 | /* SSI SRCR */ | ||
925 | #define SSI_SRCR_RXEXT (0x1 << 10) | ||
926 | #define SSI_SRCR_RXBIT0 (0x1 << 9) | ||
927 | #define SSI_SRCR_RFEN1 (0x1 << 8) | ||
928 | #define SSI_SRCR_RFEN0 (0x1 << 7) | ||
929 | #define SSI_SRCR_RFDIR (0x1 << 6) | ||
930 | #define SSI_SRCR_RXDIR (0x1 << 5) | ||
931 | #define SSI_SRCR_RSHFD (0x1 << 4) | ||
932 | #define SSI_SRCR_RSCKP (0x1 << 3) | ||
933 | #define SSI_SRCR_RFSI (0x1 << 2) | ||
934 | #define SSI_SRCR_RFSL (0x1 << 1) | ||
935 | #define SSI_SRCR_REFS (0x1 << 0) | ||
936 | |||
937 | /* SSI STCCR/SRCCR */ | ||
938 | #define SSI_STRCCR_DIV2 (0x1 << 18) | ||
939 | #define SSI_STRCCR_PSR (0x1 << 17) | ||
940 | |||
941 | #define SSI_STRCCR_WL (0xf << 13) | ||
942 | #define SSI_STRCCR_WL8 (0x3 << 13) | ||
943 | #define SSI_STRCCR_WL10 (0x4 << 13) | ||
944 | #define SSI_STRCCR_WL12 (0x5 << 13) | ||
945 | #define SSI_STRCCR_WL16 (0x7 << 13) | ||
946 | #define SSI_STRCCR_WL18 (0x8 << 13) | ||
947 | #define SSI_STRCCR_WL20 (0x9 << 13) | ||
948 | #define SSI_STRCCR_WL22 (0xa << 13) | ||
949 | #define SSI_STRCCR_WL24 (0xb << 13) | ||
950 | |||
951 | #define SSI_STRCCR_DC (0x1f << 8) | ||
952 | #define SSI_STRCCR_DCw(x) (((x) << 8) & SSI_STRCCR_DC) | ||
953 | #define SSI_STRCCR_DCr(x) (((x) & SSI_SRCCR_DC) >> 8) | ||
954 | |||
955 | #define SSI_STRCCR_PM (0xf << 0) | ||
956 | #define SSI_STRCCR_PMw(x) (((x) << 0) & SSI_STRCCR_PM) | ||
957 | #define SSI_STRCCR_PMr(x) (((x) & SSI_SRCCR_PM) >> 0) | ||
958 | |||
959 | /* SSI SFCSR */ | ||
960 | #define SSI_SFCSR_RFCNT1 (0xf << 28) | ||
961 | #define SSI_SFCSR_RFCNT1w(x) (((x) << 28) & SSI_SFCSR_RFCNT1) | ||
962 | #define SSI_SFCSR_RFCNT1r(x) (((x) & SSI_SFCSR_RFCNT1) >> 28) | ||
963 | |||
964 | #define SSI_SFCSR_TFCNT1 (0xf << 24) | ||
965 | #define SSI_SFCSR_TFCNT1w(x) (((x) << 24) & SSI_SFCSR_TFCNT1) | ||
966 | #define SSI_SFCSR_TFCNT1r(x) (((x) & SSI_SFCSR_TFCNT1) >> 24) | ||
967 | |||
968 | #define SSI_SFCSR_RFWM1 (0xf << 20) | ||
969 | #define SSI_SFCSR_RFWM1w(x) (((x) << 20) & SSI_SFCSR_RFWM1) | ||
970 | #define SSI_SFCSR_RFWM1r(x) (((x) & SSI_SFCSR_RFWM1) >> 20) | ||
971 | #define SSI_SFCSR_RFWM1_1 (0x1 << 20) | ||
972 | #define SSI_SFCSR_RFWM1_2 (0x2 << 20) | ||
973 | #define SSI_SFCSR_RFWM1_3 (0x3 << 20) | ||
974 | #define SSI_SFCSR_RFWM1_4 (0x4 << 20) | ||
975 | #define SSI_SFCSR_RFWM1_5 (0x5 << 20) | ||
976 | #define SSI_SFCSR_RFWM1_6 (0x6 << 20) | ||
977 | #define SSI_SFCSR_RFWM1_7 (0x7 << 20) | ||
978 | |||
979 | #define SSI_SFCSR_TFWM1 (0xf << 16) | ||
980 | #define SSI_SFCSR_TFWM1w(x) (((x) << 16) & SSI_SFCSR_TFWM1) | ||
981 | #define SSI_SFCSR_TFWM1r(x) (((x) & SSI_SFCSR_TFWM1) >> 16) | ||
982 | |||
983 | #define SSI_SFCSR_RFCNT0 (0xf << 12) | ||
984 | #define SSI_SFCSR_RFCNT0w(x) (((x) << 12) & SSI_SFCSR_RFCNT0) | ||
985 | #define SSI_SFCSR_RFCNT0r(x) (((x) & SSI_SFCSR_RFCNT0) >> 12) | ||
986 | |||
987 | #define SSI_SFCSR_TFCNT0 (0xf << 8) | ||
988 | #define SSI_SFCSR_TFCNT0w(x) (((x) << 8) & SSI_SFCSR_TFCNT0) | ||
989 | #define SSI_SFCSR_TFCNT0r(x) (((x) & SSI_SFCSR_TFCNT0) >> 8) | ||
990 | |||
991 | #define SSI_SFCSR_RFWM0 (0xf << 4) | ||
992 | #define SSI_SFCSR_RFWM0w(x) (((x) << 4) & SSI_SFCSR_RFWM0) | ||
993 | #define SSI_SFCSR_RFWM0r(x) (((x) & SSI_SFCSR_RFWM0) >> 4) | ||
994 | |||
995 | #define SSI_SFCSR_TFWM0 (0xf << 0) | ||
996 | #define SSI_SFCSR_TFWM0w(x) (((x) << 0) & SSI_SFCSR_TFWM0) | ||
997 | #define SSI_SFCSR_TFWM0r(x) (((x) & SSI_SFCSR_TFWM0) >> 0) | ||
998 | |||
999 | /* SACNT */ | ||
1000 | #define SSI_SACNT_FRDIV (0x3f << 5) | ||
1001 | #define SSI_SACNT_FRDIVw(x) (((x) << 5) & SSI_SACNT_FRDIV) | ||
1002 | #define SSI_SACNT_FRDIVr(x) (((x) & SSI_SACNT_FRDIV) >> 5) | ||
1003 | |||
1004 | #define SSI_SACNT_WR (0x1 << 4) | ||
1005 | #define SSI_SACNT_RD (0x1 << 3) | ||
1006 | #define SSI_SACNT_TIF (0x1 << 2) | ||
1007 | #define SSI_SACNT_FV (0x1 << 1) | ||
1008 | #define SSI_SACNT_AC97EN (0x1 << 0) | ||
1009 | |||
720 | /* RTC */ | 1010 | /* RTC */ |
721 | #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) | 1011 | #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) |
722 | #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) | 1012 | #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) |
@@ -874,6 +1164,123 @@ | |||
874 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) | 1164 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) |
875 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | 1165 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) |
876 | 1166 | ||
1167 | /* CCMR */ | ||
1168 | #define CCMR_L2PG (0x1 << 29) | ||
1169 | #define CCMR_VSTBY (0x1 << 28) | ||
1170 | #define CCMR_WBEN (0x1 << 27) | ||
1171 | #define CCMR_FPMF (0x1 << 26) | ||
1172 | #define CCMR_CSCS (0x1 << 25) | ||
1173 | #define CCMR_PERCS (0x1 << 24) | ||
1174 | |||
1175 | #define CCMR_SSI2S (0x3 << 21) | ||
1176 | #define CCMR_SSI2S_MCU_CLK (0x0 << 21) | ||
1177 | #define CCMR_SSI2S_USB_CLK (0x1 << 21) | ||
1178 | #define CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */ | ||
1179 | |||
1180 | #define CCMR_SSI1S (0x3 << 18) | ||
1181 | #define CCMR_SSI1S_MCU_CLK (0x0 << 18) | ||
1182 | #define CCMR_SSI1S_USB_CLK (0x1 << 18) | ||
1183 | #define CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */ | ||
1184 | |||
1185 | #define CCMR_RAMW (0x3 << 16) | ||
1186 | #define CCMR_RAMW_0ARM_0ALTMS (0x0 << 16) | ||
1187 | #define CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */ | ||
1188 | #define CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */ | ||
1189 | #define CCMR_RAMW_1ARM_1ALTMS (0x3 << 16) | ||
1190 | |||
1191 | #define CCMR_LPM (0x3 << 14) | ||
1192 | #define CCMR_LPM_WAIT_MODE (0x0 << 14) | ||
1193 | #define CCMR_LPM_DOZE_MODE (0x1 << 14) | ||
1194 | #define CCMR_LPM_SRM (0x2 << 14) /* State retention mode */ | ||
1195 | #define CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */ | ||
1196 | |||
1197 | #define CCMR_FIRS (0x3 << 11) | ||
1198 | #define CCMR_FIRS_MCU_CLK (0x0 << 11) | ||
1199 | #define CCMR_FIRS_USB_CLK (0x1 << 11) | ||
1200 | #define CCMR_FIRS_SERIAL_CLK (0x2 << 11) | ||
1201 | |||
1202 | #define CCMR_WAMO (0x1 << 10) | ||
1203 | #define CCMR_UPE (0x1 << 9) | ||
1204 | #define CCMR_SPE (0x1 << 8) | ||
1205 | #define CCMR_MDS (0x1 << 7) | ||
1206 | |||
1207 | #define CCMR_ROMW (0x3 << 5) | ||
1208 | #define CCMR_ROMW_0ARM_0ALTMS (0x0 << 5) | ||
1209 | #define CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */ | ||
1210 | #define CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */ | ||
1211 | #define CCMR_ROMW_1ARM_1ALTMS (0x3 << 5) | ||
1212 | |||
1213 | #define CCMR_SBYCS (0x1 << 4) | ||
1214 | #define CCMR_MPE (0x1 << 3) | ||
1215 | |||
1216 | #define CCMR_PRCS (0x3 << 1) | ||
1217 | #define CCMR_PRCS_FPM (0x1 << 1) | ||
1218 | #define CCMR_PRCS_CKIH (0x2 << 1) | ||
1219 | |||
1220 | #define CCMR_FPME (0x1 << 0) | ||
1221 | |||
1222 | /* PDR0 */ | ||
1223 | #define PDR0_CSI_PODF (0x1ff << 23) | ||
1224 | #define PDR0_CSI_PODFw(x) (((x) << 23) & PDR0_CSI_PODF) | ||
1225 | #define PDR0_CSI_PODFr(x) (((x) & PDR0_CSI_PODF) >> 23) | ||
1226 | |||
1227 | #define PDR0_PER_PODF (0x1f << 16) | ||
1228 | #define PDR0_PER_PODFw(x) (((x) << 16) & PDR0_PER_PODF) | ||
1229 | #define PDR0_PER_PODFr(x) (((x) & PDR0_PER_PODF) >> 16) | ||
1230 | |||
1231 | #define PDR0_HSP_PODF (0x7 << 11) | ||
1232 | #define PDR0_HSP_PODFw(x) (((x) << 11) & PDR0_HSP_PODF) | ||
1233 | #define PDR0_HSP_PODFr(x) (((x) & PDR0_HSP_PODF) >> 11) | ||
1234 | |||
1235 | #define PDR0_NFC_PODF (0x7 << 8) | ||
1236 | #define PDR0_NFC_PODFw(x) (((x) << 8) & PDR0_NFC_PODF) | ||
1237 | #define PDR0_NFC_PODFr(x) (((x) & PDR0_NFC_PODF) >> 8) | ||
1238 | |||
1239 | #define PDR0_IPG_PODF (0x3 << 6) | ||
1240 | #define PDR0_IPG_PODFw(x) (((x) << 6) & PDR0_IPG_PODF) | ||
1241 | #define PDR0_IPG_PODFr(x) (((x) & PDR0_IPG_PODF) >> 6) | ||
1242 | |||
1243 | #define PDR0_MAX_PODF (0x7 << 3) | ||
1244 | #define PDR0_MAX_PODFw(x) (((x) << 3) & PDR0_MAX_PODF) | ||
1245 | #define PDR0_MAX_PODFr(x) (((x) & PDR0_MAX_PODF) >> 3) | ||
1246 | |||
1247 | #define PDR0_MCU_PODF (0x7 << 0) | ||
1248 | #define PDR0_MCU_PODFw(x) (((x) << 0) & PDR0_MCU_PODF) | ||
1249 | #define PDR0_MCU_PODFr(x) (((x) & PDR0_MCU_PODF) >> 0) | ||
1250 | |||
1251 | /* PDR1 */ | ||
1252 | #define PDR1_USB_PRDF (0x3 << 30) | ||
1253 | #define PDR1_USB_PRDFw(x) (((x) << 30) & PDR1_USB_PRDF) | ||
1254 | #define PDR1_USB_PRDFr(x) (((x) & PDR1_USB_PRDF) >> 30) | ||
1255 | |||
1256 | #define PDR1_USB_PODF (0x7 << 27) | ||
1257 | #define PDR1_USB_PODFw(x) (((x) << 27) & PDR1_USB_PODF) | ||
1258 | #define PDR1_USB_PODFr(x) (((x) & PDR1_USB_PODF) >> 27) | ||
1259 | |||
1260 | #define PDR1_FIRI_PRE_PODF (0x7 << 24) | ||
1261 | #define PDR1_FIRI_PRE_PODFw(x) (((x) << 24) & PDR1_FIRI_PRE_PODF) | ||
1262 | #define PDR1_FIRI_PRE_PODFr(x) (((x) & PDR1_FIRI_PRE_PODF) >> 24) | ||
1263 | |||
1264 | #define PDR1_FIRI_PODF (0x3f << 18) | ||
1265 | #define PDR1_FIRI_PODFw(x) (((x) << 18) & PDR1_FIRI_PODF) | ||
1266 | #define PDR1_FIRI_PODFr(x) (((x) & PDR1_FIRI_PODF) >> 18) | ||
1267 | |||
1268 | #define PDR1_SSI2_PRE_PODF (0x7 << 15) | ||
1269 | #define PDR1_SSI2_PRE_PODFw(x) (((x) << 15) & PDR1_SSI2_PRE_PODF) | ||
1270 | #define PDR1_SSI2_PRE_PODFr(x) (((x) & PDR1_SSI2_PRE_PODF) >> 15) | ||
1271 | |||
1272 | #define PDR1_SSI2_PODF (0x3f << 9) | ||
1273 | #define PDR1_SSI2_PODFw(x) (((x) << 9) & PDR1_SSI2_PODF) | ||
1274 | #define PDR1_SSI2_PODFr(x) (((x) & PDR1_SSI2_PODF) >> 9) | ||
1275 | |||
1276 | #define PDR1_SSI1_PRE_PODF (0x7 << 6) | ||
1277 | #define PDR1_SSI1_PRE_PODFw(x) (((x) << 6) & PDR1_SSI1_PRE_PODF) | ||
1278 | #define PDR1_SSI1_PRE_PODFr(x) (((x) & PDR1_SSI1_PRE_PODF) >> 6) | ||
1279 | |||
1280 | #define PDR1_SSI1_PODF (0x3f << 0) | ||
1281 | #define PDR1_SSI1_PODFw(x) (((x) << 0) & PDR1_SSI1_PODF) | ||
1282 | #define PDR1_SSI1_PODFr(x) (((x) & PDR1_SSI1_PODF) >> 0) | ||
1283 | |||
877 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) | 1284 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) |
878 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) | 1285 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) |
879 | #define CGR0_GPT(cg) ((cg) << 2*2) | 1286 | #define CGR0_GPT(cg) ((cg) << 2*2) |
diff --git a/firmware/export/wm8978.h b/firmware/export/wm8978.h index aca1250665..33a7c9d4f1 100644 --- a/firmware/export/wm8978.h +++ b/firmware/export/wm8978.h | |||
@@ -21,551 +21,510 @@ | |||
21 | #ifndef _WM8978_H | 21 | #ifndef _WM8978_H |
22 | #define _WM8978_H | 22 | #define _WM8978_H |
23 | 23 | ||
24 | #define VOLUME_MIN -570 | 24 | #define VOLUME_MIN -900 |
25 | #define VOLUME_MAX 60 | 25 | #define VOLUME_MAX 60 |
26 | 26 | ||
27 | #define WM8978_I2C_ADDR 0x34 | 27 | int tenthdb2master(int db); |
28 | void audiohw_set_headphone_vol(int vol_l, int vol_r); | ||
29 | |||
30 | #define WMC_I2C_ADDR 0x34 | ||
28 | 31 | ||
29 | /* Registers */ | 32 | /* Registers */ |
30 | #define WM8978_SOFTWARE_RESET 0x00 | 33 | #define WMC_SOFTWARE_RESET 0x00 |
31 | #define WM8978_POWER_MANAGEMENT1 0x01 | 34 | #define WMC_POWER_MANAGEMENT1 0x01 |
32 | #define WM8978_POWER_MANAGEMENT2 0x02 | 35 | #define WMC_POWER_MANAGEMENT2 0x02 |
33 | #define WM8978_POWER_MANAGEMENT3 0x03 | 36 | #define WMC_POWER_MANAGEMENT3 0x03 |
34 | #define WM8978_AUDIO_INTERFACE 0x04 | 37 | #define WMC_AUDIO_INTERFACE 0x04 |
35 | #define WM8978_COMPANDING_CTRL 0x05 | 38 | #define WMC_COMPANDING_CTRL 0x05 |
36 | #define WM8978_CLOCK_GEN_CTRL 0x06 | 39 | #define WMC_CLOCK_GEN_CTRL 0x06 |
37 | #define WM8978_ADDITIONAL_CTRL 0x07 | 40 | #define WMC_ADDITIONAL_CTRL 0x07 |
38 | #define WM8978_GPIO 0x08 | 41 | #define WMC_GPIO 0x08 |
39 | #define WM8978_JACK_DETECT_CONTROL1 0x09 | 42 | #define WMC_JACK_DETECT_CONTROL1 0x09 |
40 | #define WM8978_DAC_CONTROL 0x0a | 43 | #define WMC_DAC_CONTROL 0x0a |
41 | #define WM8978_LEFT_DAC_DIGITAL_VOL 0x0b | 44 | #define WMC_LEFT_DAC_DIGITAL_VOL 0x0b |
42 | #define WM8978_RIGHT_DAC_DIGITAL_VOL 0x0c | 45 | #define WMC_RIGHT_DAC_DIGITAL_VOL 0x0c |
43 | #define WM8978_JACK_DETECT_CONTROL2 0x0d | 46 | #define WMC_JACK_DETECT_CONTROL2 0x0d |
44 | #define WM8978_ADC_CONTROL 0x0e | 47 | #define WMC_ADC_CONTROL 0x0e |
45 | #define WM8978_LEFT_ADC_DIGITAL_VOL 0x0f | 48 | #define WMC_LEFT_ADC_DIGITAL_VOL 0x0f |
46 | #define WM8978_RIGHT_ADC_DITIGAL_VOL 0x10 | 49 | #define WMC_RIGHT_ADC_DIGITAL_VOL 0x10 |
47 | #define WM8978_EQ1_LOW_SHELF 0x12 | 50 | #define WMC_EQ1_LOW_SHELF 0x12 |
48 | #define WM8978_EQ2_PEAK1 0x13 | 51 | #define WMC_EQ2_PEAK1 0x13 |
49 | #define WM8978_EQ3_PEAK2 0x14 | 52 | #define WMC_EQ3_PEAK2 0x14 |
50 | #define WM8978_EQ4_PEAK3 0x15 | 53 | #define WMC_EQ4_PEAK3 0x15 |
51 | #define WM8978_EQ5_HIGH_SHELF 0x16 | 54 | #define WMC_EQ5_HIGH_SHELF 0x16 |
52 | #define WM8978_DAC_LIMITER1 0x18 | 55 | #define WMC_DAC_LIMITER1 0x18 |
53 | #define WM8978_DAC_LIMITER2 0x19 | 56 | #define WMC_DAC_LIMITER2 0x19 |
54 | #define WM8978_NOTCH_FILTER1 0x1b | 57 | #define WMC_NOTCH_FILTER1 0x1b |
55 | #define WM8978_NOTCH_FILTER2 0x1c | 58 | #define WMC_NOTCH_FILTER2 0x1c |
56 | #define WM8978_NOTCH_FILTER3 0x1d | 59 | #define WMC_NOTCH_FILTER3 0x1d |
57 | #define WM8978_NOTCH_FILTER4 0x1e | 60 | #define WMC_NOTCH_FILTER4 0x1e |
58 | #define WM8978_ALC_CONTROL1 0x20 | 61 | #define WMC_ALC_CONTROL1 0x20 |
59 | #define WM8978_ALC_CONTROL2 0x21 | 62 | #define WMC_ALC_CONTROL2 0x21 |
60 | #define WM8978_ALC_CONTROL3 0x22 | 63 | #define WMC_ALC_CONTROL3 0x22 |
61 | #define WM8978_NOISE_GATE 0x23 | 64 | #define WMC_NOISE_GATE 0x23 |
62 | #define WM8978_PLL_N 0x24 | 65 | #define WMC_PLL_N 0x24 |
63 | #define WM8978_PLL_K1 0x25 | 66 | #define WMC_PLL_K1 0x25 |
64 | #define WM8978_PLL_K2 0x26 | 67 | #define WMC_PLL_K2 0x26 |
65 | #define WM8978_PLL_K3 0x27 | 68 | #define WMC_PLL_K3 0x27 |
66 | #define WM8978_3D_CONTROL 0x29 | 69 | #define WMC_3D_CONTROL 0x29 |
67 | #define WM8978_BEEP_CONTROL 0x2b | 70 | #define WMC_BEEP_CONTROL 0x2b |
68 | #define WM8978_INPUT_CTRL 0x2c | 71 | #define WMC_INPUT_CTRL 0x2c |
69 | #define WM8978_LEFT_INP_PGA_GAIN_CTRL 0x2d | 72 | #define WMC_LEFT_INP_PGA_GAIN_CTRL 0x2d |
70 | #define WM8978_RIGHT_INP_PGA_GAIN_CTRL 0x2e | 73 | #define WMC_RIGHT_INP_PGA_GAIN_CTRL 0x2e |
71 | #define WM8978_LEFT_ADC_BOOST_CTRL 0x2f | 74 | #define WMC_LEFT_ADC_BOOST_CTRL 0x2f |
72 | #define WM8978_RIGHT_ADC_BOOST_CTRL 0x30 | 75 | #define WMC_RIGHT_ADC_BOOST_CTRL 0x30 |
73 | #define WM8978_OUTPUT_CTRL 0x31 | 76 | #define WMC_OUTPUT_CTRL 0x31 |
74 | #define WM8978_LEFT_MIXER_CTRL 0x32 | 77 | #define WMC_LEFT_MIXER_CTRL 0x32 |
75 | #define WM8978_RIGHT_MIXER_CTRL 0x33 | 78 | #define WMC_RIGHT_MIXER_CTRL 0x33 |
76 | #define WM8978_LOUT1_HP_VOLUME_CTRL 0x34 | 79 | #define WMC_LOUT1_HP_VOLUME_CTRL 0x34 |
77 | #define WM8978_ROUT1_HP_VOLUME_CTRL 0x35 | 80 | #define WMC_ROUT1_HP_VOLUME_CTRL 0x35 |
78 | #define WM8978_LOUT2_SPK_VOLUME_CTRL 0x36 | 81 | #define WMC_LOUT2_SPK_VOLUME_CTRL 0x36 |
79 | #define WM8978_ROUT2_SPK_VOLUME_CTRL 0x37 | 82 | #define WMC_ROUT2_SPK_VOLUME_CTRL 0x37 |
80 | #define WM8978_OUT3_MIXER_CTRL 0x38 | 83 | #define WMC_OUT3_MIXER_CTRL 0x38 |
81 | #define WM8978_OUT4_MONO_MIXER_CTRL 0x39 | 84 | #define WMC_OUT4_MONO_MIXER_CTRL 0x39 |
85 | #define WMC_NUM_REGISTERS 0x3a | ||
82 | 86 | ||
83 | /* Register bitmasks */ | 87 | /* Register bitmasks */ |
84 | 88 | ||
85 | /* WM8978_SOFTWARE_RESET (0x00) */ | 89 | /* Volume update bit for volume registers */ |
86 | #define WM8978_RESET | 90 | #define WMC_VU (1 << 8) |
87 | /* Write any value */ | ||
88 | 91 | ||
89 | /* WM8978_POWER_MANAGEMENT1 (0x01) */ | 92 | /* Zero-crossing bit for volume registers */ |
90 | #define WM8978_BUFDCOMPEN (1 << 8) | 93 | #define WMC_ZC (1 << 7) |
91 | #define WM8978_OUT4MIXEN (1 << 7) | 94 | |
92 | #define WM8978_OUT3MIXEN (1 << 6) | 95 | /* Mute bit for volume registers */ |
93 | #define WM8978_PLLEN (1 << 5) | 96 | #define WMC_MUTE (1 << 6) |
94 | #define WM8978_MICBEN (1 << 4) | 97 | |
95 | #define WM8978_BIASEN (1 << 3) | 98 | /* Volume masks and macros for digital volumes */ |
96 | #define WM8978_BUFIOEN (1 << 2) | 99 | #define WMC_DVOL 0xff |
97 | #define WM8978_VMIDSEL (3 << 0) | 100 | #define WMC_DVOLr(x) ((x) & WMC_DVOL) |
98 | #define WM8978_VMIDSEL_OFF (0 << 0) | 101 | #define WMC_DVOLw(x) ((x) & WMC_DVOL) |
99 | #define WM8978_VMIDSEL_75K (1 << 0) | 102 | |
100 | #define WM8978_VMIDSEL_300K (2 << 0) | 103 | /* Volums masks and macros for analogue volumes */ |
101 | #define WM8978_VMIDSEL_5K (3 << 0) | 104 | #define WMC_AVOL 0x3f |
102 | 105 | #define WMC_AVOLr(x) ((x) & WMC_AVOLUME_MASK) | |
103 | /* WM8978_POWER_MANAGEMENT2 (0x02) */ | 106 | #define WMC_AVOLw(x) ((x) & WMC_AVOLUME_MASK) |
104 | #define WM8978_ROUT1EN (1 << 8) | 107 | |
105 | #define WM8978_LOUT1EN (1 << 7) | 108 | /* WMC_SOFTWARE_RESET (0x00) */ |
106 | #define WM8978_SLEEP (1 << 6) | 109 | #define WMC_RESET |
107 | #define WM8978_BOOSTENR (1 << 5) | 110 | /* Write any value */ |
108 | #define WM8978_BOOSTENL (1 << 4) | ||
109 | #define WM8978_INPPGAENR (1 << 3) | ||
110 | #define WM8978_INPPGAENL (1 << 2) | ||
111 | #define WM8978_ADCENR (1 << 1) | ||
112 | #define WM8978_ADCENL (1 << 0) | ||
113 | |||
114 | /* WM8978_POWER_MANAGEMENT3 (0x03) */ | ||
115 | #define WM8978_OUT4EN (1 << 8) | ||
116 | #define WM8978_OUT3EN (1 << 7) | ||
117 | #define WM8978_LOUT2EN (1 << 6) | ||
118 | #define WM8978_ROUT2EN (1 << 5) | ||
119 | #define WM8978_RMIXEN (1 << 3) | ||
120 | #define WM8978_LMIXEN (1 << 2) | ||
121 | #define WM8978_DACENR (1 << 1) | ||
122 | #define WM8978_DACENL (1 << 0) | ||
123 | |||
124 | /* WM8978_AUDIO_INTERFACE (0x04) */ | ||
125 | #define WM8978_BCP (1 << 8) | ||
126 | #define WM8978_LRP (1 << 7) | ||
127 | #define WM8978_WL (3 << 5) | ||
128 | #define WM8978_WL_16 (0 << 5) | ||
129 | #define WM8978_WL_20 (1 << 5) | ||
130 | #define WM8978_WL_24 (2 << 5) | ||
131 | #define WM8978_WL_32 (3 << 5) | ||
132 | #define WM8978_FMT (3 << 3) | ||
133 | #define WM8978_FMT_RJUST (0 << 3) | ||
134 | #define WM8978_FMT_LJUST (1 << 3) | ||
135 | #define WM8978_FMT_I2S (2 << 3) | ||
136 | #define WM8978_FMT_DSP_PCM (3 << 3) | ||
137 | #define WM8978_DACLRSWAP (1 << 2) | ||
138 | #define WM8978_ADCLRSWAP (1 << 1) | ||
139 | #define WM8978_MONO (1 << 0) | ||
140 | |||
141 | /* WM8978_COMPANDING_CTRL (0x05) */ | ||
142 | #define WM8978_WL8 (1 << 5) | ||
143 | #define WM8978_DAC_COMP (3 << 3) | ||
144 | #define WM8978_DAC_COMP_OFF (0 << 3) | ||
145 | #define WM8978_DAC_COMP_U_LAW (2 << 3) | ||
146 | #define WM8978_DAC_COMP_A_LAW (3 << 3) | ||
147 | #define WM8978_ADC_COMP (3 << 1) | ||
148 | #define WM8978_ADC_COMP_OFF (0 << 1) | ||
149 | #define WM8978_ADC_COMP_U_LAW (2 << 1) | ||
150 | #define WM8978_ADC_COMP_A_LAW (3 << 1) | ||
151 | #define WM8978_LOOPBACK (1 << 0) | ||
152 | |||
153 | /* WM8978_CLOCK_GEN_CTRL (0x06) */ | ||
154 | #define WM8978_CLKSEL (1 << 8) | ||
155 | #define WM8978_MCLKDIV (7 << 5) | ||
156 | #define WM8978_MCLKDIV_1 (0 << 5) | ||
157 | #define WM8978_MCLKDIV_1_5 (1 << 5) | ||
158 | #define WM8978_MCLKDIV_2 (2 << 5) | ||
159 | #define WM8978_MCLKDIV_3 (3 << 5) | ||
160 | #define WM8978_MCLKDIV_4 (4 << 5) | ||
161 | #define WM8978_MCLKDIV_6 (5 << 5) | ||
162 | #define WM8978_MCLKDIV_8 (6 << 5) | ||
163 | #define WM8978_MCLKDIV_12 (7 << 5) | ||
164 | #define WM8978_BCLKDIV (7 << 2) | ||
165 | #define WM8978_BCLKDIV_1 (0 << 2) | ||
166 | #define WM8978_BCLKDIV_2 (1 << 2) | ||
167 | #define WM8978_BCLKDIV_4 (2 << 2) | ||
168 | #define WM8978_BCLKDIV_8 (3 << 2) | ||
169 | #define WM8978_BCLKDIV_16 (4 << 2) | ||
170 | #define WM8978_BCLKDIV_32 (5 << 2) | ||
171 | #define WM8978_MS (1 << 0) | ||
172 | |||
173 | /* WM8978_ADDITIONAL_CTRL (0x07) */ | ||
174 | #define WM8978_SR (7 << 1) | ||
175 | #define WM8978_SLOWCLKEN (1 << 0) | ||
176 | |||
177 | /* WM8978_GPIO (0x08) */ | ||
178 | #define WM8978_OPCLKDIV (3 << 4) | ||
179 | #define WM8978_OPCLKDIV_1 (0 << 4) | ||
180 | #define WM8978_OPCLKDIV_2 (1 << 4) | ||
181 | #define WM8978_OPCLKDIV_3 (2 << 4) | ||
182 | #define WM8978_OPCLKDIV_4 (3 << 4) | ||
183 | #define WM8978_GPIO1POL (1 << 3) | ||
184 | #define WM8978_GPIO1SEL (7 << 0) | ||
185 | #define WM8978_GPIO1SEL_TEMP_OK (2 << 0) | ||
186 | #define WM8978_GPIO1SEL_AMUTE_ACTIVE (3 << 0) | ||
187 | #define WM8978_GPIO1SEL_PLL_CLK_OP (4 << 0) | ||
188 | #define WM8978_GPIO1SEL_PLL_LOCK (5 << 0) | ||
189 | #define WM8978_GPIO1SEL_LOGIC_1 (6 << 0) | ||
190 | #define WM8978_GPIO1SEL_LOGIC_0 (7 << 0) | ||
191 | |||
192 | /* WM8978_JACK_DETECT_CONTROL1 (0x09) */ | ||
193 | #define WM8978_JD_VMID (3 << 7) | ||
194 | #define WM8978_JD_VMID_EN_0 (1 << 7) | ||
195 | #define WM8978_JD_VMID_EN_1 (2 << 7) | ||
196 | #define WM8978_JD_EN (1 << 6) | ||
197 | #define WM8978_JD_SEL (3 << 4) | ||
198 | #define WM8978_JD_SEL_GPIO1 (0 << 4) | ||
199 | #define WM8978_JD_SEL_GPIO2 (1 << 4) | ||
200 | #define WM8978_JD_SEL_GPIO3 (2 << 4) | ||
201 | |||
202 | /* WM8978_DAC_CONTROL (0x0a) */ | ||
203 | #define WM8978_SOFT_MUTE (1 << 6) | ||
204 | #define WM8978_DACOSR_128 (1 << 3) | ||
205 | #define WM8978_AMUTE (1 << 2) | ||
206 | #define WM8978_DACPOLR (1 << 1) | ||
207 | #define WM8978_DACPOLL (1 << 0) | ||
208 | |||
209 | /* WM8978_LEFT_DAC_DIGITAL_VOL (0x0b) */ | ||
210 | #define WM8978_DACVUL (1 << 8) | ||
211 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ | ||
212 | #define WM8978_DACVOLL (0xff << 0) | ||
213 | #define WM8978_DACVOLLr(x) ((x) & WM8978_DACVOLL) | ||
214 | #define WM8978_DACVOLLw(x) ((x) & WM8978_DACVOLL) | ||
215 | 111 | ||
216 | /* WM8978_RIGHT_DAC_DIGITAL_VOL (0x0c) */ | 112 | /* WMC_POWER_MANAGEMENT1 (0x01) */ |
217 | #define WM8978_DACVUR (1 << 8) | 113 | #define WMC_BUFDCOMPEN (1 << 8) |
114 | #define WMC_OUT4MIXEN (1 << 7) | ||
115 | #define WMC_OUT3MIXEN (1 << 6) | ||
116 | #define WMC_PLLEN (1 << 5) | ||
117 | #define WMC_MICBEN (1 << 4) | ||
118 | #define WMC_BIASEN (1 << 3) | ||
119 | #define WMC_BUFIOEN (1 << 2) | ||
120 | #define WMC_VMIDSEL (3 << 0) | ||
121 | #define WMC_VMIDSEL_OFF (0 << 0) | ||
122 | #define WMC_VMIDSEL_75K (1 << 0) | ||
123 | #define WMC_VMIDSEL_300K (2 << 0) | ||
124 | #define WMC_VMIDSEL_5K (3 << 0) | ||
125 | |||
126 | /* WMC_POWER_MANAGEMENT2 (0x02) */ | ||
127 | #define WMC_ROUT1EN (1 << 8) | ||
128 | #define WMC_LOUT1EN (1 << 7) | ||
129 | #define WMC_SLEEP (1 << 6) | ||
130 | #define WMC_BOOSTENR (1 << 5) | ||
131 | #define WMC_BOOSTENL (1 << 4) | ||
132 | #define WMC_INPPGAENR (1 << 3) | ||
133 | #define WMC_INPPGAENL (1 << 2) | ||
134 | #define WMC_ADCENR (1 << 1) | ||
135 | #define WMC_ADCENL (1 << 0) | ||
136 | |||
137 | /* WMC_POWER_MANAGEMENT3 (0x03) */ | ||
138 | #define WMC_OUT4EN (1 << 8) | ||
139 | #define WMC_OUT3EN (1 << 7) | ||
140 | #define WMC_LOUT2EN (1 << 6) | ||
141 | #define WMC_ROUT2EN (1 << 5) | ||
142 | #define WMC_RMIXEN (1 << 3) | ||
143 | #define WMC_LMIXEN (1 << 2) | ||
144 | #define WMC_DACENR (1 << 1) | ||
145 | #define WMC_DACENL (1 << 0) | ||
146 | |||
147 | /* WMC_AUDIO_INTERFACE (0x04) */ | ||
148 | #define WMC_BCP (1 << 8) | ||
149 | #define WMC_LRP (1 << 7) | ||
150 | #define WMC_WL (3 << 5) | ||
151 | #define WMC_WL_16 (0 << 5) | ||
152 | #define WMC_WL_20 (1 << 5) | ||
153 | #define WMC_WL_24 (2 << 5) | ||
154 | #define WMC_WL_32 (3 << 5) | ||
155 | #define WMC_FMT (3 << 3) | ||
156 | #define WMC_FMT_RJUST (0 << 3) | ||
157 | #define WMC_FMT_LJUST (1 << 3) | ||
158 | #define WMC_FMT_I2S (2 << 3) | ||
159 | #define WMC_FMT_DSP_PCM (3 << 3) | ||
160 | #define WMC_DACLRSWAP (1 << 2) | ||
161 | #define WMC_ADCLRSWAP (1 << 1) | ||
162 | #define WMC_MONO (1 << 0) | ||
163 | |||
164 | /* WMC_COMPANDING_CTRL (0x05) */ | ||
165 | #define WMC_WL8 (1 << 5) | ||
166 | #define WMC_DAC_COMP (3 << 3) | ||
167 | #define WMC_DAC_COMP_OFF (0 << 3) | ||
168 | #define WMC_DAC_COMP_U_LAW (2 << 3) | ||
169 | #define WMC_DAC_COMP_A_LAW (3 << 3) | ||
170 | #define WMC_ADC_COMP (3 << 1) | ||
171 | #define WMC_ADC_COMP_OFF (0 << 1) | ||
172 | #define WMC_ADC_COMP_U_LAW (2 << 1) | ||
173 | #define WMC_ADC_COMP_A_LAW (3 << 1) | ||
174 | #define WMC_LOOPBACK (1 << 0) | ||
175 | |||
176 | /* WMC_CLOCK_GEN_CTRL (0x06) */ | ||
177 | #define WMC_CLKSEL (1 << 8) | ||
178 | #define WMC_MCLKDIV (7 << 5) | ||
179 | #define WMC_MCLKDIV_1 (0 << 5) | ||
180 | #define WMC_MCLKDIV_1_5 (1 << 5) | ||
181 | #define WMC_MCLKDIV_2 (2 << 5) | ||
182 | #define WMC_MCLKDIV_3 (3 << 5) | ||
183 | #define WMC_MCLKDIV_4 (4 << 5) | ||
184 | #define WMC_MCLKDIV_6 (5 << 5) | ||
185 | #define WMC_MCLKDIV_8 (6 << 5) | ||
186 | #define WMC_MCLKDIV_12 (7 << 5) | ||
187 | #define WMC_BCLKDIV (7 << 2) | ||
188 | #define WMC_BCLKDIV_1 (0 << 2) | ||
189 | #define WMC_BCLKDIV_2 (1 << 2) | ||
190 | #define WMC_BCLKDIV_4 (2 << 2) | ||
191 | #define WMC_BCLKDIV_8 (3 << 2) | ||
192 | #define WMC_BCLKDIV_16 (4 << 2) | ||
193 | #define WMC_BCLKDIV_32 (5 << 2) | ||
194 | #define WMC_MS (1 << 0) | ||
195 | |||
196 | /* WMC_ADDITIONAL_CTRL (0x07) */ | ||
197 | /* This configure the digital filter coefficients - pick the closest | ||
198 | * to what's really being used (greater than or equal). */ | ||
199 | #define WMC_SR (7 << 1) | ||
200 | #define WMC_SR_48KHZ (0 << 1) | ||
201 | #define WMC_SR_32KHZ (1 << 1) | ||
202 | #define WMC_SR_24KHZ (2 << 1) | ||
203 | #define WMC_SR_16KHZ (3 << 1) | ||
204 | #define WMC_SR_12KHZ (4 << 1) | ||
205 | #define WMC_SR_8KHZ (5 << 1) | ||
206 | /* 110-111=reserved */ | ||
207 | #define WMC_SLOWCLKEN (1 << 0) | ||
208 | |||
209 | /* WMC_GPIO (0x08) */ | ||
210 | #define WMC_OPCLKDIV (3 << 4) | ||
211 | #define WMC_OPCLKDIV_1 (0 << 4) | ||
212 | #define WMC_OPCLKDIV_2 (1 << 4) | ||
213 | #define WMC_OPCLKDIV_3 (2 << 4) | ||
214 | #define WMC_OPCLKDIV_4 (3 << 4) | ||
215 | #define WMC_GPIO1POL (1 << 3) | ||
216 | #define WMC_GPIO1SEL (7 << 0) | ||
217 | #define WMC_GPIO1SEL_TEMP_OK (2 << 0) | ||
218 | #define WMC_GPIO1SEL_AMUTE_ACTIVE (3 << 0) | ||
219 | #define WMC_GPIO1SEL_PLL_CLK_OP (4 << 0) | ||
220 | #define WMC_GPIO1SEL_PLL_LOCK (5 << 0) | ||
221 | #define WMC_GPIO1SEL_LOGIC_1 (6 << 0) | ||
222 | #define WMC_GPIO1SEL_LOGIC_0 (7 << 0) | ||
223 | |||
224 | /* WMC_JACK_DETECT_CONTROL1 (0x09) */ | ||
225 | #define WMC_JD_VMID (3 << 7) | ||
226 | #define WMC_JD_VMID_EN_0 (1 << 7) | ||
227 | #define WMC_JD_VMID_EN_1 (2 << 7) | ||
228 | #define WMC_JD_EN (1 << 6) | ||
229 | #define WMC_JD_SEL (3 << 4) | ||
230 | #define WMC_JD_SEL_GPIO1 (0 << 4) | ||
231 | #define WMC_JD_SEL_GPIO2 (1 << 4) | ||
232 | #define WMC_JD_SEL_GPIO3 (2 << 4) | ||
233 | |||
234 | /* WMC_DAC_CONTROL (0x0a) */ | ||
235 | #define WMC_SOFT_MUTE (1 << 6) | ||
236 | #define WMC_DACOSR_128 (1 << 3) | ||
237 | #define WMC_AMUTE (1 << 2) | ||
238 | #define WMC_DACPOLR (1 << 1) | ||
239 | #define WMC_DACPOLL (1 << 0) | ||
240 | |||
241 | /* WMC_LEFT_DAC_DIGITAL_VOL (0x0b) */ | ||
242 | /* WMC_RIGHT_DAC_DIGITAL_VOL (0x0c) */ | ||
218 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ | 243 | /* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */ |
219 | #define WM8978_DACVOLR (0xff << 0) | 244 | /* Use WMC_DVOL* macros */ |
220 | #define WM8978_DACVOLRr(x) ((x) & WM8978_DACVOLR) | 245 | |
221 | #define WM8978_DACVOLRw(x) ((x) & WM8978_DACVOLR) | 246 | /* WMC_JACK_DETECT_CONTROL2 (0x0d) */ |
222 | 247 | #define WMC_JD_EN1 (0xf << 4) | |
223 | /* WM8978_JACK_DETECT_CONTROL2 (0x0d) */ | 248 | #define WMC_OUT1_EN1 (1 << 4) |
224 | #define WM8978_JD_EN1 (0xf << 4) | 249 | #define WMC_OUT2_EN1 (2 << 4) |
225 | #define WM8978_OUT1_EN1 (1 << 4) | 250 | #define WMC_OUT3_EN1 (4 << 4) |
226 | #define WM8978_OUT2_EN1 (2 << 4) | 251 | #define WMC_OUT4_EN1 (8 << 4) |
227 | #define WM8978_OUT3_EN1 (4 << 4) | 252 | #define WMC_JD_EN0 (0xf << 0) |
228 | #define WM8978_OUT4_EN1 (8 << 4) | 253 | #define WMC_OUT1_EN0 (1 << 0) |
229 | #define WM8978_JD_EN0 (0xf << 0) | 254 | #define WMC_OUT2_EN0 (2 << 0) |
230 | #define WM8978_OUT1_EN0 (1 << 0) | 255 | #define WMC_OUT3_EN0 (4 << 0) |
231 | #define WM8978_OUT2_EN0 (2 << 0) | 256 | #define WMC_OUT4_EN0 (8 << 0) |
232 | #define WM8978_OUT3_EN0 (4 << 0) | 257 | |
233 | #define WM8978_OUT4_EN0 (8 << 0) | 258 | /* WMC_ADC_CONTROL (0x0e) */ |
234 | 259 | #define WMC_HPFEN (1 << 8) | |
235 | /* WM8978_ADC_CONTROL (0x0e) */ | 260 | #define WMC_HPFAPP (1 << 7) |
236 | #define WM8978_HPFEN (1 << 8) | 261 | #define WMC_HPFCUT (7 << 4) |
237 | #define WM8978_HPFAPP (1 << 7) | 262 | #define WMC_ADCOSR (1 << 3) |
238 | #define WM8978_HPFCUT (7 << 4) | 263 | #define WMC_ADCRPOL (1 << 1) |
239 | #define WM8978_ADCOSR (1 << 3) | 264 | #define WMC_ADCLPOL (1 << 0) |
240 | #define WM8978_ADCRPOL (1 << 1) | 265 | |
241 | #define WM8978_ADCLPOL (1 << 0) | 266 | /* WMC_LEFT_ADC_DIGITAL_VOL (0x0f) */ |
242 | 267 | /* WMC_RIGHT_ADC_DITIGAL_VOL (0x10) */ | |
243 | /* WM8978_LEFT_ADC_DIGITAL_VOL (0x0f) */ | ||
244 | /* WM8978_RIGHT_ADC_DITIGAL_VOL (0x10) */ | ||
245 | #define WM8978_ADCVU (1 << 8) | ||
246 | /* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */ | 268 | /* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */ |
247 | #define WM8978_ADCVOL (0xff << 0) | 269 | /*Use WMC_DVOL* macros */ |
248 | #define WM8978_ADCVOLr(x) ((x) & 0xff) | 270 | |
249 | #define WM8978_ADCVOLw(x) ((x) & 0xff) | 271 | /* Macros for EQ gain and cutoff */ |
250 | 272 | #define WMC_EQGC 0x1f | |
251 | /* WM8978_EQ1_LOW_SHELF (0x12) */ | 273 | #define WMC_EQGCr(x) ((x) & WMC_EQGC) |
252 | #define WM8978_EQ3DMODE (1 << 8) | 274 | #define WMC_EQGCw(x) ((x) & WMC_EQGC) |
253 | #define WM8978_EQ1C (3 << 5) /* Cutoff */ | 275 | |
254 | #define WM8978_EQ1C_80HZ (0 << 5) /* 80Hz */ | 276 | /* WMC_EQ1_LOW_SHELF (0x12) */ |
255 | #define WM8978_EQ1C_105HZ (1 << 5) /* 105Hz */ | 277 | #define WMC_EQ3DMODE (1 << 8) |
256 | #define WM8978_EQ1C_135HZ (2 << 5) /* 135Hz */ | 278 | #define WMC_EQ1C (3 << 5) /* Cutoff */ |
257 | #define WM8978_EQ1C_175HZ (3 << 5) /* 175Hz */ | 279 | #define WMC_EQ1C_80HZ (0 << 5) /* 80Hz */ |
280 | #define WMC_EQ1C_105HZ (1 << 5) /* 105Hz */ | ||
281 | #define WMC_EQ1C_135HZ (2 << 5) /* 135Hz */ | ||
282 | #define WMC_EQ1C_175HZ (3 << 5) /* 175Hz */ | ||
258 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */ | 283 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */ |
259 | #define WM8978_EQ1G (0x1f << 0) | 284 | |
260 | #define WM8978_EQ1Gr(x) ((x) & WM8978_EQ1G) | 285 | /* WMC_EQ2_PEAK1 (0x13) */ |
261 | #define WM8978_EQ1Gw(x) ((x) & WM8978_EQ1G) | 286 | #define WMC_EQ2BW (1 << 8) |
262 | 287 | #define WMC_EQ2C (3 << 5) /* Center */ | |
263 | /* WM8978_EQ2_PEAK1 (0x13) */ | 288 | #define WMC_EQ2C_230HZ (0 << 5) /* 230Hz */ |
264 | #define WM8978_EQ2BW (1 << 8) | 289 | #define WMC_EQ2C_300HZ (1 << 5) /* 300Hz */ |
265 | #define WM8978_EQ2C (3 << 5) /* Center */ | 290 | #define WMC_EQ2C_385HZ (2 << 5) /* 385Hz */ |
266 | #define WM8978_EQ2C_230HZ (0 << 5) /* 230Hz */ | 291 | #define WMC_EQ2C_500HZ (3 << 5) /* 500Hz */ |
267 | #define WM8978_EQ2C_300HZ (1 << 5) /* 300Hz */ | ||
268 | #define WM8978_EQ2C_385HZ (2 << 5) /* 385Hz */ | ||
269 | #define WM8978_EQ2C_500HZ (3 << 5) /* 500Hz */ | ||
270 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 292 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
271 | 11001-11111=reserved */ | 293 | 11001-11111=reserved */ |
272 | #define WM8978_EQ2G (0x1f << 0) | 294 | |
273 | #define WM8978_EQ2Gr(x) ((x) & WM8978_EQ2G) | 295 | /* WMC_EQ3_PEAK2 (0x14) */ |
274 | #define WM8978_EQ2Gw(x) ((x) & WM8978_EQ2G) | 296 | #define WMC_EQ3BW (1 << 8) |
275 | 297 | #define WMC_EQ3C (3 << 5) /* Center */ | |
276 | /* WM8978_EQ3_PEAK2 (0x14) */ | 298 | #define WMC_EQ3C_650HZ (0 << 5) /* 650Hz */ |
277 | #define WM8978_EQ3BW (1 << 8) | 299 | #define WMC_EQ3C_850HZ (1 << 5) /* 850Hz */ |
278 | #define WM8978_EQ3C (3 << 5) /* Center */ | 300 | #define WMC_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */ |
279 | #define WM8978_EQ3C_650HZ (0 << 5) /* 650Hz */ | 301 | #define WMC_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */ |
280 | #define WM8978_EQ3C_850HZ (1 << 5) /* 850Hz */ | ||
281 | #define WM8978_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */ | ||
282 | #define WM8978_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */ | ||
283 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 302 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
284 | 11001-11111=reserved */ | 303 | 11001-11111=reserved */ |
285 | #define WM8978_EQ3G (0x1f << 0) | 304 | |
286 | #define WM8978_EQ3Gr(x) ((x) & WM8978_EQ3G) | 305 | /* WMC_EQ4_PEAK3 (0x15) */ |
287 | #define WM8978_EQ3Gw(x) ((x) & WM8978_EQ3G) | 306 | #define WMC_EQ4BW (1 << 8) |
288 | 307 | #define WMC_EQ4C (3 << 5) /* Center */ | |
289 | /* WM8978_EQ4_PEAK3 (0x15) */ | 308 | #define WMC_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */ |
290 | #define WM8978_EQ4BW (1 << 8) | 309 | #define WMC_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */ |
291 | #define WM8978_EQ4C (3 << 5) /* Center */ | 310 | #define WMC_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */ |
292 | #define WM8978_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */ | 311 | #define WMC_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */ |
293 | #define WM8978_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */ | ||
294 | #define WM8978_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */ | ||
295 | #define WM8978_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */ | ||
296 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 312 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
297 | 11001-11111=reserved */ | 313 | 11001-11111=reserved */ |
298 | #define WM8978_EQ4G (0x1f << 0) | 314 | |
299 | #define WM8978_EQ4Gr(x) ((x) & WM8978_EQ4G) | 315 | /* WMC_EQ5_HIGH_SHELF (0x16) */ |
300 | #define WM8978_EQ4Gw(x) ((x) & WM8978_EQ4G) | 316 | #define WMC_EQ5C (3 << 5) /* Cutoff */ |
301 | 317 | #define WMC_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */ | |
302 | /* WM8978_EQ5_HIGH_SHELF (0x16) */ | 318 | #define WMC_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */ |
303 | #define WM8978_EQ5C (3 << 5) /* Cutoff */ | 319 | #define WMC_EQ5C_9KHZ (2 << 5) /* 9.0kHz */ |
304 | #define WM8978_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */ | 320 | #define WMC_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */ |
305 | #define WM8978_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */ | ||
306 | #define WM8978_EQ5C_9KHZ (2 << 5) /* 9.0kHz */ | ||
307 | #define WM8978_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */ | ||
308 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, | 321 | /* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, |
309 | 11001-11111=reserved */ | 322 | 11001-11111=reserved */ |
310 | #define WM8978_EQ5G (0x1f << 0) | ||
311 | #define WM8978_EQ5Gr(x) ((x) & WM8978_EQ5G) | ||
312 | #define WM8978_EQ5Gw(x) ((x) & WM8978_EQ5G) | ||
313 | 323 | ||
314 | /* WM8978_DAC_LIMITER1 (0x18) */ | 324 | /* WMC_DAC_LIMITER1 (0x18) */ |
315 | #define WM8978_LIMEN (1 << 8) | 325 | #define WMC_LIMEN (1 << 8) |
316 | /* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */ | 326 | /* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */ |
317 | #define WM8978_LIMDCY (0xf << 4) | 327 | #define WMC_LIMDCY (0xf << 4) |
318 | #define WM8978_LIMDCYr(x) (((x) & WM8978_LIMDCY) >> 4) | 328 | #define WMC_LIMDCYr(x) (((x) & WMC_LIMDCY) >> 4) |
319 | #define WM8978_LIMDCYw(x) (((x) << 4) & WM8978_LIMDCY) | 329 | #define WMC_LIMDCYw(x) (((x) << 4) & WMC_LIMDCY) |
320 | /* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */ | 330 | /* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */ |
321 | #define WM8978_LIMATK (0xf << 0) | 331 | #define WMC_LIMATK (0xf << 0) |
322 | #define WM8978_LIMATKr(x) ((x) & WM8978_LIMATK) | 332 | #define WMC_LIMATKr(x) ((x) & WMC_LIMATK) |
323 | #define WM8978_LIMATKw(x) ((x) & WM8978_LIMATK) | 333 | #define WMC_LIMATKw(x) ((x) & WMC_LIMATK) |
324 | 334 | ||
325 | /* WM8978_DAC_LIMITER2 (0x19) */ | 335 | /* WMC_DAC_LIMITER2 (0x19) */ |
326 | #define WM8978_LIMLVL (7 << 4) | 336 | #define WMC_LIMLVL (7 << 4) |
327 | /* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */ | 337 | /* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */ |
328 | #define WM8978_LIMLVLr(x) (((x) & WM8978_LIMLVL) >> 4) | 338 | #define WMC_LIMLVLr(x) (((x) & WMC_LIMLVL) >> 4) |
329 | #define WM8978_LIMLVLw(x) (((x) << 4) & WM8978_LIMLVL) | 339 | #define WMC_LIMLVLw(x) (((x) << 4) & WMC_LIMLVL) |
330 | #define WM8978_LIMBOOST (0xf << 0) | 340 | #define WMC_LIMBOOST (0xf << 0) |
331 | /* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */ | 341 | /* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */ |
332 | #define WM8978_LIMBOOSTr(x) (((x) & WM8978_LIMBOOST) | 342 | #define WMC_LIMBOOSTr(x) (((x) & WMC_LIMBOOST) |
333 | #define WM8978_LIMBOOSTw(x) (((x) & WM8978_LIMBOOST) | 343 | #define WMC_LIMBOOSTw(x) (((x) & WMC_LIMBOOST) |
334 | 344 | ||
335 | /* WM8978_NOTCH_FILTER1 (0x1b) */ | 345 | |
336 | #define WM8978_NFU1 (1 << 8) | 346 | /* Generic notch filter bits and macros */ |
337 | #define WM8978_NFEN (1 << 7) | 347 | #define WMC_NFU (1 << 8) |
338 | #define WM8978_NFA0_13_7 (0x7f << 0) | 348 | #define WMC_NFA (0x7f << 0) |
339 | #define WM8978_NFA0_13_7r(x) ((x) & WM8978_NFA0_13_7) | 349 | #define WMC_NFAr(x) ((x) & WMC_NFA) |
340 | #define WM8978_NFA0_13_7w(x) ((x) & WM8978_NFA0_13_7) | 350 | #define WMC_NFAw(x) ((x) & WMC_NFA) |
341 | 351 | ||
342 | /* WM8978_NOTCH_FILTER2 (0x1c) */ | 352 | /* WMC_NOTCH_FILTER1 (0x1b) */ |
343 | #define WM8978_NFU2 (1 << 8) | 353 | #define WMC_NFEN (1 << 7) |
344 | #define WM8978_NFA0_6_0 (0x7f << 0) | 354 | /* WMC_NOTCH_FILTER2 (0x1c) */ |
345 | #define WM8978_NFA0_6_0r(x) ((x) & WM8978_NFA0_6_0) | 355 | /* WMC_NOTCH_FILTER3 (0x1d) */ |
346 | #define WM8978_NFA0_6_0w(x) ((x) & WM8978_NFA0_6_0) | 356 | /* WMC_NOTCH_FILTER4 (0x1e) */ |
347 | 357 | ||
348 | /* WM8978_NOTCH_FILTER3 (0x1d) */ | 358 | /* WMC_ALC_CONTROL1 (0x20) */ |
349 | #define WM8978_NFU3 (1 << 8) | 359 | #define WMC_ALCSEL (3 << 7) |
350 | #define WM8978_NFA1_13_7 (0x7f << 0) | 360 | #define WMC_ALCSEL_OFF (0 << 7) |
351 | #define WM8978_NFA1_13_7r(x) ((x) & WM8978_NFA1_13_7) | 361 | #define WMC_ALCSEL_RIGHT_ONLY (1 << 7) |
352 | #define WM8978_NFA1_13_7w(x) ((x) & WM8978_NFA1_13_7) | 362 | #define WMC_ALCSEL_LEFT_ONLY (2 << 7) |
353 | 363 | #define WMC_ALCSEL_BOTH_ON (3 << 7) | |
354 | /* WM8978_NOTCH_FILTER4 (0x1e) */ | ||
355 | #define WM8978_NFU4 (1 << 8) | ||
356 | #define WM8978_NFA1_6_0 (0x7f << 0) | ||
357 | #define WM8978_NFA1_6_0r(x) ((x) & WM8978_NFA1_6_0) | ||
358 | #define WM8978_NFA1_6_0w(x) ((x) & WM8978_NFA1_6_0) | ||
359 | |||
360 | /* WM8978_ALC_CONTROL1 (0x20) */ | ||
361 | #define WM8978_ALCSEL (3 << 7) | ||
362 | #define WM8978_ALCSEL_OFF (0 << 7) | ||
363 | #define WM8978_ALCSEL_RIGHT_ONLY (1 << 7) | ||
364 | #define WM8978_ALCSEL_LEFT_ONLY (2 << 7) | ||
365 | #define WM8978_ALCSEL_BOTH_ON (3 << 7) | ||
366 | /* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */ | 364 | /* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */ |
367 | #define WM8978_ALCMAXGAIN (7 << 3) | 365 | #define WMC_ALCMAXGAIN (7 << 3) |
368 | #define WM8978_ALCMAXGAINr(x) (((x) & WM8978_ALCMAXGAIN) >> 3) | 366 | #define WMC_ALCMAXGAINr(x) (((x) & WMC_ALCMAXGAIN) >> 3) |
369 | #define WM8978_ALCMAXGAINw(x) (((x) << 3) & WM8978_ALCMAXGAIN) | 367 | #define WMC_ALCMAXGAINw(x) (((x) << 3) & WMC_ALCMAXGAIN) |
370 | /* 000:-12dB...(6dB steps)...111:+30dB */ | 368 | /* 000:-12dB...(6dB steps)...111:+30dB */ |
371 | #define WM8978_ALCMINGAIN (7 << 0) | 369 | #define WMC_ALCMINGAIN (7 << 0) |
372 | #define WM8978_ALCMINGAINr(x) ((x) & WM8978_ALCMINGAIN) | 370 | #define WMC_ALCMINGAINr(x) ((x) & WMC_ALCMINGAIN) |
373 | #define WM8978_ALCMINGAINw(x) ((x) & WM8978_ALCMINGAIN) | 371 | #define WMC_ALCMINGAINw(x) ((x) & WMC_ALCMINGAIN) |
374 | 372 | ||
375 | /* WM8978_ALC_CONTROL2 (0x21) */ | 373 | /* WMC_ALC_CONTROL2 (0x21) */ |
376 | /* 0000=0ms, 0001=2.67ms, 0010=5.33ms... | 374 | /* 0000=0ms, 0001=2.67ms, 0010=5.33ms... |
377 | (2x with every step)...43.691s */ | 375 | (2x with every step)...43.691s */ |
378 | #define WM8978_ALCHLD (0xf << 4) | 376 | #define WMC_ALCHLD (0xf << 4) |
379 | #define WM8978_ALCHLDr(x) (((x) & WM8978_ALCHLD) >> 4) | 377 | #define WMC_ALCHLDr(x) (((x) & WMC_ALCHLD) >> 4) |
380 | #define WM8978_ALCHLDw(x) (((x) << 4) & WM8978_ALCHLD) | 378 | #define WMC_ALCHLDw(x) (((x) << 4) & WMC_ALCHLD) |
381 | /* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS... | 379 | /* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS... |
382 | (-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */ | 380 | (-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */ |
383 | #define WM8978_ALCLVL (0xf << 0) | 381 | #define WMC_ALCLVL (0xf << 0) |
384 | #define WM8978_ALCLVLr(x) ((x) & WM8978_ALCLVL) | 382 | #define WMC_ALCLVLr(x) ((x) & WMC_ALCLVL) |
385 | #define WM8978_ALCLVLw(x) ((x) & WM8978_ALCLVL) | 383 | #define WMC_ALCLVLw(x) ((x) & WMC_ALCLVL) |
386 | 384 | ||
387 | /* WM8978_ALC_CONTROL3 (0x22) */ | 385 | /* WMC_ALC_CONTROL3 (0x22) */ |
388 | #define WM8978_ALCMODE (1 << 8) | 386 | #define WMC_ALCMODE (1 << 8) |
389 | #define WM8978_ALCDCY (0xf << 4) | 387 | #define WMC_ALCDCY (0xf << 4) |
390 | #define WM8978_ALCATK (0xf << 0) | 388 | #define WMC_ALCATK (0xf << 0) |
391 | 389 | ||
392 | /* WM8978_NOISE_GATE (0x23) */ | 390 | /* WMC_NOISE_GATE (0x23) */ |
393 | #define WM8978_NGEN (1 << 3) | 391 | #define WMC_NGEN (1 << 3) |
394 | /* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */ | 392 | /* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */ |
395 | #define WM8978_NGTH (7 << 0) | 393 | #define WMC_NGTH (7 << 0) |
396 | #define WM8978_NGTHr(x) ((x) & WM8978_NGTH) | 394 | #define WMC_NGTHr(x) ((x) & WMC_NGTH) |
397 | #define WM8978_NGTHw(x) ((x) & WM8978_NGTH) | 395 | #define WMC_NGTHw(x) ((x) & WMC_NGTH) |
398 | 396 | ||
399 | /* WM8978_PLL_N (0x24) */ | 397 | /* WMC_PLL_N (0x24) */ |
400 | #define WM8978_PLL_PRESCALE (1 << 4) | 398 | #define WMC_PLL_PRESCALE (1 << 4) |
401 | #define WM8978_PLLN (0xf << 0) | 399 | #define WMC_PLLN (0xf << 0) |
402 | #define WM8978_PLLNr(x) ((x) & WM8978_PLLN) | 400 | #define WMC_PLLNr(x) ((x) & WMC_PLLN) |
403 | #define WM8978_PLLNw(x) ((x) & WM8978_PLLN) | 401 | #define WMC_PLLNw(x) ((x) & WMC_PLLN) |
404 | 402 | ||
405 | /* WM8978_PLL_K1 (0x25) */ | 403 | /* WMC_PLL_K1 (0x25) */ |
406 | #define WM8978_PLLK_23_18 (0x3f << 0) | 404 | #define WMC_PLLK_23_18 (0x3f << 0) |
407 | #define WM8978_PLLK_23_18r(x) ((x) & WM8978_PLLK_23_18) | 405 | #define WMC_PLLK_23_18r(x) ((x) & WMC_PLLK_23_18) |
408 | #define WM8978_PLLK_23_18w(x) ((x) & WM8978_PLLK_23_18) | 406 | #define WMC_PLLK_23_18w(x) ((x) & WMC_PLLK_23_18) |
409 | 407 | ||
410 | /* WM8978_PLL_K2 (0x26) */ | 408 | /* WMC_PLL_K2 (0x26) */ |
411 | #define WM8978_PLLK_17_9 (0x1ff << 0) | 409 | #define WMC_PLLK_17_9 (0x1ff << 0) |
412 | #define WM8978_PLLK_17_9r(x) ((x) & WM8978_PLLK_17_9) | 410 | #define WMC_PLLK_17_9r(x) ((x) & WMC_PLLK_17_9) |
413 | #define WM8978_PLLK_17_9w(x) ((x) & WM8978_PLLK_17_9) | 411 | #define WMC_PLLK_17_9w(x) ((x) & WMC_PLLK_17_9) |
414 | 412 | ||
415 | /* WM8978_PLL_K3 (0x27) */ | 413 | /* WMC_PLL_K3 (0x27) */ |
416 | #define WM8978_PLLK_8_0 (0x1ff << 0) | 414 | #define WMC_PLLK_8_0 (0x1ff << 0) |
417 | #define WM8978_PLLK_8_0r(x) ((x) & WM8978_PLLK_8_0) | 415 | #define WMC_PLLK_8_0r(x) ((x) & WMC_PLLK_8_0) |
418 | #define WM8978_PLLK_8_0w(x) ((x) & WM8978_PLLK_8_0) | 416 | #define WMC_PLLK_8_0w(x) ((x) & WMC_PLLK_8_0) |
419 | 417 | ||
420 | /* WM8978_3D_CONTROL (0x29) */ | 418 | /* WMC_3D_CONTROL (0x29) */ |
421 | /* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */ | 419 | /* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */ |
422 | #define WM8978_DEPTH3D (0xf << 0) | 420 | #define WMC_DEPTH3D (0xf << 0) |
423 | #define WM8978_DEPTH3Dw(x) ((x) & WM8978_DEPTH3D) | 421 | #define WMC_DEPTH3Dw(x) ((x) & WMC_DEPTH3D) |
424 | #define WM8978_DEPTH3Dr(x) ((x) & WM8978_DEPTH3D) | 422 | #define WMC_DEPTH3Dr(x) ((x) & WMC_DEPTH3D) |
425 | 423 | ||
426 | /* WM8978_BEEP_CONTROL (0x2b) */ | 424 | /* WMC_BEEP_CONTROL (0x2b) */ |
427 | #define WM8978_MUTERPGA2INV (1 << 5) | 425 | #define WMC_MUTERPGA2INV (1 << 5) |
428 | #define WM8978_INVROUT2 (1 << 4) | 426 | #define WMC_INVROUT2 (1 << 4) |
429 | /* 000=-15dB, 001=-12dB...111=+6dB */ | 427 | /* 000=-15dB, 001=-12dB...111=+6dB */ |
430 | #define WM8978_BEEPVOL (7 << 1) | 428 | #define WMC_BEEPVOL (7 << 1) |
431 | #define WM8978_BEEPVOLr(x) (((x) & WM8978_BEEPVOL) >> 1) | 429 | #define WMC_BEEPVOLr(x) (((x) & WMC_BEEPVOL) >> 1) |
432 | #define WM8978_BEEPVOLw(x) (((x) << 1) & WM8978_BEEPVOL) | 430 | #define WMC_BEEPVOLw(x) (((x) << 1) & WMC_BEEPVOL) |
433 | #define WM8978_BEEPEN (1 << 0) | 431 | #define WMC_BEEPEN (1 << 0) |
434 | 432 | ||
435 | /* WM8978_INPUT_CTRL (0x2c) */ | 433 | /* WMC_INPUT_CTRL (0x2c) */ |
436 | #define WM8978_MBVSEL (1 << 8) | 434 | #define WMC_MBVSEL (1 << 8) |
437 | #define WM8978_R2_2INPPGA (1 << 6) | 435 | #define WMC_R2_2INPPGA (1 << 6) |
438 | #define WM8978_RIN2INPPGA (1 << 5) | 436 | #define WMC_RIN2INPPGA (1 << 5) |
439 | #define WM8978_RIP2INPPGA (1 << 4) | 437 | #define WMC_RIP2INPPGA (1 << 4) |
440 | #define WM8978_L2_2INPPGA (1 << 2) | 438 | #define WMC_L2_2INPPGA (1 << 2) |
441 | #define WM8978_LIN2INPPGA (1 << 1) | 439 | #define WMC_LIN2INPPGA (1 << 1) |
442 | #define WM8978_LIP2INPPGA (1 << 0) | 440 | #define WMC_LIP2INPPGA (1 << 0) |
443 | 441 | ||
444 | /* WM8978_LEFT_INP_PGA_GAIN_CTRL (0x2d) */ | 442 | /* WMC_LEFT_INP_PGA_GAIN_CTRL (0x2d) */ |
445 | #define WM8978_INPPGAUPDATEL (1 << 8) | ||
446 | #define WM8978_NPPGAZCL (1 << 7) | ||
447 | #define WM8978_INPPGAMUTEL (1 << 6) | ||
448 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ | 443 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ |
449 | #define WM8978_INPPGAVOLL (0x3f << 0) | 444 | /* Uses WMC_AVOL* macros */ |
450 | #define WM8978_INPPGAVOLLr(x) ((x) & WM8978_INPPGAVOLL) | 445 | |
451 | #define WM8978_INPPGAVOLLw(x) ((x) & WM8978_INPPGAVOLL) | 446 | /* WMC_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */ |
452 | |||
453 | /* WM8978_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */ | ||
454 | #define WM8978_INPPGAUPDATER (1 << 8) | ||
455 | #define WM8978_NPPGAZCR (1 << 7) | ||
456 | #define WM8978_INPPGAMUTER (1 << 6) | ||
457 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ | 447 | /* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */ |
458 | #define WM8978_INPPGAVOLR (0x3f << 0) | 448 | /* Uses WMC_AVOL* macros */ |
459 | #define WM8978_INPPGAVOLRr(x) ((x) & WM8978_INPPGAVOLR) | ||
460 | #define WM8978_INPPGAVOLRw(x) ((x) & WM8978_INPPGAVOLR) | ||
461 | 449 | ||
462 | /* WM8978_LEFT_ADC_BOOST_CTRL (0x2f) */ | 450 | /* WMC_LEFT_ADC_BOOST_CTRL (0x2f) */ |
463 | #define WM8978_PGABOOSTL (1 << 8) | 451 | #define WMC_PGABOOSTL (1 << 8) |
464 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 452 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
465 | #define WM8978_L2_2BOOSTVOL (7 << 4) | 453 | #define WMC_L2_2BOOSTVOL (7 << 4) |
466 | #define WM8978_L2_2BOOSTVOLr(x) ((x) & WM8978_L2_2_BOOSTVOL) >> 4) | 454 | #define WMC_L2_2BOOSTVOLr(x) ((x) & WMC_L2_2_BOOSTVOL) >> 4) |
467 | #define WM8978_L2_2BOOSTVOLw(x) ((x) << 4) & WM8978_L2_2_BOOSTVOL) | 455 | #define WMC_L2_2BOOSTVOLw(x) ((x) << 4) & WMC_L2_2_BOOSTVOL) |
468 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 456 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
469 | #define WM8978_AUXL2BOOSTVOL (7 << 0) | 457 | #define WMC_AUXL2BOOSTVOL (7 << 0) |
470 | #define WM8978_AUXL2BOOSTVOLr(x) ((x) & WM8978_AUXL2BOOSTVOL) | 458 | #define WMC_AUXL2BOOSTVOLr(x) ((x) & WMC_AUXL2BOOSTVOL) |
471 | #define WM8978_AUXL2BOOSTVOLw(x) ((x) & WM8978_AUXL2BOOSTVOL) | 459 | #define WMC_AUXL2BOOSTVOLw(x) ((x) & WMC_AUXL2BOOSTVOL) |
472 | 460 | ||
473 | /* WM8978_RIGHT_ADC_BOOST_CTRL (0x30) */ | 461 | /* WMC_RIGHT_ADC_BOOST_CTRL (0x30) */ |
474 | #define WM8978_PGABOOSTR (1 << 8) | 462 | #define WMC_PGABOOSTR (1 << 8) |
475 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 463 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
476 | #define WM8978_R2_2_BOOSTVOL (7 << 4) | 464 | #define WMC_R2_2_BOOSTVOL (7 << 4) |
477 | #define WM8978_R2_2BOOSTVOLr(x) ((x) & WM8978_R2_2_BOOSTVOL) >> 4) | 465 | #define WMC_R2_2BOOSTVOLr(x) ((x) & WMC_R2_2_BOOSTVOL) >> 4) |
478 | #define WM8978_R2_2BOOSTVOLw(x) ((x) << 4) & WM8978_R2_2_BOOSTVOL) | 466 | #define WMC_R2_2BOOSTVOLw(x) ((x) << 4) & WMC_R2_2_BOOSTVOL) |
479 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ | 467 | /* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */ |
480 | #define WM8978_AUXR2BOOSTVOL (7 << 0) | 468 | #define WMC_AUXR2BOOSTVOL (7 << 0) |
481 | #define WM8978_AUXR2BOOSTVOLr(x) ((x) & WM8978_AUXR2BOOSTVOL) | 469 | #define WMC_AUXR2BOOSTVOLr(x) ((x) & WMC_AUXR2BOOSTVOL) |
482 | #define WM8978_AUXR2BOOSTVOLw(x) ((x) & WM8978_AUXR2BOOSTVOL) | 470 | #define WMC_AUXR2BOOSTVOLw(x) ((x) & WMC_AUXR2BOOSTVOL) |
483 | 471 | ||
484 | /* WM8978_OUTPUT_CTRL (0x31) */ | 472 | /* WMC_OUTPUT_CTRL (0x31) */ |
485 | #define WM8978_DACL2RMIX (1 << 6) | 473 | #define WMC_DACL2RMIX (1 << 6) |
486 | #define WM8978_DACR2LMIX (1 << 5) | 474 | #define WMC_DACR2LMIX (1 << 5) |
487 | #define WM8978_OUT4BOOST (1 << 4) | 475 | #define WMC_OUT4BOOST (1 << 4) |
488 | #define WM8978_OUT3BOOST (1 << 3) | 476 | #define WMC_OUT3BOOST (1 << 3) |
489 | #define WM8978_SPKBOOST (1 << 2) | 477 | #define WMC_SPKBOOST (1 << 2) |
490 | #define WM8978_TSDEN (1 << 1) | 478 | #define WMC_TSDEN (1 << 1) |
491 | #define WM8978_VROI (1 << 0) | 479 | #define WMC_VROI (1 << 0) |
492 | 480 | ||
493 | /* WM8978_LEFT_MIXER_CTRL (0x32) */ | 481 | /* WMC_LEFT_MIXER_CTRL (0x32) */ |
494 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 482 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
495 | #define WM8978_AUXLMIXVOL (7 << 6) | 483 | #define WMC_AUXLMIXVOL (7 << 6) |
496 | #define WM8978_AUXLMIXVOLr(x) ((x) & WM8978_AUXLMIXVOL) >> 6) | 484 | #define WMC_AUXLMIXVOLr(x) ((x) & WMC_AUXLMIXVOL) >> 6) |
497 | #define WM8978_AUXLMIXVOLw(x) ((x) << 6) & WM8978_AUXLMIXVOL) | 485 | #define WMC_AUXLMIXVOLw(x) ((x) << 6) & WMC_AUXLMIXVOL) |
498 | #define WM8978_AUXL2LMIX (1 << 5) | 486 | #define WMC_AUXL2LMIX (1 << 5) |
499 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 487 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
500 | #define WM8978_BYPLMIXVOL (7 << 2) | 488 | #define WMC_BYPLMIXVOL (7 << 2) |
501 | #define WM8978_BYPLMIXVOLr(x) ((x) & WM8978_BYPLMIXVOL) >> 2) | 489 | #define WMC_BYPLMIXVOLr(x) ((x) & WMC_BYPLMIXVOL) >> 2) |
502 | #define WM8978_BYPLMIXVOLw(x) ((x) << 2) & WM8978_BYPLMIXVOL) | 490 | #define WMC_BYPLMIXVOLw(x) ((x) << 2) & WMC_BYPLMIXVOL) |
503 | #define WM8978_BYPL2LMIX (1 << 1) | 491 | #define WMC_BYPL2LMIX (1 << 1) |
504 | #define WM8978_DACL2LMIX (1 << 0) | 492 | #define WMC_DACL2LMIX (1 << 0) |
505 | 493 | ||
506 | /* WM8978_RIGHT_MIXER_CTRL (0x33) */ | 494 | /* WMC_RIGHT_MIXER_CTRL (0x33) */ |
507 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 495 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
508 | #define WM8978_AUXRMIXVOL (7 << 6) | 496 | #define WMC_AUXRMIXVOL (7 << 6) |
509 | #define WM8978_AUXRMIXVOLr(x) ((x) & WM8978_AUXRMIXVOL) >> 6) | 497 | #define WMC_AUXRMIXVOLr(x) ((x) & WMC_AUXRMIXVOL) >> 6) |
510 | #define WM8978_AUXRMIXVOLw(x) ((x) << 6) & WM8978_AUXRMIXVOL) | 498 | #define WMC_AUXRMIXVOLw(x) ((x) << 6) & WMC_AUXRMIXVOL) |
511 | #define WM8978_AUXR2RMIX (1 << 5) | 499 | #define WMC_AUXR2RMIX (1 << 5) |
512 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ | 500 | /* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */ |
513 | #define WM8978_BYPRMIXVOL (7 << 2) | 501 | #define WMC_BYPRMIXVOL (7 << 2) |
514 | #define WM8978_BYPRMIXVOLr(x) ((x) & WM8978_BYPRMIXVOL) >> 2) | 502 | #define WMC_BYPRMIXVOLr(x) ((x) & WMC_BYPRMIXVOL) >> 2) |
515 | #define WM8978_BYPRMIXVOLw(x) ((x) << 2) & WM8978_BYPRMIXVOL) | 503 | #define WMC_BYPRMIXVOLw(x) ((x) << 2) & WMC_BYPRMIXVOL) |
516 | #define WM8978_BYPR2RMIX (1 << 1) | 504 | #define WMC_BYPR2RMIX (1 << 1) |
517 | #define WM8978_DACR2RMIX (1 << 0) | 505 | #define WMC_DACR2RMIX (1 << 0) |
518 | 506 | ||
519 | /* WM8978_LOUT1_HP_VOLUME_CTRL (0x34) */ | 507 | /* WMC_LOUT1_HP_VOLUME_CTRL (0x34) */ |
520 | #define WM8978_LHPVU (1 << 8) | 508 | /* WMC_ROUT1_HP_VOLUME_CTRL (0x35) */ |
521 | #define WM8978_LOUT1ZC (1 << 7) | 509 | /* WMC_LOUT2_SPK_VOLUME_CTRL (0x36) */ |
522 | #define WM8978_LOUT1MUTE (1 << 6) | 510 | /* WMC_ROUT2_SPK_VOLUME_CTRL (0x37) */ |
523 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
524 | #define WM8978_LOUT1VOL (0x3f << 0) | ||
525 | #define WM8978_LOUT1VOLr(x) ((x) & WM8978_LOUT1VOL) | ||
526 | #define WM8978_LOUT1VOLw(x) ((x) & WM8978_LOUT1VOL) | ||
527 | |||
528 | /* WM8978_ROUT1_HP_VOLUME_CTRL (0x35) */ | ||
529 | #define WM8978_RHPVU (1 << 8) | ||
530 | #define WM8978_ROUT1ZC (1 << 7) | ||
531 | #define WM8978_ROUT1MUTE (1 << 6) | ||
532 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
533 | #define WM8978_ROUT1VOL (0x3f << 0) | ||
534 | #define WM8978_ROUT1VOLr(x) ((x) & WM8978_ROUT1VOL) | ||
535 | #define WM8978_ROUT1VOLw(x) ((x) & WM8978_ROUT1VOL) | ||
536 | |||
537 | /* WM8978_LOUT2_SPK_VOLUME_CTRL (0x36) */ | ||
538 | #define WM8978_LSPKVU (1 << 8) | ||
539 | #define WM8978_LOUT2ZC (1 << 7) | ||
540 | #define WM8978_LOUT2MUTE (1 << 6) | ||
541 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | ||
542 | #define WM8978_LOUT2VOL (0x3f << 0) | ||
543 | #define WM8978_LOUT2VOLr(x) ((x) & WM8978_LOUT2VOL) | ||
544 | #define WM8978_LOUT2VOLw(x) ((x) & WM8978_LOUT2VOL) | ||
545 | |||
546 | /* WM8978_ROUT2_SPK_VOLUME_CTRL (0x37) */ | ||
547 | #define WM8978_RSPKVU (1 << 8) | ||
548 | #define WM8978_ROUT2ZC (1 << 7) | ||
549 | #define WM8978_ROUT2MUTE (1 << 6) | ||
550 | /* 000000=-57dB...111001=0dB...111111=+6dB */ | 511 | /* 000000=-57dB...111001=0dB...111111=+6dB */ |
551 | #define WM8978_ROUT2VOL (0x3f << 0) | 512 | /* Uses WMC_AVOL* macros */ |
552 | #define WM8978_ROUT2VOLr(x) ((x) & WM8978_ROUT2VOL) | 513 | |
553 | #define WM8978_ROUT2VOLw(x) ((x) & WM8978_ROUT2VOL) | 514 | /* WMC_OUT3_MIXER_CTRL (0x38) */ |
554 | 515 | #define WMC_OUT3MUTE (1 << 6) | |
555 | /* WM8978_OUT3_MIXER_CTRL (0x38) */ | 516 | #define WMC_OUT42OUT3 (1 << 3) |
556 | #define WM8978_OUT3MUTE (1 << 6) | 517 | #define WMC_BYPL2OUT3 (1 << 2) |
557 | #define WM8978_OUT42OUT3 (1 << 3) | 518 | #define WMC_LMIX2OUT3 (1 << 1) |
558 | #define WM8978_BYPL2OUT3 (1 << 2) | 519 | #define WMC_LDAC2OUT3 (1 << 0) |
559 | #define WM8978_LMIX2OUT3 (1 << 1) | 520 | |
560 | #define WM8978_LDAC2OUT3 (1 << 0) | 521 | /* WMC_OUT4_MONO_MIXER_CTRL (0x39) */ |
561 | 522 | #define WMC_OUT4MUTE (1 << 6) | |
562 | /* WM8978_OUT4_MONO_MIXER_CTRL (0x39) */ | 523 | #define WMC_HALFSIG (1 << 5) |
563 | #define WM8978_OUT4MUTE (1 << 6) | 524 | #define WMC_LMIX2OUT4 (1 << 4) |
564 | #define WM8978_HALFSIG (1 << 5) | 525 | #define WMC_LDAC2OUT4 (1 << 3) |
565 | #define WM8978_LMIX2OUT4 (1 << 4) | 526 | #define WMC_BYPR2OUT4 (1 << 2) |
566 | #define WM8978_LDAC2OUT4 (1 << 3) | 527 | #define WMC_RMIX2OUT4 (1 << 1) |
567 | #define WM8978_BYPR2OUT4 (1 << 2) | 528 | #define WMC_RDAC2OUT4 (1 << 0) |
568 | #define WM8978_RMIX2OUT4 (1 << 1) | ||
569 | #define WM8978_RDAC2OUT4 (1 << 0) | ||
570 | 529 | ||
571 | #endif /* _WM8978_H */ | 530 | #endif /* _WM8978_H */ |
diff --git a/firmware/sound.c b/firmware/sound.c index 97d4bc268c..45d3e4b1b6 100644 --- a/firmware/sound.c +++ b/firmware/sound.c | |||
@@ -308,7 +308,7 @@ static void set_prescaled_volume(void) | |||
308 | audiohw_set_lineout_vol(tenthdb2master(0), tenthdb2master(0)); | 308 | audiohw_set_lineout_vol(tenthdb2master(0), tenthdb2master(0)); |
309 | #endif | 309 | #endif |
310 | 310 | ||
311 | #elif defined(HAVE_TLV320) | 311 | #elif defined(HAVE_TLV320) || defined(HAVE_WM8978) |
312 | audiohw_set_headphone_vol(tenthdb2master(l), tenthdb2master(r)); | 312 | audiohw_set_headphone_vol(tenthdb2master(l), tenthdb2master(r)); |
313 | #endif | 313 | #endif |
314 | } | 314 | } |
@@ -333,7 +333,8 @@ void sound_set_volume(int value) | |||
333 | #elif (CONFIG_CODEC == MAS3507D) || defined HAVE_UDA1380 \ | 333 | #elif (CONFIG_CODEC == MAS3507D) || defined HAVE_UDA1380 \ |
334 | || defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \ | 334 | || defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \ |
335 | || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ | 335 | || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ |
336 | || defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) | 336 | || defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) \ |
337 | || defined(HAVE_WM8978) | ||
337 | current_volume = value * 10; /* tenth of dB */ | 338 | current_volume = value * 10; /* tenth of dB */ |
338 | set_prescaled_volume(); | 339 | set_prescaled_volume(); |
339 | #elif CONFIG_CPU == PNX0101 | 340 | #elif CONFIG_CPU == PNX0101 |
@@ -353,7 +354,8 @@ void sound_set_balance(int value) | |||
353 | #elif CONFIG_CODEC == MAS3507D || defined HAVE_UDA1380 \ | 354 | #elif CONFIG_CODEC == MAS3507D || defined HAVE_UDA1380 \ |
354 | || defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \ | 355 | || defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \ |
355 | || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ | 356 | || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ |
356 | || defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) | 357 | || defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) \ |
358 | || defined(HAVE_WM8978) | ||
357 | current_balance = value * VOLUME_RANGE / 100; /* tenth of dB */ | 359 | current_balance = value * VOLUME_RANGE / 100; /* tenth of dB */ |
358 | set_prescaled_volume(); | 360 | set_prescaled_volume(); |
359 | #elif CONFIG_CPU == PNX0101 | 361 | #elif CONFIG_CPU == PNX0101 |
diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c index 94df64b6d7..9fe2eae584 100644 --- a/firmware/target/arm/imx31/debug-imx31.c +++ b/firmware/target/arm/imx31/debug-imx31.c | |||
@@ -27,9 +27,128 @@ | |||
27 | #include "mc13783.h" | 27 | #include "mc13783.h" |
28 | #include "adc.h" | 28 | #include "adc.h" |
29 | 29 | ||
30 | #define CONFIG_CLK32_FREQ 32768 | ||
31 | #define CONFIG_HCLK_FREQ 27000000 | ||
32 | |||
33 | /* Return PLL frequency in HZ */ | ||
34 | static unsigned int decode_pll(unsigned int reg, | ||
35 | unsigned int infreq) | ||
36 | { | ||
37 | uint64_t mfi = (reg >> 10) & 0xf; | ||
38 | uint64_t mfn = reg & 0x3ff; | ||
39 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; | ||
40 | uint64_t pd = ((reg >> 26) & 0xf) + 1; | ||
41 | |||
42 | mfi = mfi <= 5 ? 5 : mfi; | ||
43 | |||
44 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); | ||
45 | } | ||
46 | |||
47 | /* Get the PLL reference clock frequency */ | ||
48 | static unsigned int get_pll_ref_clk_freq(void) | ||
49 | { | ||
50 | if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1)) | ||
51 | return CONFIG_CLK32_FREQ * 1024; | ||
52 | else | ||
53 | return CONFIG_HCLK_FREQ; | ||
54 | } | ||
55 | |||
30 | bool __dbg_hw_info(void) | 56 | bool __dbg_hw_info(void) |
31 | { | 57 | { |
32 | return false; | 58 | char buf[50]; |
59 | int line; | ||
60 | unsigned int pllref; | ||
61 | unsigned int mcu_pllfreq, ser_pllfreq, usb_pllfreq; | ||
62 | uint32_t mpctl, spctl, upctl; | ||
63 | unsigned int freq; | ||
64 | uint32_t regval; | ||
65 | |||
66 | lcd_setmargins(0, 0); | ||
67 | lcd_clear_display(); | ||
68 | lcd_setfont(FONT_SYSFIXED); | ||
69 | |||
70 | while (1) | ||
71 | { | ||
72 | line = 0; | ||
73 | mpctl = CLKCTL_MPCTL; | ||
74 | spctl = CLKCTL_SPCTL; | ||
75 | upctl = CLKCTL_UPCTL; | ||
76 | |||
77 | pllref = get_pll_ref_clk_freq(); | ||
78 | |||
79 | mcu_pllfreq = decode_pll(mpctl, pllref); | ||
80 | ser_pllfreq = decode_pll(spctl, pllref); | ||
81 | usb_pllfreq = decode_pll(upctl, pllref); | ||
82 | |||
83 | snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref); | ||
84 | lcd_puts(0, line++, buf); line++; | ||
85 | |||
86 | /* MCU clock domain */ | ||
87 | snprintf(buf, sizeof (buf), "MPCTL: %08lX", mpctl); | ||
88 | lcd_puts(0, line++, buf); | ||
89 | |||
90 | snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq); | ||
91 | lcd_puts(0, line++, buf); line++; | ||
92 | |||
93 | regval = CLKCTL_PDR0; | ||
94 | snprintf(buf, sizeof (buf), " PDR0: %08lX", regval); | ||
95 | lcd_puts(0, line++, buf); | ||
96 | |||
97 | freq = mcu_pllfreq / (((regval & 0x7) + 1)); | ||
98 | snprintf(buf, sizeof (buf), " mcu_clk: %u", freq); | ||
99 | lcd_puts(0, line++, buf); | ||
100 | |||
101 | freq = mcu_pllfreq / (((regval >> 11) & 0x7) + 1); | ||
102 | snprintf(buf, sizeof (buf), " hsp_clk: %u", freq); | ||
103 | lcd_puts(0, line++, buf); | ||
104 | |||
105 | freq = mcu_pllfreq / (((regval >> 3) & 0x7) + 1); | ||
106 | snprintf(buf, sizeof (buf), " hclk_clk: %u", freq); | ||
107 | lcd_puts(0, line++, buf); | ||
108 | |||
109 | snprintf(buf, sizeof (buf), " ipg_clk: %u", | ||
110 | freq / (unsigned)(((regval >> 6) & 0x3) + 1)); | ||
111 | lcd_puts(0, line++, buf); | ||
112 | |||
113 | snprintf(buf, sizeof (buf), " nfc_clk: %u", | ||
114 | freq / (unsigned)(((regval >> 8) & 0x7) + 1)); | ||
115 | lcd_puts(0, line++, buf); | ||
116 | |||
117 | line++; | ||
118 | |||
119 | /* Serial clock domain */ | ||
120 | snprintf(buf, sizeof (buf), "SPCTL: %08lX", spctl); | ||
121 | lcd_puts(0, line++, buf); | ||
122 | snprintf(buf, sizeof (buf), " spl_dpdgck_clk: %u", ser_pllfreq); | ||
123 | lcd_puts(0, line++, buf); | ||
124 | |||
125 | line++; | ||
126 | |||
127 | /* USB clock domain */ | ||
128 | snprintf(buf, sizeof (buf), "UPCTL: %08lX", upctl); | ||
129 | lcd_puts(0, line++, buf); | ||
130 | |||
131 | snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq); | ||
132 | lcd_puts(0, line++, buf); line++; | ||
133 | |||
134 | regval = CLKCTL_PDR1; | ||
135 | snprintf(buf, sizeof (buf), " PDR1: %08lX", regval); | ||
136 | lcd_puts(0, line++, buf); | ||
137 | |||
138 | freq = usb_pllfreq / | ||
139 | ((((regval >> 30) & 0x3) + 1) * (((regval >> 27) & 0x7) + 1)); | ||
140 | snprintf(buf, sizeof (buf), " usb_clk: %u", freq); | ||
141 | lcd_puts(0, line++, buf); | ||
142 | |||
143 | freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1); | ||
144 | snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq); | ||
145 | lcd_puts(0, line++, buf); | ||
146 | |||
147 | lcd_update(); | ||
148 | |||
149 | if (button_get(true) == (DEBUG_CANCEL|BUTTON_REL)) | ||
150 | return false; | ||
151 | } | ||
33 | } | 152 | } |
34 | 153 | ||
35 | bool __dbg_ports(void) | 154 | bool __dbg_ports(void) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c index e37f6bfbe2..9ac96fd801 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c | |||
@@ -7,7 +7,7 @@ | |||
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2006 by Michael Sevakis | 10 | * Copyright (C) 2008 by Michael Sevakis |
11 | * | 11 | * |
12 | * All files in this archive are subject to the GNU General Public License. | 12 | * All files in this archive are subject to the GNU General Public License. |
13 | * See the file COPYING in the source tree root for full license agreement. | 13 | * See the file COPYING in the source tree root for full license agreement. |
@@ -19,69 +19,256 @@ | |||
19 | #include <stdlib.h> | 19 | #include <stdlib.h> |
20 | #include "system.h" | 20 | #include "system.h" |
21 | #include "kernel.h" | 21 | #include "kernel.h" |
22 | #include "logf.h" | ||
23 | #include "audio.h" | 22 | #include "audio.h" |
24 | #include "sound.h" | 23 | #include "sound.h" |
25 | #include "file.h" | 24 | #include "avic-imx31.h" |
26 | #include "mmu-imx31.h" | 25 | #include "clkctl-imx31.h" |
27 | 26 | ||
28 | #if 0 | 27 | /* This isn't DMA-based at the moment and is handled like Portal Player but |
29 | static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */ | 28 | * will suffice for starters. */ |
30 | #endif | 29 | |
30 | struct dma_data | ||
31 | { | ||
32 | uint16_t *p; | ||
33 | size_t size; | ||
34 | int locked; | ||
35 | int state; | ||
36 | }; | ||
37 | |||
38 | static unsigned long pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */ | ||
39 | |||
40 | static struct dma_data dma_play_data = | ||
41 | { | ||
42 | /* Initialize to a locked, stopped state */ | ||
43 | .p = NULL, | ||
44 | .size = 0, | ||
45 | .locked = 0, | ||
46 | .state = 0 | ||
47 | }; | ||
31 | 48 | ||
32 | void pcm_play_lock(void) | 49 | void pcm_play_lock(void) |
33 | { | 50 | { |
51 | if (++dma_play_data.locked == 1) | ||
52 | { | ||
53 | /* Atomically disable transmit interrupt */ | ||
54 | imx31_regmod32(&SSI_SIER1, 0, SSI_SIER_TIE); | ||
55 | } | ||
34 | } | 56 | } |
35 | 57 | ||
36 | void pcm_play_unlock(void) | 58 | void pcm_play_unlock(void) |
37 | { | 59 | { |
60 | if (--dma_play_data.locked == 0 && dma_play_data.state != 0) | ||
61 | { | ||
62 | /* Atomically enable transmit interrupt */ | ||
63 | imx31_regmod32(&SSI_SIER1, SSI_SIER_TIE, SSI_SIER_TIE); | ||
64 | } | ||
38 | } | 65 | } |
39 | 66 | ||
40 | #if 0 | ||
41 | static void _pcm_apply_settings(void) | 67 | static void _pcm_apply_settings(void) |
42 | { | 68 | { |
69 | if (pcm_freq != pcm_curr_sampr) | ||
70 | { | ||
71 | pcm_curr_sampr = pcm_freq; | ||
72 | // TODO: audiohw_set_frequency(sr_ctrl); | ||
73 | } | ||
74 | } | ||
75 | |||
76 | static void __attribute__((interrupt("IRQ"))) SSI1_HANDLER(void) | ||
77 | { | ||
78 | register pcm_more_callback_type get_more; | ||
79 | |||
80 | do | ||
81 | { | ||
82 | while (dma_play_data.size > 0) | ||
83 | { | ||
84 | if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6) | ||
85 | { | ||
86 | return; | ||
87 | } | ||
88 | SSI_STX0_1 = *dma_play_data.p++; | ||
89 | SSI_STX0_1 = *dma_play_data.p++; | ||
90 | dma_play_data.size -= 4; | ||
91 | } | ||
92 | |||
93 | /* p is empty, get some more data */ | ||
94 | get_more = pcm_callback_for_more; | ||
95 | |||
96 | if (get_more) | ||
97 | { | ||
98 | get_more((unsigned char **)&dma_play_data.p, | ||
99 | &dma_play_data.size); | ||
100 | } | ||
101 | } | ||
102 | while (dma_play_data.size > 0); | ||
103 | |||
104 | /* No more data, so disable the FIFO/interrupt */ | ||
105 | pcm_play_dma_stop(); | ||
106 | pcm_play_dma_stopped_callback(); | ||
43 | } | 107 | } |
44 | #endif | ||
45 | 108 | ||
46 | void pcm_apply_settings(void) | 109 | void pcm_apply_settings(void) |
47 | { | 110 | { |
111 | int oldstatus = disable_fiq_save(); | ||
112 | |||
113 | _pcm_apply_settings(); | ||
114 | |||
115 | restore_fiq(oldstatus); | ||
48 | } | 116 | } |
49 | 117 | ||
50 | void pcm_play_dma_init(void) | 118 | void pcm_play_dma_init(void) |
51 | { | 119 | { |
120 | imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL); | ||
121 | imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL); | ||
122 | |||
123 | /* Reset & disable SSIs */ | ||
124 | SSI_SCR2 &= ~SSI_SCR_SSIEN; | ||
125 | SSI_SCR1 &= ~SSI_SCR_SSIEN; | ||
126 | |||
127 | SSI_SIER1 = SSI_SIER_TFE0; | ||
128 | SSI_SIER2 = 0; | ||
129 | |||
130 | /* Set up audio mux */ | ||
131 | |||
132 | /* Port 1 (internally connected to SSI1) | ||
133 | * All clocking is output sourced from port 4 */ | ||
134 | AUDMUX_PTCR1 = AUDMUX_PTCR_TFS_DIR | AUDMUX_PTCR_TFSEL_PORT4 | | ||
135 | AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT4 | | ||
136 | AUDMUX_PTCR_RFSDIR | AUDMUX_PTCR_RFSSEL_PORT4 | | ||
137 | AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4 | | ||
138 | AUDMUX_PTCR_SYN; | ||
139 | |||
140 | /* Receive data from port 4 */ | ||
141 | AUDMUX_PDCR1 = AUDMUX_PDCR_RXDSEL_PORT4; | ||
142 | /* All clock lines are inputs sourced from the master mode codec and | ||
143 | * sent back to SSI1 through port 1 */ | ||
144 | AUDMUX_PTCR4 = AUDMUX_PTCR_SYN; | ||
145 | |||
146 | /* Receive data from port 1 */ | ||
147 | AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT1; | ||
148 | |||
149 | /* Port 2 (internally connected to SSI2) routes clocking to port 5 to | ||
150 | * provide MCLK to the codec */ | ||
151 | /* All port 2 clocks are inputs taken from SSI2 */ | ||
152 | AUDMUX_PTCR2 = 0; | ||
153 | AUDMUX_PDCR2 = 0; | ||
154 | /* Port 5 outputs TCLK sourced from port 2 */ | ||
155 | AUDMUX_PTCR5 = AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT2; | ||
156 | AUDMUX_PDCR5 = 0; | ||
157 | |||
158 | /* Setup SSIs */ | ||
159 | |||
160 | /* SSI1 - interface for all I2S data */ | ||
161 | SSI_SCR1 = SSI_SCR_SYN | SSI_SCR_I2S_MODE_SLAVE; | ||
162 | SSI_STCR1 = SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI | | ||
163 | SSI_STCR_TEFS | SSI_STCR_TFEN0; | ||
164 | |||
165 | /* 16 bits per word, 2 words per frame */ | ||
166 | SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | ||
167 | SSI_STRCCR_PMw(4-1); | ||
168 | |||
169 | SSI_STMSK1 = 0; | ||
170 | |||
171 | /* Receive */ | ||
172 | SSI_SRCR1 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI | | ||
173 | SSI_SRCR_REFS | SSI_SRCR_RFEN0; | ||
174 | |||
175 | /* 16 bits per word, 2 words per frame */ | ||
176 | SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | ||
177 | SSI_STRCCR_PMw(4-1); | ||
178 | |||
179 | /* Receive high watermark - 6 samples in FIFO | ||
180 | * Transmit low watermark - 2 samples in FIFO */ | ||
181 | SSI_SFCSR1 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_TFWM1w(1) | | ||
182 | SSI_SFCSR_RFWM0w(6) | SSI_SFCSR_TFWM0w(2); | ||
183 | |||
184 | SSI_SRMSK1 = 0; | ||
185 | |||
186 | /* SSI2 - provides MCLK only */ | ||
187 | SSI_SCR2 = 0; | ||
188 | SSI_SRCR2 = 0; | ||
189 | SSI_STCR2 = SSI_STCR_TXDIR; | ||
190 | SSI_STCCR2 = SSI_STRCCR_PMw(0); | ||
191 | |||
192 | /* Enable SSIs */ | ||
193 | SSI_SCR2 |= SSI_SCR_SSIEN; | ||
194 | |||
52 | audiohw_init(); | 195 | audiohw_init(); |
53 | } | 196 | } |
54 | 197 | ||
55 | void pcm_postinit(void) | 198 | void pcm_postinit(void) |
56 | { | 199 | { |
57 | audiohw_postinit(); | 200 | audiohw_postinit(); |
201 | avic_enable_int(SSI1, IRQ, 8, SSI1_HANDLER); | ||
58 | } | 202 | } |
59 | 203 | ||
60 | #if 0 | ||
61 | /* Connect the DMA and start filling the FIFO */ | ||
62 | static void play_start_pcm(void) | 204 | static void play_start_pcm(void) |
63 | { | 205 | { |
206 | /* Stop transmission (if in progress) */ | ||
207 | SSI_SCR1 &= ~SSI_SCR_TE; | ||
208 | |||
209 | /* Apply new settings */ | ||
210 | _pcm_apply_settings(); | ||
211 | |||
212 | /* Enable interrupt on unlock */ | ||
213 | dma_play_data.state = 1; | ||
214 | |||
215 | /* Fill the FIFO or start when data is used up */ | ||
216 | while (1) | ||
217 | { | ||
218 | if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6 || dma_play_data.size == 0) | ||
219 | { | ||
220 | SSI_SCR1 |= (SSI_SCR_TE | SSI_SCR_SSIEN); /* Start transmitting */ | ||
221 | return; | ||
222 | } | ||
223 | |||
224 | SSI_STX0_1 = *dma_play_data.p++; | ||
225 | SSI_STX0_1 = *dma_play_data.p++; | ||
226 | dma_play_data.size -= 4; | ||
227 | } | ||
64 | } | 228 | } |
65 | 229 | ||
66 | /* Disconnect the DMA and wait for the FIFO to clear */ | ||
67 | static void play_stop_pcm(void) | 230 | static void play_stop_pcm(void) |
68 | { | 231 | { |
232 | /* Disable interrupt */ | ||
233 | SSI_SIER1 &= ~SSI_SIER_TIE; | ||
234 | |||
235 | /* Wait for FIFO to empty */ | ||
236 | while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0); | ||
237 | |||
238 | /* Disable transmission */ | ||
239 | SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN); | ||
240 | |||
241 | /* Do not enable interrupt on unlock */ | ||
242 | dma_play_data.state = 0; | ||
69 | } | 243 | } |
70 | #endif | ||
71 | 244 | ||
72 | void pcm_play_dma_start(const void *addr, size_t size) | 245 | void pcm_play_dma_start(const void *addr, size_t size) |
73 | { | 246 | { |
74 | (void)addr; | 247 | dma_play_data.p = (void *)(((uintptr_t)addr + 3) & ~3); |
75 | (void)size; | 248 | dma_play_data.size = (size & ~3); |
249 | |||
250 | play_start_pcm(); | ||
76 | } | 251 | } |
77 | 252 | ||
78 | void pcm_play_dma_stop(void) | 253 | void pcm_play_dma_stop(void) |
79 | { | 254 | { |
255 | play_stop_pcm(); | ||
256 | dma_play_data.size = 0; | ||
80 | } | 257 | } |
81 | 258 | ||
82 | void pcm_play_dma_pause(bool pause) | 259 | void pcm_play_dma_pause(bool pause) |
83 | { | 260 | { |
84 | (void)pause; | 261 | if (pause) |
262 | { | ||
263 | play_stop_pcm(); | ||
264 | } | ||
265 | else | ||
266 | { | ||
267 | uint32_t addr = (uint32_t)dma_play_data.p; | ||
268 | dma_play_data.p = (void *)((addr + 2) & ~3); | ||
269 | dma_play_data.size &= ~3; | ||
270 | play_start_pcm(); | ||
271 | } | ||
85 | } | 272 | } |
86 | 273 | ||
87 | /* Set the pcm frequency hardware will use when play is next started or | 274 | /* Set the pcm frequency hardware will use when play is next started or |
@@ -89,20 +276,23 @@ void pcm_play_dma_pause(bool pause) | |||
89 | hardware here but simply cache it. */ | 276 | hardware here but simply cache it. */ |
90 | void pcm_set_frequency(unsigned int frequency) | 277 | void pcm_set_frequency(unsigned int frequency) |
91 | { | 278 | { |
279 | /* TODO */ | ||
92 | (void)frequency; | 280 | (void)frequency; |
93 | } | 281 | } |
94 | 282 | ||
95 | /* Return the number of bytes waiting - full L-R sample pairs only */ | 283 | /* Return the number of bytes waiting - full L-R sample pairs only */ |
96 | size_t pcm_get_bytes_waiting(void) | 284 | size_t pcm_get_bytes_waiting(void) |
97 | { | 285 | { |
98 | return 0; | 286 | return dma_play_data.size & ~3; |
99 | } | 287 | } |
100 | 288 | ||
101 | /* Return a pointer to the samples and the number of them in *count */ | 289 | /* Return a pointer to the samples and the number of them in *count */ |
102 | const void * pcm_play_dma_get_peak_buffer(int *count) | 290 | const void * pcm_play_dma_get_peak_buffer(int *count) |
103 | { | 291 | { |
104 | (void)count; | 292 | uint32_t addr = (uint32_t)dma_play_data.p; |
105 | return NULL; | 293 | size_t cnt = dma_play_data.size; |
294 | *count = cnt >> 2; | ||
295 | return (void *)((addr + 2) & ~3); | ||
106 | } | 296 | } |
107 | 297 | ||
108 | /* Any recording functionality should be implemented similarly */ | 298 | /* Any recording functionality should be implemented similarly */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c index da5026a292..ca82a18fbd 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c | |||
@@ -27,6 +27,16 @@ void system_init(void) | |||
27 | gpio_init(); | 27 | gpio_init(); |
28 | } | 28 | } |
29 | 29 | ||
30 | void imx31_regmod32(volatile uint32_t *reg_p, uint32_t mask, uint32_t value) | ||
31 | { | ||
32 | value &= mask; | ||
33 | mask = ~mask; | ||
34 | |||
35 | int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
36 | *reg_p = (*reg_p & mask) | value; | ||
37 | restore_interrupt(oldlevel); | ||
38 | } | ||
39 | |||
30 | #ifdef BOOTLOADER | 40 | #ifdef BOOTLOADER |
31 | void system_prepare_fw_start(void) | 41 | void system_prepare_fw_start(void) |
32 | { | 42 | { |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index 241f215dc1..766de7328f 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -24,16 +24,21 @@ | |||
24 | 24 | ||
25 | #define CPUFREQ_NORMAL 532000000 | 25 | #define CPUFREQ_NORMAL 532000000 |
26 | 26 | ||
27 | #if 0 | ||
27 | static inline void udelay(unsigned int usecs) | 28 | static inline void udelay(unsigned int usecs) |
28 | { | 29 | { |
29 | volatile signed int stop = EPITCNT1 - usecs; | 30 | volatile signed int stop = EPITCNT1 - usecs; |
30 | while ((signed int)EPITCNT1 > stop); | 31 | while ((signed int)EPITCNT1 > stop); |
31 | } | 32 | } |
33 | #endif | ||
32 | 34 | ||
33 | void system_prepare_fw_start(void); | 35 | void system_prepare_fw_start(void); |
34 | void tick_stop(void); | 36 | void tick_stop(void); |
35 | void kernel_device_init(void); | 37 | void kernel_device_init(void); |
36 | 38 | ||
39 | void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, | ||
40 | uint32_t mask); | ||
41 | |||
37 | #define KDEV_INIT | 42 | #define KDEV_INIT |
38 | 43 | ||
39 | #define HAVE_INVALIDATE_ICACHE | 44 | #define HAVE_INVALIDATE_ICACHE |
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c index 235ae54bad..c8a04ce20e 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | |||
@@ -7,14 +7,9 @@ | |||
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Gigabeat S specific code for the WM8978 codec | 10 | * Gigabeat S specific code for the WM8978 codec |
11 | * | 11 | * |
12 | * Based on code from the ipodlinux project - http://ipodlinux.org/ | 12 | * Copyright (C) 2008 Michael Sevakis |
13 | * Adapted for Rockbox in December 2005 | ||
14 | * | ||
15 | * Original file: linux/arch/armnommu/mach-ipod/audio.c | ||
16 | * | ||
17 | * Copyright (c) 2003-2005 Bernard Leach (leachbj@bouncycastle.org) | ||
18 | * | 13 | * |
19 | * All files in this archive are subject to the GNU General Public License. | 14 | * All files in this archive are subject to the GNU General Public License. |
20 | * See the file COPYING in the source tree root for full license agreement. | 15 | * See the file COPYING in the source tree root for full license agreement. |
@@ -23,7 +18,8 @@ | |||
23 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
24 | * | 19 | * |
25 | ****************************************************************************/ | 20 | ****************************************************************************/ |
26 | #include "cpu.h" | 21 | #include "config.h" |
22 | #include "system.h" | ||
27 | #include "kernel.h" | 23 | #include "kernel.h" |
28 | #include "sound.h" | 24 | #include "sound.h" |
29 | #include "i2c-imx31.h" | 25 | #include "i2c-imx31.h" |
@@ -37,15 +33,33 @@ static struct i2c_node wm8978_i2c_node = | |||
37 | .ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */ | 33 | .ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */ |
38 | /* Just hard-code for now - scaling may require | 34 | /* Just hard-code for now - scaling may require |
39 | * updating */ | 35 | * updating */ |
40 | .addr = WM8978_I2C_ADDR, | 36 | .addr = WMC_I2C_ADDR, |
41 | }; | 37 | }; |
42 | 38 | ||
43 | void audiohw_init(void) | 39 | void audiohw_init(void) |
44 | { | 40 | { |
41 | /* USB PLL = 338.688MHz, /30 = 11.2896MHz = 256Fs */ | ||
42 | imx31_regmod32(&CLKCTL_PDR1, PDR1_SSI1_PODF | PDR1_SSI2_PODF, | ||
43 | PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1)); | ||
44 | imx31_regmod32(&CLKCTL_PDR1, PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF, | ||
45 | PDR1_SSI1_PRE_PODFw(4-1) | PDR1_SSI2_PRE_PODFw(1-1)); | ||
45 | i2c_enable_node(&wm8978_i2c_node, true); | 46 | i2c_enable_node(&wm8978_i2c_node, true); |
46 | GPIO3_DR |= (1 << 21); /* Turn on analogue LDO */ | 47 | |
47 | sleep(HZ/10); /* Wait for things to stabilize */ | ||
48 | audiohw_preinit(); | 48 | audiohw_preinit(); |
49 | |||
50 | GPIO3_DR |= (1 << 21); /* Turn on analogue LDO */ | ||
51 | } | ||
52 | |||
53 | void audiohw_enable_headphone_jack(bool enable) | ||
54 | { | ||
55 | if (enable) | ||
56 | { | ||
57 | GPIO3_DR |= (1 << 22); /* Turn on headphone jack output */ | ||
58 | } | ||
59 | else | ||
60 | { | ||
61 | GPIO3_DR &= ~(1 << 22); /* Turn off headphone jack output */ | ||
62 | } | ||
49 | } | 63 | } |
50 | 64 | ||
51 | void wmcodec_write(int reg, int data) | 65 | void wmcodec_write(int reg, int data) |