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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#ifndef ISP1583_H
20#define ISP1583_H
21
22#ifndef ISP1583_H_OVERRIDE
23/* Initialization registers */
24#define ISP1583_INIT_ADDRESS (*((volatile unsigned char*)(ISP1583_IOBASE+0x0)))
25#define ISP1583_INIT_MODE (*((volatile unsigned short*)(ISP1583_IOBASE+0xC)))
26#define ISP1583_INIT_INTCONF (*((volatile unsigned char*)(ISP1583_IOBASE+0x10)))
27#define ISP1583_INIT_OTG (*((volatile unsigned char*)(ISP1583_IOBASE+0x12)))
28#define ISP1583_INIT_INTEN_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x14)))
29#define ISP1583_INIT_INTEN_B
30#define ISP1583_INIT_INTEN_READ ISP1583_INIT_INTEN_A
31/* Data Flow registers */
32#define ISP1583_DFLOW_EPINDEX (*((volatile unsigned char*)(ISP1583_IOBASE+0xC2)))
33#define ISP1583_DFLOW_CTRLFUN (*((volatile unsigned char*)(ISP1583_IOBASE+0x28)))
34#define ISP1583_DFLOW_DATA (*((volatile unsigned short*)(ISP1583_IOBASE+0x20)))
35#define ISP1583_DFLOW_BUFLEN (*((volatile unsigned short*)(ISP1583_IOBASE+0x1C)))
36#define ISP1583_DFLOW_BUFSTAT (*((volatile unsigned char*)(ISP1583_IOBASE+0x1E)))
37#define ISP1583_DFLOW_MAXPKSZ (*((volatile unsigned short*)(ISP1583_IOBASE+0x04)))
38#define ISP1583_DFLOW_EPTYPE (*((volatile unsigned short*)(ISP1583_IOBASE+0x08)))
39/* DMA registers */
40#define ISP1583_DMA_ENDPOINT (*((volatile unsigned char*)(ISP1583_IOBASE+0x58)))
41/* General registers */
42#define ISP1583_GEN_INT_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x18)))
43#define ISP1583_GEN_INT_B
44#define ISP1583_GEN_INT_READ ISP1583_GEN_INT_A
45#define ISP1583_GEN_CHIPID (*((volatile unsigned long*)(ISP1583_IOBASE+0x70))) /* Size=3 bytes */
46#define ISP1583_GEN_FRAMEN0 (*((volatile unsigned short*)(ISP1583_IOBASE+0x74)))
47#define ISP1583_GEN_SCRATCH (*((volatile unsigned short*)(ISP1583_IOBASE+0x78)))
48#define ISP1583_GEN_UNLCKDEV (*((volatile unsigned short*)(ISP1583_IOBASE+0x7C)))
49#define ISP1583_GEN_TSTMOD (*((volatile unsigned char*)(ISP1583_IOBASE+0x84)))
50
51#define set_int_value(a,b,value) a = value;
52#endif
53
54#define ISP1583_UNLOCK_CODE (unsigned short)0xAA37
55
56/* Initialization registers' bits */
57
58/* Initialization OTG register bits */
59#define INIT_OTG_BSESS_VALID (1 << 4)
60
61/* Initialization Mode register bits */
62#define INIT_MODE_TEST2 (1 << 15)
63#define INIT_MODE_TEST1 (1 << 14)
64#define INIT_MODE_TEST0 (1 << 13)
65#define INIT_MODE_DMA_CLKON (1 << 9)
66#define INIT_MODE_VBUSSTAT (1 << 8)
67#define INIT_MODE_CLKAON (1 << 7)
68#define INIT_MODE_SNDRSU (1 << 6)
69#define INIT_MODE_GOSUSP (1 << 5)
70#define INIT_MODE_SFRESET (1 << 4)
71#define INIT_MODE_GLINTENA (1 << 3)
72#define INIT_MODE_WKUPCS (1 << 2)
73#define INIT_MODE_PWRON (1 << 1)
74#define INIT_MODE_SOFTCT (1 << 0)
75
76/* Initialization Interrupt Enable register bits */
77#define INIT_INTEN_IEP7TX (1 << 25)
78#define INIT_INTEN_IEP7RX (1 << 24)
79#define INIT_INTEN_IEP6TX (1 << 23)
80#define INIT_INTEN_IEP6RX (1 << 22)
81#define INIT_INTEN_IEP5TX (1 << 21)
82#define INIT_INTEN_IEP5RX (1 << 20)
83#define INIT_INTEN_IEP4TX (1 << 19)
84#define INIT_INTEN_IEP4RX (1 << 18)
85#define INIT_INTEN_IEP3TX (1 << 17)
86#define INIT_INTEN_IEP3RX (1 << 16)
87#define INIT_INTEN_IEP2TX (1 << 15)
88#define INIT_INTEN_IEP2RX (1 << 14)
89#define INIT_INTEN_IEP1TX (1 << 13)
90#define INIT_INTEN_IEP1RX (1 << 12)
91#define INIT_INTEN_IEP0TX (1 << 11)
92#define INIT_INTEN_IEP0RX (1 << 10)
93#define INIT_INTEN_IEP0SETUP (1 << 8)
94#define INIT_INTEN_IEVBUS (1 << 7)
95#define INIT_INTEN_IEDMA (1 << 6)
96#define INIT_INTEN_IEHS_STA (1 << 5)
97#define INIT_INTEN_IERESM (1 << 4)
98#define INIT_INTEN_IESUSP (1 << 3)
99#define INIT_INTEN_IEPSOF (1 << 2)
100#define INIT_INTEN_IESOF (1 << 1)
101#define INIT_INTEN_IEBRST (1 << 0)
102
103/* Initialization Interrupt Configuration register bits */
104#define INIT_INTCONF_INTLVL (1 << 1)
105#define INIT_INTCONF_INTPOL (1 << 0)
106
107/* Initialization Address register bits */
108#define INIT_ADDRESS_DEVEN (1 << 7)
109
110/* Data Flow registers' bits */
111
112/* Data Flow Endpoint Index register bits */
113#define DFLOW_EPINDEX_EP0SETUP (1 << 5)
114
115/* Data Flow Control Function register bits */
116#define DFLOW_CTRLFUN_CLBUF (1 << 4)
117#define DFLOW_CTRLFUN_VENDP (1 << 3)
118#define DFLOW_CTRLFUN_DSEN (1 << 2)
119#define DFLOW_CTRLFUN_STATUS (1 << 1)
120#define DFLOW_CTRLFUN_STALL (1 << 0)
121
122/* Data Flow Endpoint Type register bits */
123#define DFLOW_EPTYPE_NOEMPKT (1 << 4)
124#define DFLOW_EPTYPE_ENABLE (1 << 3)
125#define DFLOW_EPTYPE_DBLBUF (1 << 2)
126
127/* General registers' bits */
128
129/* General Test Mode register bits */
130#define GEN_TSTMOD_FORCEHS (1 << 7)
131#define GEN_TSTMOD_FORCEFS (1 << 4)
132#define GEN_TSTMOD_PRBS (1 << 3)
133#define GEN_TSTMOD_KSTATE (1 << 2)
134#define GEN_TSTMOD_JSTATE (1 << 1)
135#define GEN_TSTMOD_SE0_NAK (1 << 0)
136
137/* Interrupts */
138#define INT_IEP7TX (1 << 25)
139#define INT_IEP7RX (1 << 24)
140#define INT_IEP6TX (1 << 23)
141#define INT_IEP6RX (1 << 22)
142#define INT_IEP5TX (1 << 21)
143#define INT_IEP5RX (1 << 20)
144#define INT_IEP4TX (1 << 19)
145#define INT_IEP4RX (1 << 18)
146#define INT_IEP3TX (1 << 17)
147#define INT_IEP3RX (1 << 16)
148#define INT_IEP2TX (1 << 15)
149#define INT_IEP2RX (1 << 14)
150#define INT_IEP1TX (1 << 13)
151#define INT_IEP1RX (1 << 12)
152#define INT_IEP0TX (1 << 11)
153#define INT_IEP0RX (1 << 10)
154#define INT_IEP0SETUP (1 << 8)
155#define INT_IEVBUS (1 << 7)
156#define INT_IEDMA (1 << 6)
157#define INT_IEHS_STA (1 << 5)
158#define INT_IERESM (1 << 4)
159#define INT_IESUSP (1 << 3)
160#define INT_IEPSOF (1 << 2)
161#define INT_IESOF (1 << 1)
162#define INT_IEBRST (1 << 0)
163
164#define INT_EP_MASK ( INT_IEP0RX | INT_IEP0TX | INT_IEP1RX | INT_IEP1TX | INT_IEP2RX | INT_IEP2TX | INT_IEP3RX | INT_IEP3TX | INT_IEP4RX | INT_IEP4TX | INT_IEP5RX | INT_IEP5TX | INT_IEP6RX | INT_IEP6TX | INT_IEP7RX | INT_IEP7TX )
165
166#define STANDARD_INTEN ( INIT_INTEN_IEBRST | INIT_INTEN_IEHS_STA | INT_IESUSP | INT_IERESM | INIT_INTEN_IEVBUS | INIT_INTEN_IEP0SETUP | INIT_INTEN_IEP0RX | INIT_INTEN_IEP0TX )
167#define STANDARD_INIT_MODE ( INIT_MODE_CLKAON | INIT_MODE_GLINTENA )
168
169bool usb_drv_powered(void);
170void usb_drv_init(void);
171int usb_drv_port_speed(void);
172void usb_drv_exit(void);
173void usb_drv_stall(int endpoint, bool stall, bool in);
174bool usb_drv_stalled(int endpoint, bool in);
175int usb_drv_recv(int ep, void* ptr, int length);
176int usb_drv_send_nonblocking(int ep, void* ptr, int length);
177int usb_drv_send(int endpoint, void* ptr, int length);
178void usb_drv_reset_endpoint(int ep, bool send);
179void usb_drv_wait(int ep, bool send);
180void usb_drv_cancel_all_transfers(void);
181void usb_drv_set_address(int address);
182void usb_drv_set_test_mode(int mode);
183void usb_drv_int(void); /* Method for handling interrupts, must be called from usb-<target>.c */
184
185#endif
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