diff options
-rw-r--r-- | firmware/target/coldfire/iaudio/m5/lcd-as-m5.S | 72 | ||||
-rw-r--r-- | firmware/target/coldfire/iriver/h100/lcd-as-h100.S | 70 |
2 files changed, 81 insertions, 61 deletions
diff --git a/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S b/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S index 0ec98e4589..0ec4f4b032 100644 --- a/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S +++ b/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S | |||
@@ -87,10 +87,14 @@ lcd_write_data: | |||
87 | .global lcd_grey_data | 87 | .global lcd_grey_data |
88 | .type lcd_grey_data,@function | 88 | .type lcd_grey_data,@function |
89 | 89 | ||
90 | /* The main loop assumes the buffers are in SDRAM. Otherwise the LCD | ||
91 | * controller timing won't be met at 124 MHz and graphical glitches | ||
92 | * will occur. */ | ||
93 | |||
90 | lcd_grey_data: | 94 | lcd_grey_data: |
91 | lea.l (-9*4, %sp), %sp | 95 | lea.l (-10*4, %sp), %sp |
92 | movem.l %d2-%d5/%a2-%a6, (%sp) /* free some registers */ | 96 | movem.l %d2-%d6/%a2-%a6, (%sp) /* free some registers */ |
93 | movem.l (9*4+4, %sp), %a0-%a2 /* values, phases, length */ | 97 | movem.l (10*4+4, %sp), %a0-%a2 /* values, phases, length */ |
94 | lea.l (%a1, %a2.l*4), %a2 /* end address */ | 98 | lea.l (%a1, %a2.l*4), %a2 /* end address */ |
95 | lea 0xf0008002, %a3 /* LCD data port */ | 99 | lea 0xf0008002, %a3 /* LCD data port */ |
96 | 100 | ||
@@ -128,9 +132,9 @@ lcd_grey_data: | |||
128 | bhi.s .g_hloop | 132 | bhi.s .g_hloop |
129 | 133 | ||
130 | .g_lloop: | 134 | .g_lloop: |
131 | movem.l (%a1), %d2-%d5 | 135 | movem.l (%a1), %d2-%d5 /* fetch 4 blocks of 4 pixel phases each */ |
132 | 136 | ||
133 | bclr.l #31, %d2 | 137 | bclr.l #31, %d2 /* calculate first pixel block */ |
134 | seq.b %d0 | 138 | seq.b %d0 |
135 | lsl.l #2, %d0 | 139 | lsl.l #2, %d0 |
136 | bclr.l #23, %d2 | 140 | bclr.l #23, %d2 |
@@ -142,23 +146,23 @@ lcd_grey_data: | |||
142 | bclr.l #7, %d2 | 146 | bclr.l #7, %d2 |
143 | seq.b %d0 | 147 | seq.b %d0 |
144 | lsr.l #6, %d0 | 148 | lsr.l #6, %d0 |
145 | move.w %d0, (%a3) | ||
146 | 149 | ||
147 | bclr.l #31, %d3 | 150 | move.w %d0, (%a3) /* write first block to LCD */ |
148 | seq.b %d0 | 151 | |
149 | lsl.l #2, %d0 | 152 | bclr.l #31, %d3 /* calculate second pixel block */ |
153 | seq.b %d6 | ||
154 | lsl.l #2, %d6 | ||
150 | bclr.l #23, %d3 | 155 | bclr.l #23, %d3 |
151 | seq.b %d0 | 156 | seq.b %d6 |
152 | lsl.l #2, %d0 | 157 | lsl.l #2, %d6 |
153 | bclr.l #15, %d3 | 158 | bclr.l #15, %d3 |
154 | seq.b %d0 | 159 | seq.b %d6 |
155 | lsl.l #2, %d0 | 160 | lsl.l #2, %d6 |
156 | bclr.l #7, %d3 | 161 | bclr.l #7, %d3 |
157 | seq.b %d0 | 162 | seq.b %d6 |
158 | lsr.l #6, %d0 | 163 | lsr.l #6, %d6 |
159 | move.w %d0, (%a3) | 164 | |
160 | 165 | bclr.l #31, %d4 /* calculate third pixel block */ | |
161 | bclr.l #31, %d4 | ||
162 | seq.b %d0 | 166 | seq.b %d0 |
163 | lsl.l #2, %d0 | 167 | lsl.l #2, %d0 |
164 | bclr.l #23, %d4 | 168 | bclr.l #23, %d4 |
@@ -170,9 +174,15 @@ lcd_grey_data: | |||
170 | bclr.l #7, %d4 | 174 | bclr.l #7, %d4 |
171 | seq.b %d0 | 175 | seq.b %d0 |
172 | lsr.l #6, %d0 | 176 | lsr.l #6, %d0 |
173 | move.w %d0, (%a3) | 177 | |
174 | 178 | move.w %d6, (%a3) /* write second block to LCD */ | |
175 | bclr.l #31, %d5 | 179 | |
180 | movem.l (%a0), %d6/%a4-%a6 /* fetch 4 blocks of 4 pixel values each */ | ||
181 | lea.l (16, %a0), %a0 | ||
182 | |||
183 | move.w %d0, (%a3) /* write third block to LCD */ | ||
184 | |||
185 | bclr.l #31, %d5 /* calculate fourth pixel block */ | ||
176 | seq.b %d0 | 186 | seq.b %d0 |
177 | lsl.l #2, %d0 | 187 | lsl.l #2, %d0 |
178 | bclr.l #23, %d5 | 188 | bclr.l #23, %d5 |
@@ -184,20 +194,20 @@ lcd_grey_data: | |||
184 | bclr.l #7, %d5 | 194 | bclr.l #7, %d5 |
185 | seq.b %d0 | 195 | seq.b %d0 |
186 | lsr.l #6, %d0 | 196 | lsr.l #6, %d0 |
187 | move.w %d0, (%a3) | 197 | |
188 | 198 | add.l %d6, %d2 /* calculate 4*4 new pixel phases */ | |
189 | movem.l (%a0), %d0/%a4-%a6 | 199 | add.l %a4, %d3 /* (packed addition) */ |
190 | lea.l (16, %a0), %a0 | ||
191 | add.l %d0, %d2 | ||
192 | add.l %a4, %d3 | ||
193 | add.l %a5, %d4 | 200 | add.l %a5, %d4 |
194 | add.l %a6, %d5 | 201 | add.l %a6, %d5 |
195 | movem.l %d2-%d5, (%a1) | 202 | |
203 | movem.l %d2-%d5, (%a1) /* store 4*4 new pixel phases */ | ||
196 | lea.l (16, %a1), %a1 | 204 | lea.l (16, %a1), %a1 |
197 | 205 | ||
206 | move.w %d0, (%a3) /* write fourth block to LCD */ | ||
207 | |||
198 | cmp.l %a1, %d1 /* go up to last line bound */ | 208 | cmp.l %a1, %d1 /* go up to last line bound */ |
199 | bhi.w .g_lloop | 209 | bhi.w .g_lloop |
200 | 210 | ||
201 | cmp.l %a1, %a2 | 211 | cmp.l %a1, %a2 |
202 | bls.s .g_no_tail | 212 | bls.s .g_no_tail |
203 | 213 | ||
@@ -225,8 +235,8 @@ lcd_grey_data: | |||
225 | bhi.s .g_tloop | 235 | bhi.s .g_tloop |
226 | 236 | ||
227 | .g_no_tail: | 237 | .g_no_tail: |
228 | movem.l (%sp), %d2-%d5/%a2-%a6 /* restore registers */ | 238 | movem.l (%sp), %d2-%d6/%a2-%a6 /* restore registers */ |
229 | lea.l (9*4, %sp), %sp | 239 | lea.l (10*4, %sp), %sp |
230 | rts | 240 | rts |
231 | 241 | ||
232 | .gd_end: | 242 | .gd_end: |
diff --git a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S index 776e22a6c4..8e483d23ad 100644 --- a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S +++ b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S | |||
@@ -99,10 +99,14 @@ lcd_write_data: | |||
99 | .global lcd_grey_data | 99 | .global lcd_grey_data |
100 | .type lcd_grey_data,@function | 100 | .type lcd_grey_data,@function |
101 | 101 | ||
102 | /* The main loop assumes the buffers are in SDRAM. Otherwise the LCD | ||
103 | * controller timing won't be met at 124 MHz and graphical glitches | ||
104 | * will occur. */ | ||
105 | |||
102 | lcd_grey_data: | 106 | lcd_grey_data: |
103 | lea.l (-9*4, %sp), %sp | 107 | lea.l (-10*4, %sp), %sp |
104 | movem.l %d2-%d5/%a2-%a6, (%sp) /* free some registers */ | 108 | movem.l %d2-%d6/%a2-%a6, (%sp) /* free some registers */ |
105 | movem.l (9*4+4, %sp), %a0-%a2 /* values, phases, length */ | 109 | movem.l (10*4+4, %sp), %a0-%a2 /* values, phases, length */ |
106 | lea.l (%a1, %a2.l*4), %a2 /* end address */ | 110 | lea.l (%a1, %a2.l*4), %a2 /* end address */ |
107 | moveq #8, %d1 | 111 | moveq #8, %d1 |
108 | or.l %d1, (MBAR2+0xb4) /* A0 = 1 (data) */ | 112 | or.l %d1, (MBAR2+0xb4) /* A0 = 1 (data) */ |
@@ -142,9 +146,9 @@ lcd_grey_data: | |||
142 | bhi.s .g_hloop | 146 | bhi.s .g_hloop |
143 | 147 | ||
144 | .g_lloop: | 148 | .g_lloop: |
145 | movem.l (%a1), %d2-%d5 | 149 | movem.l (%a1), %d2-%d5 /* fetch 4 blocks of 4 pixel phases each */ |
146 | 150 | ||
147 | bclr.l #31, %d2 | 151 | bclr.l #31, %d2 /* calculate first pixel block */ |
148 | seq.b %d0 | 152 | seq.b %d0 |
149 | lsl.l #2, %d0 | 153 | lsl.l #2, %d0 |
150 | bclr.l #23, %d2 | 154 | bclr.l #23, %d2 |
@@ -156,23 +160,23 @@ lcd_grey_data: | |||
156 | bclr.l #7, %d2 | 160 | bclr.l #7, %d2 |
157 | seq.b %d0 | 161 | seq.b %d0 |
158 | lsr.l #6, %d0 | 162 | lsr.l #6, %d0 |
159 | move.w %d0, (%a3) | ||
160 | 163 | ||
161 | bclr.l #31, %d3 | 164 | move.w %d0, (%a3) /* write first block to LCD */ |
162 | seq.b %d0 | 165 | |
163 | lsl.l #2, %d0 | 166 | bclr.l #31, %d3 /* calculate second pixel block */ |
167 | seq.b %d6 | ||
168 | lsl.l #2, %d6 | ||
164 | bclr.l #23, %d3 | 169 | bclr.l #23, %d3 |
165 | seq.b %d0 | 170 | seq.b %d6 |
166 | lsl.l #2, %d0 | 171 | lsl.l #2, %d6 |
167 | bclr.l #15, %d3 | 172 | bclr.l #15, %d3 |
168 | seq.b %d0 | 173 | seq.b %d6 |
169 | lsl.l #2, %d0 | 174 | lsl.l #2, %d6 |
170 | bclr.l #7, %d3 | 175 | bclr.l #7, %d3 |
171 | seq.b %d0 | 176 | seq.b %d6 |
172 | lsr.l #6, %d0 | 177 | lsr.l #6, %d6 |
173 | move.w %d0, (%a3) | 178 | |
174 | 179 | bclr.l #31, %d4 /* calculate third pixel block */ | |
175 | bclr.l #31, %d4 | ||
176 | seq.b %d0 | 180 | seq.b %d0 |
177 | lsl.l #2, %d0 | 181 | lsl.l #2, %d0 |
178 | bclr.l #23, %d4 | 182 | bclr.l #23, %d4 |
@@ -184,9 +188,15 @@ lcd_grey_data: | |||
184 | bclr.l #7, %d4 | 188 | bclr.l #7, %d4 |
185 | seq.b %d0 | 189 | seq.b %d0 |
186 | lsr.l #6, %d0 | 190 | lsr.l #6, %d0 |
187 | move.w %d0, (%a3) | 191 | |
188 | 192 | move.w %d6, (%a3) /* write second block to LCD */ | |
189 | bclr.l #31, %d5 | 193 | |
194 | movem.l (%a0), %d6/%a4-%a6 /* fetch 4 blocks of 4 pixel values each */ | ||
195 | lea.l (16, %a0), %a0 | ||
196 | |||
197 | move.w %d0, (%a3) /* write third block to LCD */ | ||
198 | |||
199 | bclr.l #31, %d5 /* calculate fourth pixel block */ | ||
190 | seq.b %d0 | 200 | seq.b %d0 |
191 | lsl.l #2, %d0 | 201 | lsl.l #2, %d0 |
192 | bclr.l #23, %d5 | 202 | bclr.l #23, %d5 |
@@ -198,17 +208,17 @@ lcd_grey_data: | |||
198 | bclr.l #7, %d5 | 208 | bclr.l #7, %d5 |
199 | seq.b %d0 | 209 | seq.b %d0 |
200 | lsr.l #6, %d0 | 210 | lsr.l #6, %d0 |
201 | move.w %d0, (%a3) | 211 | |
202 | 212 | add.l %d6, %d2 /* calculate 4*4 new pixel phases */ | |
203 | movem.l (%a0), %d0/%a4-%a6 | 213 | add.l %a4, %d3 /* (packed addition) */ |
204 | lea.l (16, %a0), %a0 | ||
205 | add.l %d0, %d2 | ||
206 | add.l %a4, %d3 | ||
207 | add.l %a5, %d4 | 214 | add.l %a5, %d4 |
208 | add.l %a6, %d5 | 215 | add.l %a6, %d5 |
209 | movem.l %d2-%d5, (%a1) | 216 | |
217 | movem.l %d2-%d5, (%a1) /* store 4*4 new pixel phases */ | ||
210 | lea.l (16, %a1), %a1 | 218 | lea.l (16, %a1), %a1 |
211 | 219 | ||
220 | move.w %d0, (%a3) /* write fourth block to LCD */ | ||
221 | |||
212 | cmp.l %a1, %d1 /* go up to last line bound */ | 222 | cmp.l %a1, %d1 /* go up to last line bound */ |
213 | bhi.w .g_lloop | 223 | bhi.w .g_lloop |
214 | 224 | ||
@@ -239,8 +249,8 @@ lcd_grey_data: | |||
239 | bhi.s .g_tloop | 249 | bhi.s .g_tloop |
240 | 250 | ||
241 | .g_no_tail: | 251 | .g_no_tail: |
242 | movem.l (%sp), %d2-%d5/%a2-%a6 /* restore registers */ | 252 | movem.l (%sp), %d2-%d6/%a2-%a6 /* restore registers */ |
243 | lea.l (9*4, %sp), %sp | 253 | lea.l (10*4, %sp), %sp |
244 | rts | 254 | rts |
245 | 255 | ||
246 | .gd_end: | 256 | .gd_end: |