Fix graphical glitches occuring in the greyscale library on H1x0 and M5 at 124MHz. The main loop within lcd_grey_data() needed instruction reordering (interspersing lcd writes with memory accesses) to meed the LCD controller timing. Slight slowdown because of the extra register needed.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16091 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 81 insertions, 61 deletions

diff --git a/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S b/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S
index 0ec98e4589..0ec4f4b032 100644
--- a/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S
+++ b/firmware/target/coldfire/iaudio/m5/lcd-as-m5.S
@@ -87,10 +87,14 @@ lcd_write_data:
     .global     lcd_grey_data
     .type       lcd_grey_data,@function
 
+    /* The main loop assumes the buffers are in SDRAM. Otherwise the LCD
+     * controller timing won't be met at 124 MHz and graphical glitches 
+     * will occur. */
+
 lcd_grey_data:
-    lea.l   (-9*4, %sp), %sp
-    movem.l %d2-%d5/%a2-%a6, (%sp)  /* free some registers */
-    movem.l (9*4+4, %sp), %a0-%a2   /* values, phases, length */
+    lea.l   (-10*4, %sp), %sp
+    movem.l %d2-%d6/%a2-%a6, (%sp)  /* free some registers */
+    movem.l (10*4+4, %sp), %a0-%a2  /* values, phases, length */
     lea.l   (%a1, %a2.l*4), %a2     /* end address */
     lea     0xf0008002, %a3     /* LCD data port */
 
@@ -128,9 +132,9 @@ lcd_grey_data:
     bhi.s   .g_hloop
     
 .g_lloop:
-    movem.l (%a1), %d2-%d5
+    movem.l (%a1), %d2-%d5      /* fetch 4 blocks of 4 pixel phases each */
     
-    bclr.l  #31, %d2
+    bclr.l  #31, %d2            /* calculate first pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d2
@@ -142,23 +146,23 @@ lcd_grey_data:
     bclr.l  #7, %d2
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
 
-    bclr.l  #31, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    move.w  %d0, (%a3)          /* write first block to LCD */
+
+    bclr.l  #31, %d3            /* calculate second pixel block */
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #23, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #15, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #7, %d3
-    seq.b   %d0
-    lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    bclr.l  #31, %d4
+    seq.b   %d6
+    lsr.l   #6, %d6
+
+    bclr.l  #31, %d4            /* calculate third pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d4
@@ -170,9 +174,15 @@ lcd_grey_data:
     bclr.l  #7, %d4
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    bclr.l  #31, %d5
+
+    move.w  %d6, (%a3)          /* write second block to LCD */
+
+    movem.l (%a0), %d6/%a4-%a6  /* fetch 4 blocks of 4 pixel values each */
+    lea.l   (16, %a0), %a0
+
+    move.w  %d0, (%a3)          /* write third block to LCD */
+
+    bclr.l  #31, %d5            /* calculate fourth pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d5
@@ -184,20 +194,20 @@ lcd_grey_data:
     bclr.l  #7, %d5
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    movem.l (%a0), %d0/%a4-%a6
-    lea.l   (16, %a0), %a0
-    add.l   %d0, %d2
-    add.l   %a4, %d3
+
+    add.l   %d6, %d2            /* calculate 4*4 new pixel phases */
+    add.l   %a4, %d3            /* (packed addition) */
     add.l   %a5, %d4
     add.l   %a6, %d5
-    movem.l %d2-%d5, (%a1)
+
+    movem.l %d2-%d5, (%a1)      /* store 4*4 new pixel phases */
     lea.l   (16, %a1), %a1
 
+    move.w  %d0, (%a3)          /* write fourth block to LCD */
+
     cmp.l   %a1, %d1            /* go up to last line bound */
     bhi.w   .g_lloop
-    
+
     cmp.l   %a1, %a2
     bls.s   .g_no_tail
 
@@ -225,8 +235,8 @@ lcd_grey_data:
     bhi.s   .g_tloop
 
 .g_no_tail:
-    movem.l (%sp), %d2-%d5/%a2-%a6  /* restore registers */
-    lea.l   (9*4, %sp), %sp
+    movem.l (%sp), %d2-%d6/%a2-%a6  /* restore registers */
+    lea.l   (10*4, %sp), %sp
     rts
 
 .gd_end:
diff --git a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
index 776e22a6c4..8e483d23ad 100644
--- a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
+++ b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
@@ -99,10 +99,14 @@ lcd_write_data:
     .global     lcd_grey_data
     .type       lcd_grey_data,@function
 
+    /* The main loop assumes the buffers are in SDRAM. Otherwise the LCD
+     * controller timing won't be met at 124 MHz and graphical glitches 
+     * will occur. */
+
 lcd_grey_data:
-    lea.l   (-9*4, %sp), %sp
-    movem.l %d2-%d5/%a2-%a6, (%sp)  /* free some registers */
-    movem.l (9*4+4, %sp), %a0-%a2   /* values, phases, length */
+    lea.l   (-10*4, %sp), %sp
+    movem.l %d2-%d6/%a2-%a6, (%sp)  /* free some registers */
+    movem.l (10*4+4, %sp), %a0-%a2  /* values, phases, length */
     lea.l   (%a1, %a2.l*4), %a2     /* end address */
     moveq   #8, %d1
     or.l    %d1, (MBAR2+0xb4)   /* A0 = 1 (data) */
@@ -142,9 +146,9 @@ lcd_grey_data:
     bhi.s   .g_hloop
     
 .g_lloop:
-    movem.l (%a1), %d2-%d5
+    movem.l (%a1), %d2-%d5      /* fetch 4 blocks of 4 pixel phases each */
     
-    bclr.l  #31, %d2
+    bclr.l  #31, %d2            /* calculate first pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d2
@@ -156,23 +160,23 @@ lcd_grey_data:
     bclr.l  #7, %d2
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
 
-    bclr.l  #31, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    move.w  %d0, (%a3)          /* write first block to LCD */
+
+    bclr.l  #31, %d3            /* calculate second pixel block */
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #23, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #15, %d3
-    seq.b   %d0
-    lsl.l   #2, %d0
+    seq.b   %d6
+    lsl.l   #2, %d6
     bclr.l  #7, %d3
-    seq.b   %d0
-    lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    bclr.l  #31, %d4
+    seq.b   %d6
+    lsr.l   #6, %d6
+
+    bclr.l  #31, %d4            /* calculate third pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d4
@@ -184,9 +188,15 @@ lcd_grey_data:
     bclr.l  #7, %d4
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    bclr.l  #31, %d5
+
+    move.w  %d6, (%a3)          /* write second block to LCD */
+
+    movem.l (%a0), %d6/%a4-%a6  /* fetch 4 blocks of 4 pixel values each */
+    lea.l   (16, %a0), %a0
+
+    move.w  %d0, (%a3)          /* write third block to LCD */
+
+    bclr.l  #31, %d5            /* calculate fourth pixel block */
     seq.b   %d0
     lsl.l   #2, %d0
     bclr.l  #23, %d5
@@ -198,17 +208,17 @@ lcd_grey_data:
     bclr.l  #7, %d5
     seq.b   %d0
     lsr.l   #6, %d0
-    move.w  %d0, (%a3)
-    
-    movem.l (%a0), %d0/%a4-%a6
-    lea.l   (16, %a0), %a0
-    add.l   %d0, %d2
-    add.l   %a4, %d3
+
+    add.l   %d6, %d2            /* calculate 4*4 new pixel phases */
+    add.l   %a4, %d3            /* (packed addition) */
     add.l   %a5, %d4
     add.l   %a6, %d5
-    movem.l %d2-%d5, (%a1)
+
+    movem.l %d2-%d5, (%a1)      /* store 4*4 new pixel phases */
     lea.l   (16, %a1), %a1
 
+    move.w  %d0, (%a3)          /* write fourth block to LCD */
+
     cmp.l   %a1, %d1            /* go up to last line bound */
     bhi.w   .g_lloop
     
@@ -239,8 +249,8 @@ lcd_grey_data:
     bhi.s   .g_tloop
 
 .g_no_tail:
-    movem.l (%sp), %d2-%d5/%a2-%a6  /* restore registers */
-    lea.l   (9*4, %sp), %sp
+    movem.l (%sp), %d2-%d6/%a2-%a6  /* restore registers */
+    lea.l   (10*4, %sp), %sp
     rts
 
 .gd_end: