diff options
-rw-r--r-- | firmware/export/dm320.h | 99 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c | 82 |
2 files changed, 151 insertions, 30 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index a70083331e..311ac01f29 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -411,9 +411,9 @@ | |||
411 | #define IO_CLK_LPCTL0 DM320_REG(0x089E) | 411 | #define IO_CLK_LPCTL0 DM320_REG(0x089E) |
412 | #define IO_CLK_LPCTL1 DM320_REG(0x08A0) | 412 | #define IO_CLK_LPCTL1 DM320_REG(0x08A0) |
413 | #define IO_CLK_OSEL DM320_REG(0x08A2) | 413 | #define IO_CLK_OSEL DM320_REG(0x08A2) |
414 | #define IO_CLK_00DIV DM320_REG(0x08A4) | 414 | #define IO_CLK_O0DIV DM320_REG(0x08A4) |
415 | #define IO_CLK_O1DIV DM320_REG(0x08A6) | 415 | #define IO_CLK_O1DIV DM320_REG(0x08A6) |
416 | #define IO_CLK_02DIV DM320_REG(0x08A8) | 416 | #define IO_CLK_O2DIV DM320_REG(0x08A8) |
417 | #define IO_CLK_PWM0C DM320_REG(0x08AA) | 417 | #define IO_CLK_PWM0C DM320_REG(0x08AA) |
418 | #define IO_CLK_PWM0H DM320_REG(0x08AC) | 418 | #define IO_CLK_PWM0H DM320_REG(0x08AC) |
419 | #define IO_CLK_PWM1C DM320_REG(0x08AE) | 419 | #define IO_CLK_PWM1C DM320_REG(0x08AE) |
@@ -838,6 +838,15 @@ | |||
838 | #define CLK_MOD2_TMR0 (1 << 1) | 838 | #define CLK_MOD2_TMR0 (1 << 1) |
839 | #define CLK_MOD2_WDT (1 << 0) | 839 | #define CLK_MOD2_WDT (1 << 0) |
840 | 840 | ||
841 | #define CLK_SEL1_OSD (1 << 12) | ||
842 | #define CLK_SEL1_CCD (1 << 8) | ||
843 | #define CLK_SEL1_VENCPLL (1 << 4) | ||
844 | #define CLK_SEL1_VENC(x) (x << 0) | ||
845 | |||
846 | #define CLK_OSEL_O2SEL(x) (x << 8) | ||
847 | #define CLK_OSEL_O1SEL(x) (x << 4) | ||
848 | #define CLK_OSEL_O0SEL(x) (x << 0) | ||
849 | |||
841 | /* | 850 | /* |
842 | * IO_EINTx bits | 851 | * IO_EINTx bits |
843 | */ | 852 | */ |
@@ -905,4 +914,90 @@ | |||
905 | #define INTR_IRQ1_EXT2 INTR_EINT1_EXT2 | 914 | #define INTR_IRQ1_EXT2 INTR_EINT1_EXT2 |
906 | #define INTR_IRQ1_EXT7 INTR_EINT1_EXT7 | 915 | #define INTR_IRQ1_EXT7 INTR_EINT1_EXT7 |
907 | 916 | ||
917 | /* | ||
918 | * HPIBCTL bits | ||
919 | */ | ||
920 | #define HPIBCTL_DBIO (1 << 10) | ||
921 | #define HPIBCTL_DHOLD (1 << 9) | ||
922 | #define HPIBCTL_DRST (1 << 8) | ||
923 | #define HPIBCTL_DINT0 (1 << 7) | ||
924 | #define HPIBCTL_EXCHG (1 << 5) | ||
925 | #define HPIBCTL_HPNMI (1 << 3) | ||
926 | #define HPIBCTL_HPIEN (1 << 0) | ||
927 | |||
928 | /* | ||
929 | * Video Encoder bits | ||
930 | */ | ||
931 | #define VENC_VMOD_VDMD(x) (x << 12) | ||
932 | #define VENC_VMOD_ITLC (1 << 10) | ||
933 | #define VENC_VMOD_CBTYP (1 << 9) | ||
934 | #define VENC_VMOD_CBMD (1 << 8) | ||
935 | #define VENC_VMOD_NTPLS(x) (x << 6) | ||
936 | #define VENC_VMOD_SLAVE (1 << 5) | ||
937 | #define VENC_VMOD_VMD (1 << 4) | ||
938 | #define VENC_VMOD_BLNK (1 << 3) | ||
939 | #define VENC_VMOD_DACPD (1 << 2) | ||
940 | #define VENC_VMOD_VIE (1 << 1) | ||
941 | #define VENC_VMOD_VENC (1 << 0) | ||
942 | |||
943 | #define VENC_VDCTL_VCLKP (1 << 14) | ||
944 | #define VENC_VDCTL_VCLKE (1 << 13) | ||
945 | #define VENC_VDCTL_VCLKZ (1 << 12) | ||
946 | #define VENC_VDCTL_DOMD(x) (x << 4) | ||
947 | #define VENC_VDCTL_YCDC (1 << 2) | ||
948 | #define VENC_VDCTL_INPTRU (1 << 1) | ||
949 | #define VENC_VDCTL_YCDIR (1 << 0) | ||
950 | |||
951 | #define VENC_VDPRO_PFLTY(x) (x << 12) | ||
952 | #define VENC_VDPRO_PFLTR (1 << 11) | ||
953 | #define VENC_VDPRO_YCDLY(x) (x << 8) | ||
954 | #define VENC_VDPRO_RGBMAT (1 << 7) | ||
955 | #define VENC_VDPRO_ATRGB (1 << 6) | ||
956 | #define VENC_VDPRO_ATYCC (1 << 5) | ||
957 | #define VENC_VDPRO_ATCOM (1 << 4) | ||
958 | #define VENC_VDPRO_STUP (1 << 3) | ||
959 | #define VENC_VDPRO_CRCUT (1 << 2) | ||
960 | #define VENC_VDPRO_CUPS (1 << 1) | ||
961 | #define VENC_VDPRO_YUPS (1 << 0) | ||
962 | |||
963 | #define VENC_SYNCCTL_EXFEN (1 << 12) | ||
964 | #define VENC_SYNCCTL_EXFIV (1 << 11) | ||
965 | #define VENC_SYNCCTL_EXSYNC (1 << 10) | ||
966 | #define VENC_SYNCCTL_EXVIV (1 << 9) | ||
967 | #define VENC_SYNCCTL_EXHIV (1 << 8) | ||
968 | #define VENC_SYNCCTL_CSP (1 << 7) | ||
969 | #define VENC_SYNCCTL_CSE (1 << 6) | ||
970 | #define VENC_SYNCCTL_SYSW (1 << 5) | ||
971 | #define VENC_SYNCCTL_VSYNCS (1 << 4) | ||
972 | #define VENC_SYNCCTL_VPL (1 << 3) | ||
973 | #define VENC_SYNCCTL_HPL (1 << 2) | ||
974 | #define VENC_SYNCCTL_SYE (1 << 1) | ||
975 | #define VENC_SYNCCTL_SYDIR (1 << 0) | ||
976 | |||
977 | #define VENC_RGBCTL_IRONM (1 << 11) | ||
978 | #define VENC_RGBCTL_DFLTR (1 << 10) | ||
979 | #define VENC_RGBCTL_DFLTS(x) (x << 8) | ||
980 | #define VENC_RGBCTL_RGBEF(x) (x << 4) | ||
981 | #define VENC_RGBCTL_RGBOF(x) (x << 0) | ||
982 | |||
983 | #define VENC_RGBCLP_UCLIP(x) (x << 8) | ||
984 | #define VENC_RGBCLP_OFST(x) (x << 0) | ||
985 | |||
986 | #define VENC_LCDOUT_FIDS (1 << 8) | ||
987 | #define VENC_LCDOUT_FIDP (1 << 7) | ||
988 | #define VENC_LCDOUT_PWMP (1 << 6) | ||
989 | #define VENC_LCDOUT_PWME (1 << 5) | ||
990 | #define VENC_LCDOUT_ACE (1 << 4) | ||
991 | #define VENC_LCDOUT_BRP (1 << 3) | ||
992 | #define VENC_LCDOUT_BRE (1 << 2) | ||
993 | #define VENC_LCDOUT_OEP (1 << 1) | ||
994 | #define VENC_LCDOUT_OEE (1 << 0) | ||
995 | |||
996 | #define VENC_DCLKCTL_DOFST(x) (x << 12) | ||
997 | #define VENC_DCLKCTL_DCKEC (1 << 11) | ||
998 | #define VENC_DCLKCTL_DCKME (1 << 10) | ||
999 | #define VENC_DCLKCTL_DCKOH (1 << 9) | ||
1000 | #define VENC_DCLKCTL_DCKIH (1 << 8) | ||
1001 | #define VENC_DCLKCTL_DCKPW(x) (x << 0) | ||
1002 | |||
908 | #endif | 1003 | #endif |
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c index 14a9febe59..5ed4054c8c 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c | |||
@@ -46,8 +46,7 @@ int lcd_default_contrast(void) | |||
46 | 46 | ||
47 | void lcd_set_contrast(int val) | 47 | void lcd_set_contrast(int val) |
48 | { | 48 | { |
49 | /* iirc there is an ltv250qv command to do this */ | 49 | /* find S6F2002 controller datasheet first */ |
50 | #warning function not implemented | ||
51 | (void)val; | 50 | (void)val; |
52 | } | 51 | } |
53 | 52 | ||
@@ -61,7 +60,6 @@ void lcd_set_flip(bool yesno) { | |||
61 | /* TODO: */ | 60 | /* TODO: */ |
62 | } | 61 | } |
63 | 62 | ||
64 | |||
65 | /* LTV250QV panel functions */ | 63 | /* LTV250QV panel functions */ |
66 | #ifdef ENABLE_DISPLAY_FUNCS | 64 | #ifdef ENABLE_DISPLAY_FUNCS |
67 | static void lcd_write_reg(unsigned char reg, unsigned short val) | 65 | static void lcd_write_reg(unsigned char reg, unsigned short val) |
@@ -161,14 +159,12 @@ static void lcd_display_on(void) | |||
161 | lcd_write_reg(9, 0xA55); | 159 | lcd_write_reg(9, 0xA55); |
162 | lcd_write_reg(10, 0x111A); | 160 | lcd_write_reg(10, 0x111A); |
163 | sleep_ms(10); | 161 | sleep_ms(10); |
164 | |||
165 | /*TODO: other stuff! */ | ||
166 | 162 | ||
167 | /* tell that we're on now */ | 163 | /* tell that we're on now */ |
168 | display_on = true; | 164 | display_on = true; |
169 | } | 165 | } |
170 | 166 | ||
171 | static void lcd_display_off(void) | 167 | void lcd_display_off(void) |
172 | { | 168 | { |
173 | display_on = false; | 169 | display_on = false; |
174 | 170 | ||
@@ -250,6 +246,48 @@ void lcd_init_device(void) | |||
250 | 246 | ||
251 | /* Clear the Frame */ | 247 | /* Clear the Frame */ |
252 | memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); | 248 | memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); |
249 | |||
250 | #ifdef ENABLE_DISPLAY_FUNCS | ||
251 | lcd_display_on(); | ||
252 | |||
253 | /* Set OSD clock */ | ||
254 | IO_CLK_MOD1 &= ~(CLK_MOD1_VENC | CLK_MOD1_OSD); /* disable OSD clock and VENC clock */ | ||
255 | IO_CLK_O2DIV = 3; | ||
256 | |||
257 | IO_CLK_OSEL &= ~CLK_OSEL_O2SEL(0xF); /* reset 'General purpose clock output (GIO26, GIO34)' and */ | ||
258 | IO_CLK_OSEL |= CLK_OSEL_O2SEL(4); /* set to 'PLLIN clock' */ | ||
259 | |||
260 | IO_CLK_SEL1 |= (CLK_SEL1_OSD | CLK_SEL1_VENC(7)); /* set to 'GP clock output 2 (GIO26, GIO34)' and turn on 'VENC clock' */ | ||
261 | IO_CLK_MOD1 |= (CLK_MOD1_VENC | CLK_MOD1_OSD); /* enable OSD clock and VENC clock */ | ||
262 | |||
263 | /* Set LCD values in Video Encoder */ | ||
264 | IO_VID_ENC_VMOD &= 0x8800; /* Clear all values */ | ||
265 | IO_VID_ENC_VMOD |= (VENC_VMOD_DACPD | VENC_VMOD_VMD | VENC_VMOD_ITLC | VENC_VMOD_VDMD(2)); /* set mode to RGB666 parallel 16 bit */ | ||
266 | IO_VID_ENC_VDTL &= 8FE8; /* Clear all values */ | ||
267 | IO_VID_ENC_VDCTL |= (VENC_VDCTL_VCLKP | VENC_VDCTL_DOMD(2)), | ||
268 | IO_VID_ENC_VPRO = VENC_VDPRO_PFLTR; | ||
269 | IO_VID_ENC_SYNCCTL &= 0xE000; /* Clear all values */ | ||
270 | IO_VID_ENC_SYNCCTL |= (VENC_SYNCCTL_VPL | VENC_SYNCCTL_HPL); | ||
271 | IO_VID_ENC_HSDLY = 0; | ||
272 | IO_VID_ENC_HSPLS = 0x12; | ||
273 | IO_VID_ENC_HSTART = 0x1B; | ||
274 | IO_VID_ENC_HVALID = 0x140; | ||
275 | IO_VID_ENC_HINT = 0x168; | ||
276 | IO_VID_ENC_VSDLY = 0; | ||
277 | IO_VID_ENC_VSPLS = 3; | ||
278 | IO_VID_ENC_VSTART = 5; | ||
279 | IO_VID_ENC_VVALID = 0xF0; | ||
280 | IO_VID_ENC_VINT = 0x118; | ||
281 | IO_VID_ENC_RGBCTL &= 0x088; /* Clear all values */ | ||
282 | IO_VID_ENC_RGBCTL |= VENC_RGBCTL_DFLTR; | ||
283 | IO_VID_ENC_RGBCLP = VENC_RGBCLP_UCLIP(0xFF); | ||
284 | IO_VID_ENC_LCDOUT &= 0xFE00; /* Clear all values */ | ||
285 | IO_VID_ENC_LCDOUT |= (VENC_LCDOUT_OEE | VENC_LCDOUT_FIDS); | ||
286 | IO_VID_ENC_DCLKCTL &= 0xC0C0; /* Clear all values */ | ||
287 | IO_VID_ENC_DCLKCTL |= VENC_DCLKCTL_DCKEC; | ||
288 | IO_VID_ENC_DCLKPTN0 = 1; | ||
289 | DM320_REG(0x0864) = 0; /* ???? */ | ||
290 | #endif | ||
253 | 291 | ||
254 | IO_OSD_MODE = 0x00ff; | 292 | IO_OSD_MODE = 0x00ff; |
255 | IO_OSD_VIDWINMD = 0x0002; | 293 | IO_OSD_VIDWINMD = 0x0002; |
@@ -264,35 +302,23 @@ void lcd_init_device(void) | |||
264 | IO_OSD_OSDWIN0ADL = addr & 0xFFFF; | 302 | IO_OSD_OSDWIN0ADL = addr & 0xFFFF; |
265 | 303 | ||
266 | #ifndef ZEN_VISION | 304 | #ifndef ZEN_VISION |
267 | IO_OSD_BASEPX=26; | 305 | IO_OSD_BASEPX = 26; |
268 | IO_OSD_BASEPY=5; | 306 | IO_OSD_BASEPY = 5; |
269 | #else | 307 | #else |
270 | IO_OSD_BASEPX=80; | 308 | IO_OSD_BASEPX = 80; |
271 | IO_OSD_BASEPY=0; | 309 | IO_OSD_BASEPY = 0; |
272 | #endif | 310 | #endif |
273 | 311 | ||
274 | IO_OSD_OSDWIN0XP = 0; | 312 | IO_OSD_OSDWIN0XP = 0; |
275 | IO_OSD_OSDWIN0YP = 0; | 313 | IO_OSD_OSDWIN0YP = 0; |
276 | IO_OSD_OSDWIN0XL = LCD_WIDTH; | 314 | IO_OSD_OSDWIN0XL = LCD_WIDTH; |
277 | IO_OSD_OSDWIN0YL = LCD_HEIGHT; | 315 | IO_OSD_OSDWIN0YL = LCD_HEIGHT; |
278 | #if 0 | 316 | |
279 | /*TODO: set LCD clock! */ | 317 | #ifdef ENABLE_DISPLAY_FUNCS |
280 | IO_CLK_MOD1 &= ~0x18; /* disable OSD clock and VENC clock */ | 318 | IO_VID_ENC_VDCTL |= VENC_VDCTL_VCLKE; /* Enable VCLK */ |
281 | IO_CLK_02DIV = 3; | 319 | IO_VID_ENC_VMOD |= VENC_VMOD_VENC; /* Enable video encoder */ |
282 | 320 | IO_VID_ENC_SYNCCTL |= VENC_SYNCCTL_SYE; /* Enable sync output */ | |
283 | /* reset 'General purpose clock output (GIO26, GIO34)' and set to 'PLLIN | 321 | IO_VID_ENC_VDCTL &= ~VENC_VDCTL_DOMD(3); /* Normal digital data output */ |
284 | clock' */ | ||
285 | IO_CLK_OSEL = (IO_CLK_OSEL & ~0xF00) | 0x400; | ||
286 | |||
287 | /* set to 'GP clock output 2 (GIO26, GIO34)' and turn on 'VENC clock' */ | ||
288 | IO_CLK_SEL1 = (IO_CLK_SEL1 | 7) | 0x1000; | ||
289 | IO_CLK_MOD1 |= 0x18; /* enable OSD clock and VENC clock */ | ||
290 | |||
291 | /* Set LCD values in OSD */ | ||
292 | /* disable NTSC/PAL encoder & set mode to RGB666 parallel 18 bit */ | ||
293 | IO_VID_ENC_VMOD = ( ( (IO_VID_ENC_VMOD & 0xFFFF8C00) | 0x14) | 0x2400 ); | ||
294 | IO_VID_ENC_VDCTL = ( ( (IO_VID_ENC_VDCTL & 0xFFFFCFE8) | 0x20) | 0x4000 ); | ||
295 | /* TODO: finish this... */ | ||
296 | #endif | 322 | #endif |
297 | } | 323 | } |
298 | 324 | ||