regtools: add headergen_v2

This new header generator works differently from the previous one:
- it uses the new format
- the generated macro follow a different style (see below)
- the generated macro are highly documented!
- it supports SCT-style platform or RMW-style ones

Compared to the old style, the new one generate a big set of macros per
register/field/enum (loosely related to iohw.h from Embedded C spec). The user
then calls generic (names are customizable) macros to perform operations:

reg_read(REG_A)
reg_read(REG_B(3))
reg_read_field(REG_A, FIELD_X)
reg_read_field(REG_B(3), COOL_FIELD)
reg_write(REG_A, 0x42)
reg_write_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ))
reg_write_fielc(REG_B(3), COOL_FIELD_V(I_AM_COOL), BLA(42))

the following use RMW or SET/CLR variants, depending on target:
reg_set_field(REG_A, FLAG_U, FLAG_V)
reg_clr_field(REG_A, FIELD_X, FIELD_Y, IRQ)
reg_clr_field(REG_B(3), COOL_FIELD, BLA)

the following does clear followed by set, on SET/CLR targets:
reg_cs(REG_A, 0xff, 0x42)
reg_cs(REG_B(3), 0xaa, 0x55)
reg_cs_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ))
reg_cs_field(REG_B(3), COOL_FIELD_V(I_AM_COOL))

The generator code is pretty long but has lots of documentation and lots of
macro names can be customized.

Change-Id: I5d6c5ec2406e58b5da11a5240c3a409a5bb5239a

1 files changed, 20 insertions, 11 deletions

diff --git a/utils/regtools/desc/regs-vsoc2000.xml b/utils/regtools/desc/regs-vsoc2000.xml
index 858c13254c..db51e8eb98 100644
--- a/utils/regtools/desc/regs-vsoc2000.xml
+++ b/utils/regtools/desc/regs-vsoc2000.xml
@@ -66,16 +66,30 @@
                 <address>0x10</address>
             </instance>
             <register>
+                <access>read-only</access>
                 <field>
                     <name>STATUS</name>
-                    <desc>Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it. Secured interrupts can only be cleared or polled by secured processors (non-secure will always read 0 for those).</desc>
+                    <desc>Bit is set to 1 is the interrupt is pending. Secured interrupts can only be polled by secured processors (non-secure will always read 0 for those).</desc>
+                    <position>0</position>
+                    <width>32</width>
+                </field>
+            </register>
+        </node>
+        <node>
+            <name>clear</name>
+            <title>Interrupt clear register</title>
+            <instance>
+                <name>CLEAR</name>
+                <address>0x14</address>
+            </instance>
+            <register>
+                <access>write-only</access>
+                <field>
+                    <name>CLEAR</name>
+                    <desc>Write 1 to clear a pending interrupt. Secured interrupts can only be cleared by secured processors.</desc>
                     <position>0</position>
                     <width>32</width>
                 </field>
-                <variant>
-                    <type>clr</type>
-                    <offset>8</offset>
-                </variant>
             </register>
         </node>
         <node>
@@ -335,7 +349,7 @@
                         <offset>8</offset>
                     </variant>
                     <variant>
-                        <type>mask</type>
+                        <type>tog</type>
                         <offset>12</offset>
                     </variant>
                 </register>
@@ -391,11 +405,6 @@
             <register>
                 <width>8</width>
                 <access>read-only</access>
-                <variant>
-                    <type>debug</type>
-                    <offset>4</offset>
-                    <access>write-only</access>
-                </variant>
             </register>
         </node>
     </node>