From e62203aac1876987e52f3be9db079bd4ad133b28 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Mon, 16 May 2016 00:08:52 +0100 Subject: regtools: add headergen_v2 This new header generator works differently from the previous one: - it uses the new format - the generated macro follow a different style (see below) - the generated macro are highly documented! - it supports SCT-style platform or RMW-style ones Compared to the old style, the new one generate a big set of macros per register/field/enum (loosely related to iohw.h from Embedded C spec). The user then calls generic (names are customizable) macros to perform operations: reg_read(REG_A) reg_read(REG_B(3)) reg_read_field(REG_A, FIELD_X) reg_read_field(REG_B(3), COOL_FIELD) reg_write(REG_A, 0x42) reg_write_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ)) reg_write_fielc(REG_B(3), COOL_FIELD_V(I_AM_COOL), BLA(42)) the following use RMW or SET/CLR variants, depending on target: reg_set_field(REG_A, FLAG_U, FLAG_V) reg_clr_field(REG_A, FIELD_X, FIELD_Y, IRQ) reg_clr_field(REG_B(3), COOL_FIELD, BLA) the following does clear followed by set, on SET/CLR targets: reg_cs(REG_A, 0xff, 0x42) reg_cs(REG_B(3), 0xaa, 0x55) reg_cs_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ)) reg_cs_field(REG_B(3), COOL_FIELD_V(I_AM_COOL)) The generator code is pretty long but has lots of documentation and lots of macro names can be customized. Change-Id: I5d6c5ec2406e58b5da11a5240c3a409a5bb5239a --- utils/regtools/desc/regs-vsoc2000.xml | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) (limited to 'utils/regtools/desc') diff --git a/utils/regtools/desc/regs-vsoc2000.xml b/utils/regtools/desc/regs-vsoc2000.xml index 858c13254c..db51e8eb98 100644 --- a/utils/regtools/desc/regs-vsoc2000.xml +++ b/utils/regtools/desc/regs-vsoc2000.xml @@ -66,16 +66,30 @@
0x10
+ read-only STATUS - Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it. Secured interrupts can only be cleared or polled by secured processors (non-secure will always read 0 for those). + Bit is set to 1 is the interrupt is pending. Secured interrupts can only be polled by secured processors (non-secure will always read 0 for those). + 0 + 32 + + + + + clear + Interrupt clear register + + CLEAR +
0x14
+
+ + write-only + + CLEAR + Write 1 to clear a pending interrupt. Secured interrupts can only be cleared by secured processors. 0 32 - - clr - 8 -
@@ -335,7 +349,7 @@ 8 - mask + tog 12 @@ -391,11 +405,6 @@ 8 read-only - - debug - 4 - write-only - -- cgit v1.2.3