hwstub: add the possibility to flush caches before exec

This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h

Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e

1 files changed, 6 insertions, 0 deletions

diff --git a/utils/hwstub/stub/jz4760b/target-config.h b/utils/hwstub/stub/jz4760b/target-config.h
index fa018c14dc..681e17e6f6 100644
--- a/utils/hwstub/stub/jz4760b/target-config.h
+++ b/utils/hwstub/stub/jz4760b/target-config.h
@@ -3,6 +3,12 @@
 #define TCSM0_SIZE      0x4000
 #define CPU_MIPS
 #define STACK_SIZE      0x300
+#define DCACHE_SIZE     0x4000 /* 16 kB */
+#define DCACHE_LINE_SIZE    0x20   /* 32 B */
+#define ICACHE_SIZE     0x4000 /* 16 kB */
+#define ICACHE_LINE_SIZE    0x20   /* 32 B */
+/* we need to flush caches before executing */
+#define CONFIG_FLUSH_CACHES
 
 /* something provides define
  * #define mips 1